fsl-lx2160a-bluebox3.dts (11250B)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2// 3// Device Tree file for LX2160A BLUEBOX3 4// 5// Copyright 2020-2021 NXP 6 7/dts-v1/; 8 9#include "fsl-lx2160a.dtsi" 10 11/ { 12 model = "NXP Layerscape LX2160ABLUEBOX3"; 13 compatible = "fsl,lx2160a-bluebox3", "fsl,lx2160a"; 14 15 aliases { 16 crypto = &crypto; 17 mmc0 = &esdhc0; 18 mmc1 = &esdhc1; 19 serial0 = &uart0; 20 }; 21 22 chosen { 23 stdout-path = "serial0:115200n8"; 24 }; 25 26 sb_3v3: regulator-sb3v3 { 27 compatible = "regulator-fixed"; 28 regulator-name = "MC34717-3.3VSB"; 29 regulator-min-microvolt = <3300000>; 30 regulator-max-microvolt = <3300000>; 31 regulator-boot-on; 32 regulator-always-on; 33 }; 34}; 35 36&can0 { 37 status = "okay"; 38 39 can-transceiver { 40 max-bitrate = <5000000>; 41 }; 42}; 43 44&can1 { 45 status = "okay"; 46 47 can-transceiver { 48 max-bitrate = <5000000>; 49 }; 50}; 51 52&crypto { 53 status = "okay"; 54}; 55 56&dpmac5 { 57 phy-handle = <&aqr113c_phy1>; 58 phy-mode = "usxgmii"; 59 managed = "in-band-status"; 60}; 61 62&dpmac6 { 63 phy-handle = <&aqr113c_phy2>; 64 phy-mode = "usxgmii"; 65 managed = "in-band-status"; 66}; 67 68&dpmac9 { 69 phy-handle = <&aqr113c_phy3>; 70 phy-mode = "usxgmii"; 71 managed = "in-band-status"; 72}; 73 74&dpmac10 { 75 phy-handle = <&aqr113c_phy4>; 76 phy-mode = "usxgmii"; 77 managed = "in-band-status"; 78}; 79 80&dpmac17 { 81 phy-mode = "rgmii"; 82 status = "okay"; 83 84 fixed-link { 85 speed = <1000>; 86 full-duplex; 87 }; 88}; 89 90&dpmac18 { 91 phy-mode = "rgmii"; 92 status = "okay"; 93 94 fixed-link { 95 speed = <1000>; 96 full-duplex; 97 }; 98}; 99 100&emdio1 { 101 status = "okay"; 102 103 aqr113c_phy2: ethernet-phy@0 { 104 compatible = "ethernet-phy-ieee802.3-c45"; 105 reg = <0x0>; 106 /* IRQ_10G_PHY2 */ 107 interrupts-extended = <&extirq 3 IRQ_TYPE_LEVEL_LOW>; 108 }; 109 110 aqr113c_phy1: ethernet-phy@8 { 111 compatible = "ethernet-phy-ieee802.3-c45"; 112 reg = <0x8>; 113 /* IRQ_10G_PHY1 */ 114 interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>; 115 }; 116 117 sw1_mii3_phy: ethernet-phy@5 { 118 /* AR8035 */ 119 compatible = "ethernet-phy-id004d.d072"; 120 reg = <0x5>; 121 interrupts-extended = <&extirq 6 IRQ_TYPE_LEVEL_LOW>; 122 }; 123 124 sw2_mii3_phy: ethernet-phy@6 { 125 /* AR8035 */ 126 compatible = "ethernet-phy-id004d.d072"; 127 reg = <0x6>; 128 interrupts-extended = <&extirq 7 IRQ_TYPE_LEVEL_LOW>; 129 }; 130}; 131 132&emdio2 { 133 status = "okay"; 134 135 aqr113c_phy4: ethernet-phy@0 { 136 compatible = "ethernet-phy-ieee802.3-c45"; 137 reg = <0x0>; 138 /* IRQ_10G_PHY4 */ 139 interrupts-extended = <&extirq 5 IRQ_TYPE_LEVEL_LOW>; 140 }; 141 142 aqr113c_phy3: ethernet-phy@8 { 143 compatible = "ethernet-phy-ieee802.3-c45"; 144 reg = <0x8>; 145 /* IRQ_10G_PHY3 */ 146 interrupts-extended = <&extirq 4 IRQ_TYPE_LEVEL_LOW>; 147 }; 148}; 149 150&esdhc0 { 151 sd-uhs-sdr104; 152 sd-uhs-sdr50; 153 sd-uhs-sdr25; 154 sd-uhs-sdr12; 155 status = "okay"; 156}; 157 158&esdhc1 { 159 mmc-hs200-1_8v; 160 mmc-hs400-1_8v; 161 bus-width = <8>; 162 status = "okay"; 163}; 164 165&fspi { 166 status = "okay"; 167 168 mt35xu512aba0: flash@0 { 169 compatible = "jedec,spi-nor"; 170 #address-cells = <1>; 171 #size-cells = <1>; 172 reg = <0>; 173 m25p,fast-read; 174 spi-max-frequency = <50000000>; 175 spi-rx-bus-width = <8>; 176 spi-tx-bus-width = <8>; 177 }; 178 179 mt35xu512aba1: flash@1 { 180 compatible = "jedec,spi-nor"; 181 #address-cells = <1>; 182 #size-cells = <1>; 183 reg = <1>; 184 m25p,fast-read; 185 spi-max-frequency = <50000000>; 186 spi-rx-bus-width = <8>; 187 spi-tx-bus-width = <8>; 188 }; 189}; 190 191&i2c0 { 192 status = "okay"; 193 194 i2c-mux@77 { 195 compatible = "nxp,pca9547"; 196 reg = <0x77>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 200 i2c@2 { 201 #address-cells = <1>; 202 #size-cells = <0>; 203 reg = <0x2>; 204 205 power-monitor@40 { 206 compatible = "ti,ina220"; 207 reg = <0x40>; 208 shunt-resistor = <500>; 209 }; 210 }; 211 212 i2c@3 { 213 #address-cells = <1>; 214 #size-cells = <0>; 215 reg = <0x3>; 216 217 temp2: temperature-sensor@48 { 218 compatible = "nxp,sa56004"; 219 reg = <0x48>; 220 vcc-supply = <&sb_3v3>; 221 #thermal-sensor-cells = <1>; 222 }; 223 224 temp1: temperature-sensor@4c { 225 compatible = "nxp,sa56004"; 226 reg = <0x4c>; 227 vcc-supply = <&sb_3v3>; 228 #thermal-sensor-cells = <1>; 229 }; 230 }; 231 232 i2c@4 { 233 #address-cells = <1>; 234 #size-cells = <0>; 235 reg = <0x4>; 236 237 rtc@51 { 238 compatible = "nxp,pcf2129"; 239 reg = <0x51>; 240 interrupts-extended = <&extirq 11 IRQ_TYPE_LEVEL_LOW>; 241 }; 242 }; 243 244 i2c@7 { 245 #address-cells = <1>; 246 #size-cells = <0>; 247 reg = <0x7>; 248 249 i2c-mux@75 { 250 compatible = "nxp,pca9547"; 251 reg = <0x75>; 252 #address-cells = <1>; 253 #size-cells = <0>; 254 255 i2c@0 { 256 #address-cells = <1>; 257 #size-cells = <0>; 258 reg = <0x0>; 259 260 spi_bridge: spi@28 { 261 compatible = "nxp,sc18is602b"; 262 reg = <0x28>; 263 #address-cells = <1>; 264 #size-cells = <0>; 265 }; 266 }; 267 }; 268 }; 269 }; 270}; 271 272&i2c5 { 273 status = "okay"; 274 275 i2c-mux@77 { 276 compatible = "nxp,pca9846"; 277 reg = <0x77>; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 281 i2c@1 { 282 #address-cells = <1>; 283 #size-cells = <0>; 284 reg = <0x1>; 285 286 /* The I2C multiplexer and temperature sensors are on 287 * the T6 riser card. 288 */ 289 i2c-mux@70 { 290 compatible = "nxp,pca9548"; 291 reg = <0x70>; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 295 i2c@6 { 296 #address-cells = <1>; 297 #size-cells = <0>; 298 reg = <0x6>; 299 300 q12: temperature-sensor@4c { 301 compatible = "nxp,sa56004"; 302 reg = <0x4c>; 303 vcc-supply = <&sb_3v3>; 304 #thermal-sensor-cells = <1>; 305 }; 306 }; 307 308 i2c@7 { 309 #address-cells = <1>; 310 #size-cells = <0>; 311 reg = <0x7>; 312 313 q11: temperature-sensor@4c { 314 compatible = "nxp,sa56004"; 315 reg = <0x4c>; 316 vcc-supply = <&sb_3v3>; 317 #thermal-sensor-cells = <1>; 318 }; 319 320 q13: temperature-sensor@48 { 321 compatible = "nxp,sa56004"; 322 reg = <0x48>; 323 vcc-supply = <&sb_3v3>; 324 #thermal-sensor-cells = <1>; 325 }; 326 327 q14: temperature-sensor@4a { 328 compatible = "nxp,sa56004"; 329 reg = <0x4a>; 330 vcc-supply = <&sb_3v3>; 331 #thermal-sensor-cells = <1>; 332 }; 333 }; 334 }; 335 }; 336 }; 337}; 338 339&pcs_mdio5 { 340 status = "okay"; 341}; 342 343&pcs_mdio6 { 344 status = "okay"; 345}; 346 347&pcs_mdio9 { 348 status = "okay"; 349}; 350 351&pcs_mdio10 { 352 status = "okay"; 353}; 354 355&spi_bridge { 356 sw1: ethernet-switch@0 { 357 compatible = "nxp,sja1110a"; 358 reg = <0>; 359 spi-max-frequency = <4000000>; 360 spi-cpol; 361 dsa,member = <0 0>; 362 363 ethernet-ports { 364 #address-cells = <1>; 365 #size-cells = <0>; 366 367 /* Microcontroller port */ 368 port@0 { 369 reg = <0>; 370 status = "disabled"; 371 }; 372 373 /* SW1_P1 */ 374 port@1 { 375 reg = <1>; 376 label = "con_2x20"; 377 phy-mode = "sgmii"; 378 379 fixed-link { 380 speed = <1000>; 381 full-duplex; 382 }; 383 }; 384 385 port@2 { 386 reg = <2>; 387 ethernet = <&dpmac17>; 388 phy-mode = "rgmii-id"; 389 rx-internal-delay-ps = <2000>; 390 tx-internal-delay-ps = <2000>; 391 392 fixed-link { 393 speed = <1000>; 394 full-duplex; 395 }; 396 }; 397 398 port@3 { 399 reg = <3>; 400 label = "1ge_p1"; 401 phy-mode = "rgmii-id"; 402 phy-handle = <&sw1_mii3_phy>; 403 }; 404 405 sw1p4: port@4 { 406 reg = <4>; 407 link = <&sw2p1>; 408 phy-mode = "sgmii"; 409 410 fixed-link { 411 speed = <1000>; 412 full-duplex; 413 }; 414 }; 415 416 port@5 { 417 reg = <5>; 418 label = "trx1"; 419 phy-mode = "internal"; 420 phy-handle = <&sw1_port5_base_t1_phy>; 421 }; 422 423 port@6 { 424 reg = <6>; 425 label = "trx2"; 426 phy-mode = "internal"; 427 phy-handle = <&sw1_port6_base_t1_phy>; 428 }; 429 430 port@7 { 431 reg = <7>; 432 label = "trx3"; 433 phy-mode = "internal"; 434 phy-handle = <&sw1_port7_base_t1_phy>; 435 }; 436 437 port@8 { 438 reg = <8>; 439 label = "trx4"; 440 phy-mode = "internal"; 441 phy-handle = <&sw1_port8_base_t1_phy>; 442 }; 443 444 port@9 { 445 reg = <9>; 446 label = "trx5"; 447 phy-mode = "internal"; 448 phy-handle = <&sw1_port9_base_t1_phy>; 449 }; 450 451 port@a { 452 reg = <10>; 453 label = "trx6"; 454 phy-mode = "internal"; 455 phy-handle = <&sw1_port10_base_t1_phy>; 456 }; 457 }; 458 459 mdios { 460 #address-cells = <1>; 461 #size-cells = <0>; 462 463 mdio@0 { 464 compatible = "nxp,sja1110-base-t1-mdio"; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 reg = <0>; 468 469 sw1_port5_base_t1_phy: ethernet-phy@1 { 470 compatible = "ethernet-phy-ieee802.3-c45"; 471 reg = <0x1>; 472 }; 473 474 sw1_port6_base_t1_phy: ethernet-phy@2 { 475 compatible = "ethernet-phy-ieee802.3-c45"; 476 reg = <0x2>; 477 }; 478 479 sw1_port7_base_t1_phy: ethernet-phy@3 { 480 compatible = "ethernet-phy-ieee802.3-c45"; 481 reg = <0x3>; 482 }; 483 484 sw1_port8_base_t1_phy: ethernet-phy@4 { 485 compatible = "ethernet-phy-ieee802.3-c45"; 486 reg = <0x4>; 487 }; 488 489 sw1_port9_base_t1_phy: ethernet-phy@5 { 490 compatible = "ethernet-phy-ieee802.3-c45"; 491 reg = <0x5>; 492 }; 493 494 sw1_port10_base_t1_phy: ethernet-phy@6 { 495 compatible = "ethernet-phy-ieee802.3-c45"; 496 reg = <0x6>; 497 }; 498 }; 499 }; 500 }; 501 502 sw2: ethernet-switch@2 { 503 compatible = "nxp,sja1110a"; 504 reg = <2>; 505 spi-max-frequency = <4000000>; 506 spi-cpol; 507 dsa,member = <0 1>; 508 509 ethernet-ports { 510 #address-cells = <1>; 511 #size-cells = <0>; 512 513 /* Microcontroller port */ 514 port@0 { 515 reg = <0>; 516 status = "disabled"; 517 }; 518 519 sw2p1: port@1 { 520 reg = <1>; 521 link = <&sw1p4>; 522 phy-mode = "sgmii"; 523 524 fixed-link { 525 speed = <1000>; 526 full-duplex; 527 }; 528 }; 529 530 port@2 { 531 reg = <2>; 532 ethernet = <&dpmac18>; 533 phy-mode = "rgmii-id"; 534 rx-internal-delay-ps = <2000>; 535 tx-internal-delay-ps = <2000>; 536 537 fixed-link { 538 speed = <1000>; 539 full-duplex; 540 }; 541 }; 542 543 port@3 { 544 reg = <3>; 545 label = "1ge_p2"; 546 phy-mode = "rgmii-id"; 547 phy-handle = <&sw2_mii3_phy>; 548 }; 549 550 port@4 { 551 reg = <4>; 552 label = "to_sw3"; 553 phy-mode = "2500base-x"; 554 555 fixed-link { 556 speed = <2500>; 557 full-duplex; 558 }; 559 }; 560 561 port@5 { 562 reg = <5>; 563 label = "trx7"; 564 phy-mode = "internal"; 565 phy-handle = <&sw2_port5_base_t1_phy>; 566 }; 567 568 port@6 { 569 reg = <6>; 570 label = "trx8"; 571 phy-mode = "internal"; 572 phy-handle = <&sw2_port6_base_t1_phy>; 573 }; 574 575 port@7 { 576 reg = <7>; 577 label = "trx9"; 578 phy-mode = "internal"; 579 phy-handle = <&sw2_port7_base_t1_phy>; 580 }; 581 582 port@8 { 583 reg = <8>; 584 label = "trx10"; 585 phy-mode = "internal"; 586 phy-handle = <&sw2_port8_base_t1_phy>; 587 }; 588 589 port@9 { 590 reg = <9>; 591 label = "trx11"; 592 phy-mode = "internal"; 593 phy-handle = <&sw2_port9_base_t1_phy>; 594 }; 595 596 port@a { 597 reg = <10>; 598 label = "trx12"; 599 phy-mode = "internal"; 600 phy-handle = <&sw2_port10_base_t1_phy>; 601 }; 602 }; 603 604 mdios { 605 #address-cells = <1>; 606 #size-cells = <0>; 607 608 mdio@0 { 609 compatible = "nxp,sja1110-base-t1-mdio"; 610 #address-cells = <1>; 611 #size-cells = <0>; 612 reg = <0>; 613 614 sw2_port5_base_t1_phy: ethernet-phy@1 { 615 compatible = "ethernet-phy-ieee802.3-c45"; 616 reg = <0x1>; 617 }; 618 619 sw2_port6_base_t1_phy: ethernet-phy@2 { 620 compatible = "ethernet-phy-ieee802.3-c45"; 621 reg = <0x2>; 622 }; 623 624 sw2_port7_base_t1_phy: ethernet-phy@3 { 625 compatible = "ethernet-phy-ieee802.3-c45"; 626 reg = <0x3>; 627 }; 628 629 sw2_port8_base_t1_phy: ethernet-phy@4 { 630 compatible = "ethernet-phy-ieee802.3-c45"; 631 reg = <0x4>; 632 }; 633 634 sw2_port9_base_t1_phy: ethernet-phy@5 { 635 compatible = "ethernet-phy-ieee802.3-c45"; 636 reg = <0x5>; 637 }; 638 639 sw2_port10_base_t1_phy: ethernet-phy@6 { 640 compatible = "ethernet-phy-ieee802.3-c45"; 641 reg = <0x6>; 642 }; 643 }; 644 }; 645 }; 646}; 647 648&uart0 { 649 status = "okay"; 650}; 651 652&uart1 { 653 status = "okay"; 654}; 655 656&usb0 { 657 status = "okay"; 658}; 659 660&usb1 { 661 status = "okay"; 662};