cachepc-linux

imx8mm-tqma8mqml-mba8mx.dts (7957B)

// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
 * Copyright 2020-2021 TQ-Systems GmbH
 */

/dts-v1/;

#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mm-tqma8mqml.dtsi"
#include "mba8mx.dtsi"

/ {
	model = "TQ-Systems GmbH i.MX8MM TQMa8MxML on MBa8Mx";
	compatible = "tq,imx8mm-tqma8mqml-mba8mx", "tq,imx8mm-tqma8mqml", "fsl,imx8mm";

	aliases {
		eeprom0 = &eeprom3;
		mmc0 = &usdhc3;
		mmc1 = &usdhc2;
		mmc2 = &usdhc1;
		rtc0 = &pcf85063;
		rtc1 = &snvs_rtc;
	};

	reg_usdhc2_vmmc: regulator-vmmc {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		startup-delay-us = <100>;
		off-on-delay-us = <12000>;
	};

	extcon_usbotg1: extcon-usbotg1 {
		compatible = "linux,extcon-usb-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb1_extcon>;
		id-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
	};
};

&i2c1 {
	expander2: gpio@27 {
		compatible = "nxp,pca9555";
		reg = <0x27>;
		gpio-controller;
		#gpio-cells = <2>;
		vcc-supply = <&reg_vcc_3v3>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_expander>;
		interrupt-parent = <&gpio1>;
		interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};
};

&pcie_phy {
	clocks = <&pcie0_refclk>;
	status = "okay";
};

&pcie0 {
	reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
		<&pcie0_refclk>;
	clock-names = "pcie", "pcie_aux", "pcie_bus";
	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
				<&clk IMX8MM_CLK_PCIE1_CTRL>;
	assigned-clock-rates = <10000000>, <250000000>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
				<&clk IMX8MM_SYS_PLL2_250M>;
	status = "okay";
};

&sai3 {
	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
	clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <&clk IMX8MM_CLK_DUMMY>,
		<&clk IMX8MM_CLK_SAI3_ROOT>, <&clk IMX8MM_CLK_DUMMY>,
		<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>,
		<&clk IMX8MM_AUDIO_PLL2_OUT>;
};

&tlv320aic3x04 {
	clock-names = "mclk";
	clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
};

&uart1 {
	assigned-clocks = <&clk IMX8MM_CLK_UART1>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
};

&uart2 {
	assigned-clocks = <&clk IMX8MM_CLK_UART2>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
};

&usbotg1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg1>;
	dr_mode = "otg";
	extcon = <&extcon_usbotg1>;
	srp-disable;
	hnp-disable;
	adp-disable;
	power-active-high;
	over-current-active-low;
	status = "okay";
};

&usbotg2 {
	dr_mode = "host";
	disable-over-current;
	vbus-supply = <&reg_hub_vbus>;
	status = "okay";
};

&iomuxc {
	pinctrl_ecspi1: ecspi1grp {
		fsl,pins = <MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	0x00000006>,
			   <MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x00000006>,
			   <MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	0x00000006>,
			   <MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x00000006>;
	};

	pinctrl_ecspi2: ecspi2grp {
		fsl,pins = <MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0x00000006>,
			   <MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0x00000006>,
			   <MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0x00000006>,
			   <MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x00000006>;
	};

	pinctrl_expander: expandergrp {
		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x94>;
	};

	pinctrl_fec1: fec1grp {
		fsl,pins = <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x40000002>,
			   <MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x40000002>,
			   <MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x14>,
			   <MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x14>,
			   <MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x14>,
			   <MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x14>,
			   <MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x90>,
			   <MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x90>,
			   <MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x90>,
			   <MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x90>,
			   <MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x14>,
			   <MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x90>,
			   <MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x90>,
			   <MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x14>;
	};

	pinctrl_gpiobutton: gpiobuttongrp {
		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5		0x84>,
			   <MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x84>,
			   <MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0		0x84>;
	};

	pinctrl_gpioled: gpioledgrp {
		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x84>,
			   <MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14		0x84>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x40000004>,
			   <MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x40000004>;
	};

	pinctrl_i2c2_gpio: i2c2gpiogrp {
		fsl,pins = <MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16		0x40000004>,
			   <MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17		0x40000004>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL		0x40000004>,
			   <MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA		0x40000004>;
	};

	pinctrl_i2c3_gpio: i2c3gpiogrp {
		fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18		0x40000004>,
			   <MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19		0x40000004>;
	};

	pinctrl_pwm3: pwm3grp {
		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT		0x14>;
	};

	pinctrl_pwm4: pwm4grp {
		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT		0x14>;
	};

	pinctrl_sai3: sai3grp {
		fsl,pins = <MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK		0x94>,
			   <MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK		0x94>,
			   <MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC		0x94>,
			   <MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0		0x94>,
			   <MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC		0x94>,
			   <MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0		0x94>,
			   <MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK		0x94>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX		0x16>,
			   <MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX		0x16>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX		0x16>,
			   <MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX		0x16>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX		0x16>,
			   <MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX		0x16>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX		0x16>,
			   <MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX		0x16>;
	};

	pinctrl_usbotg1: usbotg1grp {
		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR	0x84>,
			   <MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC		0x84>;
	};

	pinctrl_usb1_extcon: usb1-extcongrp {
		fsl,pins = <MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x1c0>;
	};

	pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
		fsl,pins = <MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x84>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x1d4>,
			   <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4>,
			   <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4>,
			   <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4>,
			   <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4>,
			   <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4>,
			   <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x84>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x1d4>,
			   <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4>,
			   <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4>,
			   <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4>,
			   <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4>,
			   <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4>,
			   <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x84>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x1d4>,
			   <MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4>,
			   <MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4>,
			   <MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4>,
			   <MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4>,
			   <MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4>,
			   <MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x84>;
	};
};