imx8mn-evk.dtsi (11724B)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/usb/pd.h> 7#include "imx8mn.dtsi" 8 9/ { 10 chosen { 11 stdout-path = &uart2; 12 }; 13 14 gpio-leds { 15 compatible = "gpio-leds"; 16 pinctrl-names = "default"; 17 pinctrl-0 = <&pinctrl_gpio_led>; 18 19 status { 20 label = "yellow:status"; 21 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; 22 default-state = "on"; 23 }; 24 }; 25 26 memory@40000000 { 27 device_type = "memory"; 28 reg = <0x0 0x40000000 0 0x80000000>; 29 }; 30 31 reg_usdhc2_vmmc: regulator-usdhc2 { 32 compatible = "regulator-fixed"; 33 pinctrl-names = "default"; 34 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 35 regulator-name = "VSD_3V3"; 36 regulator-min-microvolt = <3300000>; 37 regulator-max-microvolt = <3300000>; 38 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 39 enable-active-high; 40 }; 41 42 ir-receiver { 43 compatible = "gpio-ir-receiver"; 44 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; 45 pinctrl-names = "default"; 46 pinctrl-0 = <&pinctrl_ir>; 47 linux,autosuspend-period = <125>; 48 }; 49 50 wm8524: audio-codec { 51 #sound-dai-cells = <0>; 52 compatible = "wlf,wm8524"; 53 pinctrl-names = "default"; 54 pinctrl-0 = <&pinctrl_gpio_wlf>; 55 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; 56 clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; 57 clock-names = "mclk"; 58 }; 59 60 sound-wm8524 { 61 compatible = "fsl,imx-audio-wm8524"; 62 model = "wm8524-audio"; 63 audio-cpu = <&sai3>; 64 audio-codec = <&wm8524>; 65 audio-asrc = <&easrc>; 66 audio-routing = 67 "Line Out Jack", "LINEVOUTL", 68 "Line Out Jack", "LINEVOUTR"; 69 }; 70 71 sound-spdif { 72 compatible = "fsl,imx-audio-spdif"; 73 model = "imx-spdif"; 74 spdif-controller = <&spdif1>; 75 spdif-out; 76 spdif-in; 77 }; 78}; 79 80&easrc { 81 fsl,asrc-rate = <48000>; 82 status = "okay"; 83}; 84 85&fec1 { 86 pinctrl-names = "default"; 87 pinctrl-0 = <&pinctrl_fec1>; 88 phy-mode = "rgmii-id"; 89 phy-handle = <ðphy0>; 90 fsl,magic-packet; 91 status = "okay"; 92 93 mdio { 94 #address-cells = <1>; 95 #size-cells = <0>; 96 97 ethphy0: ethernet-phy@0 { 98 compatible = "ethernet-phy-ieee802.3-c22"; 99 reg = <0>; 100 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 101 reset-assert-us = <10000>; 102 qca,disable-smarteee; 103 vddio-supply = <&vddio>; 104 105 vddio: vddio-regulator { 106 regulator-min-microvolt = <1800000>; 107 regulator-max-microvolt = <1800000>; 108 }; 109 }; 110 }; 111}; 112 113&flexspi { 114 pinctrl-names = "default"; 115 pinctrl-0 = <&pinctrl_flexspi>; 116 status = "okay"; 117 118 flash0: flash@0 { 119 compatible = "jedec,spi-nor"; 120 reg = <0>; 121 #address-cells = <1>; 122 #size-cells = <1>; 123 spi-max-frequency = <166000000>; 124 spi-tx-bus-width = <4>; 125 spi-rx-bus-width = <4>; 126 }; 127}; 128 129&i2c1 { 130 clock-frequency = <400000>; 131 pinctrl-names = "default"; 132 pinctrl-0 = <&pinctrl_i2c1>; 133 status = "okay"; 134}; 135 136&i2c2 { 137 clock-frequency = <400000>; 138 pinctrl-names = "default"; 139 pinctrl-0 = <&pinctrl_i2c2>; 140 status = "okay"; 141 142 ptn5110: tcpc@50 { 143 compatible = "nxp,ptn5110"; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&pinctrl_typec1>; 146 reg = <0x50>; 147 interrupt-parent = <&gpio2>; 148 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 149 status = "okay"; 150 151 port { 152 typec1_dr_sw: endpoint { 153 remote-endpoint = <&usb1_drd_sw>; 154 }; 155 }; 156 157 typec1_con: connector { 158 compatible = "usb-c-connector"; 159 label = "USB-C"; 160 power-role = "dual"; 161 data-role = "dual"; 162 try-power-role = "sink"; 163 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 164 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 165 PDO_VAR(5000, 20000, 3000)>; 166 op-sink-microwatt = <15000000>; 167 self-powered; 168 }; 169 }; 170}; 171 172&i2c3 { 173 clock-frequency = <400000>; 174 pinctrl-names = "default"; 175 pinctrl-0 = <&pinctrl_i2c3>; 176 status = "okay"; 177 178 pca6416: gpio@20 { 179 compatible = "ti,tca6416"; 180 reg = <0x20>; 181 gpio-controller; 182 #gpio-cells = <2>; 183 }; 184}; 185 186&sai3 { 187 pinctrl-names = "default"; 188 pinctrl-0 = <&pinctrl_sai3>; 189 assigned-clocks = <&clk IMX8MN_CLK_SAI3>; 190 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; 191 assigned-clock-rates = <24576000>; 192 fsl,sai-mclk-direction-output; 193 status = "okay"; 194}; 195 196&snvs_pwrkey { 197 status = "okay"; 198}; 199 200&spdif1 { 201 pinctrl-names = "default"; 202 pinctrl-0 = <&pinctrl_spdif1>; 203 assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>; 204 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; 205 assigned-clock-rates = <24576000>; 206 status = "okay"; 207}; 208 209&uart2 { /* console */ 210 pinctrl-names = "default"; 211 pinctrl-0 = <&pinctrl_uart2>; 212 status = "okay"; 213}; 214 215&uart3 { 216 pinctrl-names = "default"; 217 pinctrl-0 = <&pinctrl_uart3>; 218 assigned-clocks = <&clk IMX8MN_CLK_UART3>; 219 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; 220 uart-has-rtscts; 221 status = "okay"; 222}; 223 224&usbotg1 { 225 dr_mode = "otg"; 226 hnp-disable; 227 srp-disable; 228 adp-disable; 229 usb-role-switch; 230 disable-over-current; 231 samsung,picophy-pre-emp-curr-control = <3>; 232 samsung,picophy-dc-vol-level-adjust = <7>; 233 status = "okay"; 234 235 port { 236 usb1_drd_sw: endpoint { 237 remote-endpoint = <&typec1_dr_sw>; 238 }; 239 }; 240}; 241 242&usdhc2 { 243 assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; 244 assigned-clock-rates = <200000000>; 245 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 246 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 247 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 248 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 249 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; 250 bus-width = <4>; 251 vmmc-supply = <®_usdhc2_vmmc>; 252 status = "okay"; 253}; 254 255&usdhc3 { 256 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>; 257 assigned-clock-rates = <400000000>; 258 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 259 pinctrl-0 = <&pinctrl_usdhc3>; 260 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 261 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 262 bus-width = <8>; 263 non-removable; 264 status = "okay"; 265}; 266 267&wdog1 { 268 pinctrl-names = "default"; 269 pinctrl-0 = <&pinctrl_wdog>; 270 fsl,ext-reset-output; 271 status = "okay"; 272}; 273 274&iomuxc { 275 pinctrl_fec1: fec1grp { 276 fsl,pins = < 277 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 278 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 279 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 280 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 281 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 282 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 283 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 284 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 285 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 286 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 287 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 288 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 289 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 290 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 291 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 292 >; 293 }; 294 295 pinctrl_flexspi: flexspigrp { 296 fsl,pins = < 297 MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 298 MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 299 MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 300 MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 301 MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 302 MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 303 >; 304 }; 305 306 pinctrl_gpio_led: gpioledgrp { 307 fsl,pins = < 308 MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 309 >; 310 }; 311 312 pinctrl_gpio_wlf: gpiowlfgrp { 313 fsl,pins = < 314 MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6 315 >; 316 }; 317 318 pinctrl_ir: irgrp { 319 fsl,pins = < 320 MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f 321 >; 322 }; 323 324 pinctrl_i2c1: i2c1grp { 325 fsl,pins = < 326 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 327 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 328 >; 329 }; 330 331 pinctrl_i2c2: i2c2grp { 332 fsl,pins = < 333 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 334 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 335 >; 336 }; 337 338 pinctrl_i2c3: i2c3grp { 339 fsl,pins = < 340 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 341 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 342 >; 343 }; 344 345 pinctrl_pmic: pmicirqgrp { 346 fsl,pins = < 347 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 348 >; 349 }; 350 351 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 352 fsl,pins = < 353 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 354 >; 355 }; 356 357 pinctrl_sai3: sai3grp { 358 fsl,pins = < 359 MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 360 MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 361 MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 362 MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 363 >; 364 }; 365 366 pinctrl_spdif1: spdif1grp { 367 fsl,pins = < 368 MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 369 MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 370 >; 371 }; 372 373 pinctrl_typec1: typec1grp { 374 fsl,pins = < 375 MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 376 >; 377 }; 378 379 pinctrl_uart2: uart2grp { 380 fsl,pins = < 381 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 382 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 383 >; 384 }; 385 386 pinctrl_uart3: uart3grp { 387 fsl,pins = < 388 MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 389 MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 390 MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 391 MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 392 >; 393 }; 394 395 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 396 fsl,pins = < 397 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 398 >; 399 }; 400 401 pinctrl_usdhc2: usdhc2grp { 402 fsl,pins = < 403 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 404 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 405 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 406 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 407 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 408 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 409 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 410 >; 411 }; 412 413 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 414 fsl,pins = < 415 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 416 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 417 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 418 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 419 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 420 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 421 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 422 >; 423 }; 424 425 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 426 fsl,pins = < 427 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 428 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 429 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 430 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 431 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 432 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 433 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 434 >; 435 }; 436 437 pinctrl_usdhc3: usdhc3grp { 438 fsl,pins = < 439 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 440 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 441 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 442 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 443 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 444 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 445 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 446 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 447 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 448 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 449 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 450 >; 451 }; 452 453 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 454 fsl,pins = < 455 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 456 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 457 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 458 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 459 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 460 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 461 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 462 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 463 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 464 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 465 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 466 >; 467 }; 468 469 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 470 fsl,pins = < 471 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 472 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 473 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 474 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 475 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 476 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 477 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 478 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 479 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 480 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 481 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 482 >; 483 }; 484 485 pinctrl_wdog: wdoggrp { 486 fsl,pins = < 487 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 488 >; 489 }; 490};