imx8mp-venice-gw74xx.dts (19397B)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2021 Gateworks Corporation 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/linux-event-codes.h> 10#include <dt-bindings/leds/common.h> 11 12#include "imx8mp.dtsi" 13 14/ { 15 model = "Gateworks Venice GW74xx i.MX8MP board"; 16 compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp"; 17 18 aliases { 19 ethernet0 = &eqos; 20 ethernet1 = &fec; 21 ethernet2 = &lan1; 22 ethernet3 = &lan2; 23 ethernet4 = &lan3; 24 ethernet5 = &lan4; 25 ethernet6 = &lan5; 26 }; 27 28 chosen { 29 stdout-path = &uart2; 30 }; 31 32 memory@40000000 { 33 device_type = "memory"; 34 reg = <0x0 0x40000000 0 0x80000000>; 35 }; 36 37 gpio-keys { 38 compatible = "gpio-keys"; 39 40 key-0 { 41 label = "user_pb"; 42 gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 43 linux,code = <BTN_0>; 44 }; 45 46 key-1 { 47 label = "user_pb1x"; 48 linux,code = <BTN_1>; 49 interrupt-parent = <&gsc>; 50 interrupts = <0>; 51 }; 52 53 key-2 { 54 label = "key_erased"; 55 linux,code = <BTN_2>; 56 interrupt-parent = <&gsc>; 57 interrupts = <1>; 58 }; 59 60 key-3 { 61 label = "eeprom_wp"; 62 linux,code = <BTN_3>; 63 interrupt-parent = <&gsc>; 64 interrupts = <2>; 65 }; 66 67 key-4 { 68 label = "tamper"; 69 linux,code = <BTN_4>; 70 interrupt-parent = <&gsc>; 71 interrupts = <5>; 72 }; 73 74 key-5 { 75 label = "switch_hold"; 76 linux,code = <BTN_5>; 77 interrupt-parent = <&gsc>; 78 interrupts = <7>; 79 }; 80 }; 81 82 led-controller { 83 compatible = "gpio-leds"; 84 pinctrl-names = "default"; 85 pinctrl-0 = <&pinctrl_gpio_leds>; 86 87 led-0 { 88 function = LED_FUNCTION_HEARTBEAT; 89 color = <LED_COLOR_ID_GREEN>; 90 gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; 91 default-state = "on"; 92 linux,default-trigger = "heartbeat"; 93 }; 94 95 led-1 { 96 function = LED_FUNCTION_STATUS; 97 color = <LED_COLOR_ID_RED>; 98 gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; 99 default-state = "off"; 100 }; 101 }; 102 103 pps { 104 compatible = "pps-gpio"; 105 pinctrl-names = "default"; 106 pinctrl-0 = <&pinctrl_pps>; 107 gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; 108 }; 109 110 reg_usb2_vbus: regulator-usb2 { 111 pinctrl-names = "default"; 112 pinctrl-0 = <&pinctrl_reg_usb2>; 113 compatible = "regulator-fixed"; 114 regulator-name = "usb_usb2_vbus"; 115 gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>; 116 enable-active-high; 117 regulator-min-microvolt = <5000000>; 118 regulator-max-microvolt = <5000000>; 119 }; 120 121 reg_can2_stby: regulator-can2-stby { 122 compatible = "regulator-fixed"; 123 pinctrl-names = "default"; 124 pinctrl-0 = <&pinctrl_reg_can>; 125 regulator-name = "can2_stby"; 126 gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; 127 enable-active-high; 128 regulator-min-microvolt = <3300000>; 129 regulator-max-microvolt = <3300000>; 130 }; 131 132 reg_wifi_en: regulator-wifi-en { 133 pinctrl-names = "default"; 134 pinctrl-0 = <&pinctrl_reg_wifi>; 135 compatible = "regulator-fixed"; 136 regulator-name = "wl"; 137 gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; 138 startup-delay-us = <100>; 139 enable-active-high; 140 regulator-min-microvolt = <1800000>; 141 regulator-max-microvolt = <1800000>; 142 }; 143}; 144 145/* off-board header */ 146&ecspi2 { 147 pinctrl-names = "default"; 148 pinctrl-0 = <&pinctrl_spi2>; 149 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 150 status = "okay"; 151}; 152 153&eqos { 154 pinctrl-names = "default"; 155 pinctrl-0 = <&pinctrl_eqos>; 156 phy-mode = "rgmii-id"; 157 phy-handle = <ðphy0>; 158 status = "okay"; 159 160 mdio { 161 compatible = "snps,dwmac-mdio"; 162 #address-cells = <1>; 163 #size-cells = <0>; 164 165 ethphy0: ethernet-phy@0 { 166 compatible = "ethernet-phy-ieee802.3-c22"; 167 reg = <0x0>; 168 }; 169 }; 170}; 171 172&fec { 173 pinctrl-names = "default"; 174 pinctrl-0 = <&pinctrl_fec>; 175 phy-mode = "rgmii-id"; 176 local-mac-address = [00 00 00 00 00 00]; 177 status = "okay"; 178 179 fixed-link { 180 speed = <1000>; 181 full-duplex; 182 }; 183}; 184 185&flexcan2 { 186 pinctrl-names = "default"; 187 pinctrl-0 = <&pinctrl_flexcan2>; 188 xceiver-supply = <®_can2_stby>; 189 status = "okay"; 190}; 191 192&gpio1 { 193 gpio-line-names = 194 "", "", "", "", "", "", "", "", 195 "", "", "dio0", "", "dio1", "", "", "", 196 "", "", "", "", "", "", "", "", 197 "", "", "", "", "", "", "", ""; 198}; 199 200&gpio2 { 201 gpio-line-names = 202 "", "", "", "", "", "", "", "", 203 "", "", "", "", "", "", "", "", 204 "pcie3_wdis#", "", "", "pcie1_wdis@", "pcie2_wdis#", "", "", "", 205 "", "", "", "", "", "", "", ""; 206}; 207 208&gpio3 { 209 gpio-line-names = 210 "m2_gdis#", "", "", "", "", "", "", "m2_rst#", 211 "", "", "", "", "", "", "", "", 212 "m2_off#", "", "", "", "", "", "", "", 213 "", "", "", "", "", "", "", ""; 214}; 215 216&gpio4 { 217 gpio-line-names = 218 "", "", "", "", "", "", "", "", 219 "", "", "", "", "", "", "", "", 220 "", "", "", "", "m2_wdis#", "", "", "", 221 "", "", "", "", "", "", "", "uart_rs485"; 222}; 223 224&gpio5 { 225 gpio-line-names = 226 "uart_half", "uart_term", "", "", "", "", "", "", 227 "", "", "", "", "", "", "", "", 228 "", "", "", "", "", "", "", "", 229 "", "", "", "", "", "", "", ""; 230}; 231 232&i2c1 { 233 clock-frequency = <100000>; 234 pinctrl-names = "default"; 235 pinctrl-0 = <&pinctrl_i2c1>; 236 status = "okay"; 237 238 gsc: gsc@20 { 239 compatible = "gw,gsc"; 240 reg = <0x20>; 241 pinctrl-0 = <&pinctrl_gsc>; 242 interrupt-parent = <&gpio4>; 243 interrupts = <20 IRQ_TYPE_EDGE_FALLING>; 244 interrupt-controller; 245 #interrupt-cells = <1>; 246 247 adc { 248 compatible = "gw,gsc-adc"; 249 #address-cells = <1>; 250 #size-cells = <0>; 251 252 channel@6 { 253 gw,mode = <0>; 254 reg = <0x06>; 255 label = "temp"; 256 }; 257 258 channel@8 { 259 gw,mode = <1>; 260 reg = <0x08>; 261 label = "vdd_bat"; 262 }; 263 264 channel@82 { 265 gw,mode = <2>; 266 reg = <0x82>; 267 label = "vdd_adc1"; 268 gw,voltage-divider-ohms = <10000 10000>; 269 }; 270 271 channel@84 { 272 gw,mode = <2>; 273 reg = <0x84>; 274 label = "vdd_adc2"; 275 gw,voltage-divider-ohms = <10000 10000>; 276 }; 277 278 channel@86 { 279 gw,mode = <2>; 280 reg = <0x86>; 281 label = "vdd_vin"; 282 gw,voltage-divider-ohms = <22100 1000>; 283 }; 284 285 channel@88 { 286 gw,mode = <2>; 287 reg = <0x88>; 288 label = "vdd_3p3"; 289 gw,voltage-divider-ohms = <10000 10000>; 290 }; 291 292 channel@8c { 293 gw,mode = <2>; 294 reg = <0x8c>; 295 label = "vdd_2p5"; 296 gw,voltage-divider-ohms = <10000 10000>; 297 }; 298 299 channel@90 { 300 gw,mode = <2>; 301 reg = <0x90>; 302 label = "vdd_soc"; 303 }; 304 305 channel@92 { 306 gw,mode = <2>; 307 reg = <0x92>; 308 label = "vdd_arm"; 309 }; 310 311 channel@98 { 312 gw,mode = <2>; 313 reg = <0x98>; 314 label = "vdd_1p8"; 315 }; 316 317 channel@9a { 318 gw,mode = <2>; 319 reg = <0x9a>; 320 label = "vdd_1p2"; 321 }; 322 323 channel@9c { 324 gw,mode = <2>; 325 reg = <0x9c>; 326 label = "vdd_dram"; 327 }; 328 329 channel@a2 { 330 gw,mode = <2>; 331 reg = <0xa2>; 332 label = "vdd_gsc"; 333 gw,voltage-divider-ohms = <10000 10000>; 334 }; 335 }; 336 }; 337 338 gpio: gpio@23 { 339 compatible = "nxp,pca9555"; 340 reg = <0x23>; 341 gpio-controller; 342 #gpio-cells = <2>; 343 interrupt-parent = <&gsc>; 344 interrupts = <4>; 345 }; 346 347 pmic@25 { 348 compatible = "nxp,pca9450c"; 349 reg = <0x25>; 350 pinctrl-names = "default"; 351 pinctrl-0 = <&pinctrl_pmic>; 352 interrupt-parent = <&gpio3>; 353 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 354 355 regulators { 356 BUCK1 { 357 regulator-name = "BUCK1"; 358 regulator-min-microvolt = <720000>; 359 regulator-max-microvolt = <1000000>; 360 regulator-boot-on; 361 regulator-always-on; 362 regulator-ramp-delay = <3125>; 363 }; 364 365 BUCK2 { 366 regulator-name = "BUCK2"; 367 regulator-min-microvolt = <720000>; 368 regulator-max-microvolt = <1025000>; 369 regulator-boot-on; 370 regulator-always-on; 371 regulator-ramp-delay = <3125>; 372 nxp,dvs-run-voltage = <950000>; 373 nxp,dvs-standby-voltage = <850000>; 374 }; 375 376 BUCK4 { 377 regulator-name = "BUCK4"; 378 regulator-min-microvolt = <3000000>; 379 regulator-max-microvolt = <3600000>; 380 regulator-boot-on; 381 regulator-always-on; 382 }; 383 384 BUCK5 { 385 regulator-name = "BUCK5"; 386 regulator-min-microvolt = <1650000>; 387 regulator-max-microvolt = <1950000>; 388 regulator-boot-on; 389 regulator-always-on; 390 }; 391 392 BUCK6 { 393 regulator-name = "BUCK6"; 394 regulator-min-microvolt = <1045000>; 395 regulator-max-microvolt = <1155000>; 396 regulator-boot-on; 397 regulator-always-on; 398 }; 399 400 LDO1 { 401 regulator-name = "LDO1"; 402 regulator-min-microvolt = <1650000>; 403 regulator-max-microvolt = <1950000>; 404 regulator-boot-on; 405 regulator-always-on; 406 }; 407 408 LDO3 { 409 regulator-name = "LDO3"; 410 regulator-min-microvolt = <1710000>; 411 regulator-max-microvolt = <1890000>; 412 regulator-boot-on; 413 regulator-always-on; 414 }; 415 416 LDO5 { 417 regulator-name = "LDO5"; 418 regulator-min-microvolt = <1800000>; 419 regulator-max-microvolt = <3300000>; 420 regulator-boot-on; 421 regulator-always-on; 422 }; 423 }; 424 }; 425 426 eeprom@50 { 427 compatible = "atmel,24c02"; 428 reg = <0x50>; 429 pagesize = <16>; 430 }; 431 432 eeprom@51 { 433 compatible = "atmel,24c02"; 434 reg = <0x51>; 435 pagesize = <16>; 436 }; 437 438 eeprom@52 { 439 compatible = "atmel,24c02"; 440 reg = <0x52>; 441 pagesize = <16>; 442 }; 443 444 eeprom@53 { 445 compatible = "atmel,24c02"; 446 reg = <0x53>; 447 pagesize = <16>; 448 }; 449 450 rtc@68 { 451 compatible = "dallas,ds1672"; 452 reg = <0x68>; 453 }; 454}; 455 456&i2c2 { 457 clock-frequency = <400000>; 458 pinctrl-names = "default"; 459 pinctrl-0 = <&pinctrl_i2c2>; 460 status = "okay"; 461 462 accelerometer@19 { 463 compatible = "st,lis2de12"; 464 pinctrl-names = "default"; 465 pinctrl-0 = <&pinctrl_accel>; 466 reg = <0x19>; 467 st,drdy-int-pin = <1>; 468 interrupt-parent = <&gpio1>; 469 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 470 interrupt-names = "INT1"; 471 }; 472 473 switch: switch@5f { 474 compatible = "microchip,ksz9897"; 475 reg = <0x5f>; 476 pinctrl-0 = <&pinctrl_ksz>; 477 interrupt-parent = <&gpio4>; 478 interrupts = <29 IRQ_TYPE_EDGE_FALLING>; 479 480 ports { 481 #address-cells = <1>; 482 #size-cells = <0>; 483 484 lan1: port@0 { 485 reg = <0>; 486 label = "lan1"; 487 local-mac-address = [00 00 00 00 00 00]; 488 }; 489 490 lan2: port@1 { 491 reg = <1>; 492 label = "lan2"; 493 local-mac-address = [00 00 00 00 00 00]; 494 }; 495 496 lan3: port@2 { 497 reg = <2>; 498 label = "lan3"; 499 local-mac-address = [00 00 00 00 00 00]; 500 }; 501 502 lan4: port@3 { 503 reg = <3>; 504 label = "lan4"; 505 local-mac-address = [00 00 00 00 00 00]; 506 }; 507 508 lan5: port@4 { 509 reg = <4>; 510 label = "lan5"; 511 local-mac-address = [00 00 00 00 00 00]; 512 }; 513 514 port@6 { 515 reg = <6>; 516 label = "cpu"; 517 ethernet = <&fec>; 518 phy-mode = "rgmii-id"; 519 520 fixed-link { 521 speed = <1000>; 522 full-duplex; 523 }; 524 }; 525 }; 526 }; 527}; 528 529/* off-board header */ 530&i2c3 { 531 clock-frequency = <400000>; 532 pinctrl-names = "default"; 533 pinctrl-0 = <&pinctrl_i2c3>; 534 status = "okay"; 535}; 536 537/* off-board header */ 538&i2c4 { 539 clock-frequency = <400000>; 540 pinctrl-names = "default"; 541 pinctrl-0 = <&pinctrl_i2c4>; 542 status = "okay"; 543}; 544 545/* GPS / off-board header */ 546&uart1 { 547 pinctrl-names = "default"; 548 pinctrl-0 = <&pinctrl_uart1>; 549 status = "okay"; 550}; 551 552/* RS232 console */ 553&uart2 { 554 pinctrl-names = "default"; 555 pinctrl-0 = <&pinctrl_uart2>; 556 status = "okay"; 557}; 558 559&uart4 { 560 pinctrl-names = "default"; 561 pinctrl-0 = <&pinctrl_uart4>; 562 status = "okay"; 563}; 564 565/* USB1 - Type C front panel */ 566&usb3_phy0 { 567 pinctrl-names = "default"; 568 pinctrl-0 = <&pinctrl_usb1>; 569 status = "okay"; 570}; 571 572&usb3_0 { 573 fsl,over-current-active-low; 574 status = "okay"; 575}; 576 577&usb_dwc3_0 { 578 dr_mode = "host"; 579 status = "okay"; 580}; 581 582/* USB2 - USB3.0 Hub */ 583&usb3_phy1 { 584 vbus-supply = <®_usb2_vbus>; 585 status = "okay"; 586}; 587 588&usb3_1 { 589 fsl,permanently-attached; 590 fsl,disable-port-power-control; 591 status = "okay"; 592}; 593 594&usb_dwc3_1 { 595 dr_mode = "host"; 596 status = "okay"; 597}; 598 599/* eMMC */ 600&usdhc3 { 601 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; 602 assigned-clock-rates = <400000000>; 603 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 604 pinctrl-0 = <&pinctrl_usdhc3>; 605 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 606 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 607 bus-width = <8>; 608 non-removable; 609 status = "okay"; 610}; 611 612&wdog1 { 613 pinctrl-names = "default"; 614 pinctrl-0 = <&pinctrl_wdog>; 615 fsl,ext-reset-output; 616 status = "okay"; 617}; 618 619&iomuxc { 620 pinctrl-names = "default"; 621 pinctrl-0 = <&pinctrl_hog>; 622 623 pinctrl_hog: hoggrp { 624 fsl,pins = < 625 MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000040 /* DIO0 */ 626 MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000040 /* DIO1 */ 627 MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000040 /* M2SKT_OFF# */ 628 MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x40000150 /* PCIE1_WDIS# */ 629 MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */ 630 MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */ 631 MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */ 632 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000150 /* M2SKT_WDIS# */ 633 MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x40000150 /* M2SKT_GDIS# */ 634 MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */ 635 MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */ 636 MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */ 637 >; 638 }; 639 640 pinctrl_accel: accelgrp { 641 fsl,pins = < 642 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x150 643 >; 644 }; 645 646 pinctrl_eqos: eqosgrp { 647 fsl,pins = < 648 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 649 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 650 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 651 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 652 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 653 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 654 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 655 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 656 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 657 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 658 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 659 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 660 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 661 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 662 MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x140 /* RST# */ 663 MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x150 /* IRQ# */ 664 >; 665 }; 666 667 pinctrl_fec: fecgrp { 668 fsl,pins = < 669 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 670 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 671 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 672 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 673 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 674 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 675 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 676 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 677 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 678 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 679 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 680 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 681 MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x140 682 MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x140 683 >; 684 }; 685 686 pinctrl_flexcan2: flexcan2grp { 687 fsl,pins = < 688 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 689 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 690 >; 691 }; 692 693 pinctrl_gsc: gscgrp { 694 fsl,pins = < 695 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x150 696 >; 697 }; 698 699 pinctrl_i2c1: i2c1grp { 700 fsl,pins = < 701 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 702 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 703 >; 704 }; 705 706 pinctrl_i2c2: i2c2grp { 707 fsl,pins = < 708 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 709 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 710 >; 711 }; 712 713 pinctrl_i2c3: i2c3grp { 714 fsl,pins = < 715 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 716 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 717 >; 718 }; 719 720 pinctrl_i2c4: i2c4grp { 721 fsl,pins = < 722 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2 723 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2 724 >; 725 }; 726 727 pinctrl_ksz: kszgrp { 728 fsl,pins = < 729 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x150 /* IRQ# */ 730 MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x140 /* RST# */ 731 >; 732 }; 733 734 pinctrl_gpio_leds: ledgrp { 735 fsl,pins = < 736 MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x10 737 MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x10 738 >; 739 }; 740 741 pinctrl_pmic: pmicgrp { 742 fsl,pins = < 743 MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x140 744 >; 745 }; 746 747 pinctrl_pps: ppsgrp { 748 fsl,pins = < 749 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140 750 >; 751 }; 752 753 pinctrl_reg_can: regcangrp { 754 fsl,pins = < 755 MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x154 756 >; 757 }; 758 759 pinctrl_reg_usb2: regusb2grp { 760 fsl,pins = < 761 MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x140 762 >; 763 }; 764 765 pinctrl_reg_wifi: regwifigrp { 766 fsl,pins = < 767 MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x110 768 >; 769 }; 770 771 pinctrl_sai2: sai2grp { 772 fsl,pins = < 773 MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 774 MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 775 MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 776 MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 777 >; 778 }; 779 780 pinctrl_spi2: spi2grp { 781 fsl,pins = < 782 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 783 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 784 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 785 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 786 >; 787 }; 788 789 pinctrl_uart1: uart1grp { 790 fsl,pins = < 791 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 792 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 793 >; 794 }; 795 796 pinctrl_uart2: uart2grp { 797 fsl,pins = < 798 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 799 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 800 >; 801 }; 802 803 pinctrl_uart3: uart3grp { 804 fsl,pins = < 805 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 806 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 807 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 808 MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x140 809 >; 810 }; 811 812 pinctrl_uart3_gpio: uart3gpiogrp { 813 fsl,pins = < 814 MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x110 815 >; 816 }; 817 818 pinctrl_uart4: uart4grp { 819 fsl,pins = < 820 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 821 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 822 >; 823 }; 824 825 pinctrl_usb1: usb1grp { 826 fsl,pins = < 827 MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 828 MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x140 829 >; 830 }; 831 832 pinctrl_usdhc1: usdhc1grp { 833 fsl,pins = < 834 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 835 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 836 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 837 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 838 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 839 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 840 >; 841 }; 842 843 pinctrl_usdhc3: usdhc3grp { 844 fsl,pins = < 845 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 846 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 847 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 848 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 849 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 850 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 851 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 852 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 853 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 854 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 855 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 856 >; 857 }; 858 859 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 860 fsl,pins = < 861 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 862 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 863 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 864 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 865 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 866 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 867 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 868 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 869 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 870 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 871 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 872 >; 873 }; 874 875 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 876 fsl,pins = < 877 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 878 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 879 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 880 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 881 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 882 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 883 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 884 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 885 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 886 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 887 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 888 >; 889 }; 890 891 pinctrl_wdog: wdoggrp { 892 fsl,pins = < 893 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 894 >; 895 }; 896};