imx8mp-verdin.dtsi (36409B)
1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2022 Toradex 4 */ 5 6#include "dt-bindings/pwm/pwm.h" 7#include "imx8mp.dtsi" 8 9/ { 10 chosen { 11 stdout-path = &uart3; 12 }; 13 14 aliases { 15 /* Ethernet aliases to ensure correct MAC addresses */ 16 ethernet0 = &eqos; 17 ethernet1 = &fec; 18 rtc0 = &rtc_i2c; 19 rtc1 = &snvs_rtc; 20 }; 21 22 backlight: backlight { 23 compatible = "pwm-backlight"; 24 brightness-levels = <0 45 63 88 119 158 203 255>; 25 default-brightness-level = <4>; 26 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */ 27 enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; 28 pinctrl-names = "default"; 29 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>; 30 power-supply = <®_3p3v>; 31 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */ 32 pwms = <&pwm3 0 6666667 PWM_POLARITY_INVERTED>; 33 status = "disabled"; 34 }; 35 36 backlight_mezzanine: backlight-mezzanine { 37 compatible = "pwm-backlight"; 38 brightness-levels = <0 45 63 88 119 158 203 255>; 39 default-brightness-level = <4>; 40 /* Verdin GPIO 4 (SODIMM 212) */ 41 enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; 42 /* Verdin PWM_2 (SODIMM 16) */ 43 pwms = <&pwm2 0 6666667 PWM_POLARITY_INVERTED>; 44 status = "disabled"; 45 }; 46 47 gpio-keys { 48 compatible = "gpio-keys"; 49 pinctrl-names = "default"; 50 pinctrl-0 = <&pinctrl_gpio_keys>; 51 52 wakeup { 53 debounce-interval = <10>; 54 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ 55 gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; 56 label = "Wake-Up"; 57 linux,code = <KEY_WAKEUP>; 58 wakeup-source; 59 }; 60 }; 61 62 /* Carrier Board Supplies */ 63 reg_1p8v: regulator-1p8v { 64 compatible = "regulator-fixed"; 65 regulator-max-microvolt = <1800000>; 66 regulator-min-microvolt = <1800000>; 67 regulator-name = "+V1.8_SW"; 68 }; 69 70 reg_3p3v: regulator-3p3v { 71 compatible = "regulator-fixed"; 72 regulator-max-microvolt = <3300000>; 73 regulator-min-microvolt = <3300000>; 74 regulator-name = "+V3.3_SW"; 75 }; 76 77 reg_5p0v: regulator-5p0v { 78 compatible = "regulator-fixed"; 79 regulator-max-microvolt = <5000000>; 80 regulator-min-microvolt = <5000000>; 81 regulator-name = "+V5_SW"; 82 }; 83 84 /* Non PMIC On-module Supplies */ 85 reg_module_eth1phy: regulator-module-eth1phy { 86 compatible = "regulator-fixed"; 87 enable-active-high; 88 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */ 89 off-on-delay = <500000>; 90 pinctrl-names = "default"; 91 pinctrl-0 = <&pinctrl_reg_eth>; 92 regulator-always-on; 93 regulator-boot-on; 94 regulator-max-microvolt = <3300000>; 95 regulator-min-microvolt = <3300000>; 96 regulator-name = "On-module +V3.3_ETH"; 97 startup-delay-us = <200000>; 98 vin-supply = <®_vdd_3v3>; 99 }; 100 101 reg_usb1_vbus: regulator-usb1-vbus { 102 compatible = "regulator-fixed"; 103 enable-active-high; 104 /* Verdin USB_1_EN (SODIMM 155) */ 105 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 106 pinctrl-names = "default"; 107 pinctrl-0 = <&pinctrl_usb1_vbus>; 108 regulator-max-microvolt = <5000000>; 109 regulator-min-microvolt = <5000000>; 110 regulator-name = "USB_1_EN"; 111 }; 112 113 reg_usb2_vbus: regulator-usb2-vbus { 114 compatible = "regulator-fixed"; 115 enable-active-high; 116 /* Verdin USB_2_EN (SODIMM 185) */ 117 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; 118 pinctrl-names = "default"; 119 pinctrl-0 = <&pinctrl_usb2_vbus>; 120 regulator-max-microvolt = <5000000>; 121 regulator-min-microvolt = <5000000>; 122 regulator-name = "USB_2_EN"; 123 }; 124 125 reg_usdhc2_vmmc: regulator-usdhc2 { 126 compatible = "regulator-fixed"; 127 enable-active-high; 128 /* Verdin SD_1_PWR_EN (SODIMM 76) */ 129 gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; 130 off-on-delay = <100000>; 131 pinctrl-names = "default"; 132 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; 133 regulator-max-microvolt = <3300000>; 134 regulator-min-microvolt = <3300000>; 135 regulator-name = "+V3.3_SD"; 136 startup-delay-us = <2000>; 137 }; 138 139 reserved-memory { 140 #address-cells = <2>; 141 #size-cells = <2>; 142 ranges; 143 144 /* Use the kernel configuration settings instead */ 145 /delete-node/ linux,cma; 146 }; 147}; 148 149/* Verdin SPI_1 */ 150&ecspi1 { 151 #address-cells = <1>; 152 #size-cells = <0>; 153 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 154 pinctrl-names = "default"; 155 pinctrl-0 = <&pinctrl_ecspi1>; 156}; 157 158/* Verdin ETH_1 (On-module PHY) */ 159&eqos { 160 phy-handle = <ðphy0>; 161 phy-mode = "rgmii-id"; 162 phy-supply = <®_module_eth1phy>; 163 pinctrl-names = "default"; 164 pinctrl-0 = <&pinctrl_eqos>; 165 snps,force_thresh_dma_mode; 166 snps,mtl-rx-config = <&mtl_rx_setup>; 167 snps,mtl-tx-config = <&mtl_tx_setup>; 168 169 mdio { 170 compatible = "snps,dwmac-mdio"; 171 #address-cells = <1>; 172 #size-cells = <0>; 173 174 ethphy0: ethernet-phy@7 { 175 compatible = "ethernet-phy-ieee802.3-c22"; 176 eee-broken-100tx; 177 eee-broken-1000t; 178 interrupt-parent = <&gpio1>; 179 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 180 micrel,led-mode = <0>; 181 reg = <7>; 182 }; 183 }; 184 185 mtl_rx_setup: rx-queues-config { 186 snps,rx-queues-to-use = <5>; 187 snps,rx-sched-sp; 188 189 queue0 { 190 snps,dcb-algorithm; 191 snps,priority = <0x1>; 192 snps,map-to-dma-channel = <0>; 193 }; 194 195 queue1 { 196 snps,dcb-algorithm; 197 snps,priority = <0x2>; 198 snps,map-to-dma-channel = <1>; 199 }; 200 201 queue2 { 202 snps,dcb-algorithm; 203 snps,priority = <0x4>; 204 snps,map-to-dma-channel = <2>; 205 }; 206 207 queue3 { 208 snps,dcb-algorithm; 209 snps,priority = <0x8>; 210 snps,map-to-dma-channel = <3>; 211 }; 212 213 queue4 { 214 snps,dcb-algorithm; 215 snps,priority = <0xf0>; 216 snps,map-to-dma-channel = <4>; 217 }; 218 }; 219 220 mtl_tx_setup: tx-queues-config { 221 snps,tx-queues-to-use = <5>; 222 snps,tx-sched-sp; 223 224 queue0 { 225 snps,dcb-algorithm; 226 snps,priority = <0x1>; 227 }; 228 229 queue1 { 230 snps,dcb-algorithm; 231 snps,priority = <0x2>; 232 }; 233 234 queue2 { 235 snps,dcb-algorithm; 236 snps,priority = <0x4>; 237 }; 238 239 queue3 { 240 snps,dcb-algorithm; 241 snps,priority = <0x8>; 242 }; 243 244 queue4 { 245 snps,dcb-algorithm; 246 snps,priority = <0xf0>; 247 }; 248 }; 249}; 250 251/* Verdin ETH_2_RGMII */ 252&fec { 253 fsl,magic-packet; 254 phy-handle = <ðphy1>; 255 phy-mode = "rgmii-id"; 256 pinctrl-names = "default", "sleep"; 257 pinctrl-0 = <&pinctrl_fec>; 258 pinctrl-1 = <&pinctrl_fec_sleep>; 259 260 mdio { 261 #address-cells = <1>; 262 #size-cells = <0>; 263 264 ethphy1: ethernet-phy@7 { 265 compatible = "ethernet-phy-ieee802.3-c22"; 266 interrupt-parent = <&gpio4>; 267 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 268 micrel,led-mode = <0>; 269 reg = <7>; 270 }; 271 }; 272}; 273 274/* Verdin CAN_1 */ 275&flexcan1 { 276 pinctrl-names = "default"; 277 pinctrl-0 = <&pinctrl_flexcan1>; 278 status = "disabled"; 279}; 280 281 282/* Verdin CAN_2 */ 283&flexcan2 { 284 pinctrl-names = "default"; 285 pinctrl-0 = <&pinctrl_flexcan2>; 286 status = "disabled"; 287}; 288 289/* Verdin QSPI_1 */ 290&flexspi { 291 pinctrl-names = "default"; 292 pinctrl-0 = <&pinctrl_flexspi0>; 293}; 294 295&gpio1 { 296 gpio-line-names = "SODIMM_206", 297 "SODIMM_208", 298 "", 299 "", 300 "", 301 "SODIMM_210", 302 "SODIMM_212", 303 "SODIMM_216", 304 "SODIMM_218", 305 "", 306 "", 307 "SODIMM_16", 308 "SODIMM_155", 309 "SODIMM_157", 310 "SODIMM_185", 311 "SODIMM_91"; 312}; 313 314&gpio2 { 315 gpio-line-names = "", 316 "", 317 "", 318 "", 319 "", 320 "", 321 "SODIMM_143", 322 "SODIMM_141", 323 "", 324 "", 325 "SODIMM_161", 326 "", 327 "SODIMM_84", 328 "SODIMM_78", 329 "SODIMM_74", 330 "SODIMM_80", 331 "SODIMM_82", 332 "SODIMM_70", 333 "SODIMM_72"; 334 335 ctrl-sleep-moci-hog { 336 gpio-hog; 337 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ 338 gpios = <29 GPIO_ACTIVE_HIGH>; 339 line-name = "CTRL_SLEEP_MOCI#"; 340 output-high; 341 pinctrl-names = "default"; 342 pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; 343 }; 344}; 345 346&gpio3 { 347 gpio-line-names = "SODIMM_52", 348 "SODIMM_54", 349 "", 350 "", 351 "", 352 "", 353 "SODIMM_56", 354 "SODIMM_58", 355 "SODIMM_60", 356 "SODIMM_62", 357 "", 358 "", 359 "", 360 "", 361 "SODIMM_66", 362 "", 363 "SODIMM_64", 364 "", 365 "", 366 "SODIMM_34", 367 "SODIMM_19", 368 "", 369 "SODIMM_32", 370 "", 371 "", 372 "SODIMM_30", 373 "SODIMM_59", 374 "SODIMM_57", 375 "SODIMM_63", 376 "SODIMM_61"; 377}; 378 379&gpio4 { 380 gpio-line-names = "SODIMM_252", 381 "SODIMM_222", 382 "SODIMM_36", 383 "SODIMM_220", 384 "SODIMM_193", 385 "SODIMM_191", 386 "SODIMM_201", 387 "SODIMM_203", 388 "SODIMM_205", 389 "SODIMM_207", 390 "SODIMM_199", 391 "SODIMM_197", 392 "SODIMM_221", 393 "SODIMM_219", 394 "SODIMM_217", 395 "SODIMM_215", 396 "SODIMM_211", 397 "SODIMM_213", 398 "SODIMM_189", 399 "SODIMM_244", 400 "SODIMM_38", 401 "", 402 "SODIMM_76", 403 "SODIMM_135", 404 "SODIMM_133", 405 "SODIMM_17", 406 "SODIMM_24", 407 "SODIMM_26", 408 "SODIMM_21", 409 "SODIMM_256", 410 "SODIMM_48", 411 "SODIMM_44"; 412}; 413 414/* On-module I2C */ 415&i2c1 { 416 clock-frequency = <400000>; 417 pinctrl-names = "default", "gpio"; 418 pinctrl-0 = <&pinctrl_i2c1>; 419 pinctrl-1 = <&pinctrl_i2c1_gpio>; 420 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 421 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 422 status = "okay"; 423 424 pca9450: pmic@25 { 425 compatible = "nxp,pca9450c"; 426 interrupt-parent = <&gpio1>; 427 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ 428 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 429 pinctrl-names = "default"; 430 pinctrl-0 = <&pinctrl_pmic>; 431 reg = <0x25>; 432 sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 433 434 /* 435 * The bootloader is expected to switch on LDO4 for the on-module +V3.3_ADC and the 436 * I2C level shifter for the TLA2024 ADC behind this PMIC. 437 */ 438 439 regulators { 440 BUCK1 { 441 regulator-always-on; 442 regulator-boot-on; 443 regulator-max-microvolt = <1000000>; 444 regulator-min-microvolt = <720000>; 445 regulator-name = "On-module +VDD_SOC (BUCK1)"; 446 regulator-ramp-delay = <3125>; 447 }; 448 449 BUCK2 { 450 nxp,dvs-run-voltage = <950000>; 451 nxp,dvs-standby-voltage = <850000>; 452 regulator-always-on; 453 regulator-boot-on; 454 regulator-max-microvolt = <1025000>; 455 regulator-min-microvolt = <720000>; 456 regulator-name = "On-module +VDD_ARM (BUCK2)"; 457 regulator-ramp-delay = <3125>; 458 }; 459 460 reg_vdd_3v3: BUCK4 { 461 regulator-always-on; 462 regulator-boot-on; 463 regulator-max-microvolt = <3300000>; 464 regulator-min-microvolt = <3300000>; 465 regulator-name = "On-module +V3.3 (BUCK4)"; 466 }; 467 468 reg_vdd_1v8: BUCK5 { 469 regulator-always-on; 470 regulator-boot-on; 471 regulator-max-microvolt = <1800000>; 472 regulator-min-microvolt = <1800000>; 473 regulator-name = "PWR_1V8_MOCI (BUCK5)"; 474 }; 475 476 BUCK6 { 477 regulator-always-on; 478 regulator-boot-on; 479 regulator-max-microvolt = <1155000>; 480 regulator-min-microvolt = <1045000>; 481 regulator-name = "On-module +VDD_DDR (BUCK6)"; 482 }; 483 484 LDO1 { 485 regulator-always-on; 486 regulator-boot-on; 487 regulator-max-microvolt = <1950000>; 488 regulator-min-microvolt = <1650000>; 489 regulator-name = "On-module +V1.8_SNVS (LDO1)"; 490 }; 491 492 LDO2 { 493 regulator-always-on; 494 regulator-boot-on; 495 regulator-max-microvolt = <1150000>; 496 regulator-min-microvolt = <800000>; 497 regulator-name = "On-module +V0.8_SNVS (LDO2)"; 498 }; 499 500 LDO3 { 501 regulator-always-on; 502 regulator-boot-on; 503 regulator-max-microvolt = <1800000>; 504 regulator-min-microvolt = <1800000>; 505 regulator-name = "On-module +V1.8A (LDO3)"; 506 }; 507 508 LDO4 { 509 regulator-always-on; 510 regulator-boot-on; 511 regulator-max-microvolt = <3300000>; 512 regulator-min-microvolt = <3300000>; 513 regulator-name = "On-module +V3.3_ADC (LDO4)"; 514 }; 515 516 LDO5 { 517 regulator-max-microvolt = <3300000>; 518 regulator-min-microvolt = <1800000>; 519 regulator-name = "On-module +V3.3_1.8_SD (LDO5)"; 520 }; 521 }; 522 }; 523 524 rtc_i2c: rtc@32 { 525 compatible = "epson,rx8130"; 526 reg = <0x32>; 527 }; 528 529 /* On-module temperature sensor */ 530 hwmon_temp_module: sensor@48 { 531 compatible = "ti,tmp1075"; 532 reg = <0x48>; 533 vs-supply = <®_vdd_1v8>; 534 }; 535 536 adc@49 { 537 compatible = "ti,ads1015"; 538 reg = <0x49>; 539 #address-cells = <1>; 540 #size-cells = <0>; 541 542 /* Verdin I2C_1 (ADC_4 - ADC_3) */ 543 channel@0 { 544 reg = <0>; 545 ti,datarate = <4>; 546 ti,gain = <2>; 547 }; 548 549 /* Verdin I2C_1 (ADC_4 - ADC_1) */ 550 channel@1 { 551 reg = <1>; 552 ti,datarate = <4>; 553 ti,gain = <2>; 554 }; 555 556 /* Verdin I2C_1 (ADC_3 - ADC_1) */ 557 channel@2 { 558 reg = <2>; 559 ti,datarate = <4>; 560 ti,gain = <2>; 561 }; 562 563 /* Verdin I2C_1 (ADC_2 - ADC_1) */ 564 channel@3 { 565 reg = <3>; 566 ti,datarate = <4>; 567 ti,gain = <2>; 568 }; 569 570 /* Verdin I2C_1 ADC_4 */ 571 channel@4 { 572 reg = <4>; 573 ti,datarate = <4>; 574 ti,gain = <2>; 575 }; 576 577 /* Verdin I2C_1 ADC_3 */ 578 channel@5 { 579 reg = <5>; 580 ti,datarate = <4>; 581 ti,gain = <2>; 582 }; 583 584 /* Verdin I2C_1 ADC_2 */ 585 channel@6 { 586 reg = <6>; 587 ti,datarate = <4>; 588 ti,gain = <2>; 589 }; 590 591 /* Verdin I2C_1 ADC_1 */ 592 channel@7 { 593 reg = <7>; 594 ti,datarate = <4>; 595 ti,gain = <2>; 596 }; 597 }; 598 599 eeprom@50 { 600 compatible = "st,24c02"; 601 pagesize = <16>; 602 reg = <0x50>; 603 }; 604}; 605 606/* Verdin I2C_2_DSI */ 607&i2c2 { 608 /* Lower frequency to avoid DDC/EDID issues with certain displays/screens. */ 609 clock-frequency = <10000>; 610 pinctrl-names = "default", "gpio"; 611 pinctrl-0 = <&pinctrl_i2c2>; 612 pinctrl-1 = <&pinctrl_i2c2_gpio>; 613 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 614 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 615 616 atmel_mxt_ts_mezzanine: touch-mezzanine@4a { 617 compatible = "atmel,maxtouch"; 618 /* Verdin GPIO_3 (SODIMM 210) */ 619 interrupt-parent = <&gpio1>; 620 interrupts = <5 IRQ_TYPE_EDGE_FALLING>; 621 reg = <0x4a>; 622 /* Verdin GPIO_2 (SODIMM 208) */ 623 reset-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 624 status = "disabled"; 625 }; 626}; 627 628/* TODO: Verdin I2C_3_HDMI */ 629 630/* Verdin I2C_4_CSI */ 631&i2c3 { 632 clock-frequency = <400000>; 633 pinctrl-names = "default", "gpio"; 634 pinctrl-0 = <&pinctrl_i2c3>; 635 pinctrl-1 = <&pinctrl_i2c3_gpio>; 636 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 637 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 638}; 639 640/* Verdin I2C_1 */ 641&i2c4 { 642 clock-frequency = <400000>; 643 pinctrl-names = "default", "gpio"; 644 pinctrl-0 = <&pinctrl_i2c4>; 645 pinctrl-1 = <&pinctrl_i2c4_gpio>; 646 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 647 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 648 649 gpio_expander_21: gpio-expander@21 { 650 compatible = "nxp,pcal6416"; 651 #gpio-cells = <2>; 652 gpio-controller; 653 reg = <0x21>; 654 vcc-supply = <®_3p3v>; 655 status = "disabled"; 656 }; 657 658 lvds_ti_sn65dsi83: bridge@2c { 659 compatible = "ti,sn65dsi83"; 660 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ 661 /* Verdin GPIO_10_DSI (SODIMM 21) */ 662 enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; 663 pinctrl-names = "default"; 664 pinctrl-0 = <&pinctrl_gpio_10_dsi>; 665 reg = <0x2c>; 666 status = "disabled"; 667 }; 668 669 /* Current measurement into module VCC */ 670 hwmon: hwmon@40 { 671 compatible = "ti,ina219"; 672 reg = <0x40>; 673 shunt-resistor = <10000>; 674 status = "disabled"; 675 }; 676 677 hdmi_lontium_lt8912: hdmi@48 { 678 compatible = "lontium,lt8912b"; 679 pinctrl-names = "default"; 680 pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>; 681 reg = <0x48>; 682 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */ 683 /* Verdin GPIO_10_DSI (SODIMM 21) */ 684 reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; 685 status = "disabled"; 686 }; 687 688 atmel_mxt_ts: touch@4a { 689 compatible = "atmel,maxtouch"; 690 /* 691 * Verdin GPIO_9_DSI 692 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused) 693 */ 694 interrupt-parent = <&gpio4>; 695 interrupts = <25 IRQ_TYPE_EDGE_FALLING>; 696 pinctrl-names = "default"; 697 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; 698 reg = <0x4a>; 699 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */ 700 reset-gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; 701 status = "disabled"; 702 }; 703 704 /* Temperature sensor on carrier board */ 705 hwmon_temp: sensor@4f { 706 compatible = "ti,tmp75c"; 707 reg = <0x4f>; 708 status = "disabled"; 709 }; 710 711 /* EEPROM on display adapter (MIPI DSI Display Adapter) */ 712 eeprom_display_adapter: eeprom@50 { 713 compatible = "st,24c02"; 714 pagesize = <16>; 715 reg = <0x50>; 716 status = "disabled"; 717 }; 718 719 /* EEPROM on carrier board */ 720 eeprom_carrier_board: eeprom@57 { 721 compatible = "st,24c02"; 722 pagesize = <16>; 723 reg = <0x57>; 724 status = "disabled"; 725 }; 726}; 727 728/* TODO: Verdin PCIE_1 */ 729 730/* Verdin PWM_1 */ 731&pwm1 { 732 pinctrl-names = "default"; 733 pinctrl-0 = <&pinctrl_pwm_1>; 734 #pwm-cells = <3>; 735}; 736 737/* Verdin PWM_2 */ 738&pwm2 { 739 pinctrl-names = "default"; 740 pinctrl-0 = <&pinctrl_pwm_2>; 741 #pwm-cells = <3>; 742}; 743 744/* Verdin PWM_3_DSI */ 745&pwm3 { 746 pinctrl-names = "default"; 747 pinctrl-0 = <&pinctrl_pwm_3>; 748 #pwm-cells = <3>; 749}; 750 751/* TODO: Verdin I2S_1 */ 752 753/* TODO: Verdin I2S_2 */ 754 755&snvs_pwrkey { 756 status = "okay"; 757}; 758 759/* Verdin UART_1 */ 760&uart1 { 761 pinctrl-names = "default"; 762 pinctrl-0 = <&pinctrl_uart1>; 763 uart-has-rtscts; 764}; 765 766/* Verdin UART_2 */ 767&uart2 { 768 pinctrl-names = "default"; 769 pinctrl-0 = <&pinctrl_uart2>; 770 uart-has-rtscts; 771}; 772 773/* Verdin UART_3, used as the Linux Console */ 774&uart3 { 775 pinctrl-names = "default"; 776 pinctrl-0 = <&pinctrl_uart3>; 777}; 778 779/* Verdin UART_4, used for Bluetooth on Wi-Fi/Bluetooth SKUs */ 780&uart4 { 781 pinctrl-names = "default"; 782 pinctrl-0 = <&pinctrl_uart4>; 783}; 784 785/* Verdin USB_1 */ 786&usb3_phy0 { 787 vbus-supply = <®_usb1_vbus>; 788}; 789 790&usb_dwc3_0 { 791 adp-disable; 792 dr_mode = "otg"; 793 hnp-disable; 794 maximum-speed = "high-speed"; 795 over-current-active-low; 796 pinctrl-names = "default"; 797 pinctrl-0 = <&pinctrl_usb_1_id>; 798 srp-disable; 799}; 800 801/* Verdin USB_2 */ 802&usb3_phy1 { 803 vbus-supply = <®_usb2_vbus>; 804}; 805 806&usb_dwc3_1 { 807 disable-over-current; 808 dr_mode = "host"; 809}; 810 811/* Verdin SD_1 */ 812&usdhc2 { 813 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; 814 assigned-clock-rates = <400000000>; 815 bus-width = <4>; 816 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 817 disable-wp; 818 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 819 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; 820 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; 821 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; 822 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; 823 vmmc-supply = <®_usdhc2_vmmc>; 824}; 825 826/* On-module eMMC */ 827&usdhc3 { 828 assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>; 829 assigned-clock-rates = <400000000>; 830 bus-width = <8>; 831 non-removable; 832 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 833 pinctrl-0 = <&pinctrl_usdhc3>; 834 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 835 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 836 status = "okay"; 837}; 838 839&wdog1 { 840 fsl,ext-reset-output; 841 pinctrl-names = "default"; 842 pinctrl-0 = <&pinctrl_wdog>; 843 status = "okay"; 844}; 845 846&iomuxc { 847 pinctrl_bt_uart: btuartgrp { 848 fsl,pins = 849 <MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x1c4>, 850 <MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x1c4>, 851 <MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x1c4>, 852 <MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x1c4>; 853 }; 854 855 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { 856 fsl,pins = 857 <MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1c4>; /* SODIMM 256 */ 858 }; 859 860 pinctrl_ecspi1: ecspi1grp { 861 fsl,pins = 862 <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c4>, /* SODIMM 198 */ 863 <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x4>, /* SODIMM 200 */ 864 <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x4>, /* SODIMM 196 */ 865 <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c4>; /* SODIMM 202 */ 866 }; 867 868 /* Connection On Board PHY */ 869 pinctrl_eqos: eqosgrp { 870 fsl,pins = 871 <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3>, 872 <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3>, 873 <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91>, 874 <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91>, 875 <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91>, 876 <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91>, 877 <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91>, 878 <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91>, 879 <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f>, 880 <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f>, 881 <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f>, 882 <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f>, 883 <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f>, 884 <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f>; 885 }; 886 887 /* ETH_INT# shared with TPM_INT# (usually N/A) */ 888 pinctrl_eth_tpm_int: ethtpmintgrp { 889 fsl,pins = 890 <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c4>; 891 }; 892 893 /* Connection Carrier Board PHY ETH_2 */ 894 pinctrl_fec: fecgrp { 895 fsl,pins = 896 <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, /* SODIMM 193 */ 897 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, /* SODIMM 191 */ 898 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, /* SODIMM 201 */ 899 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, /* SODIMM 203 */ 900 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, /* SODIMM 205 */ 901 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, /* SODIMM 207 */ 902 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, /* SODIMM 197 */ 903 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, /* SODIMM 199 */ 904 <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f>, /* SODIMM 221 */ 905 <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f>, /* SODIMM 219 */ 906 <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f>, /* SODIMM 217 */ 907 <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f>, /* SODIMM 215 */ 908 <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f>, /* SODIMM 211 */ 909 <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f>, /* SODIMM 213 */ 910 <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x1c4>; /* SODIMM 189 */ 911 }; 912 913 pinctrl_fec_sleep: fecsleepgrp { 914 fsl,pins = 915 <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, /* SODIMM 193 */ 916 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, /* SODIMM 191 */ 917 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, /* SODIMM 201 */ 918 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, /* SODIMM 203 */ 919 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, /* SODIMM 205 */ 920 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, /* SODIMM 207 */ 921 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, /* SODIMM 197 */ 922 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, /* SODIMM 199 */ 923 <MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x1f>, /* SODIMM 221 */ 924 <MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x1f>, /* SODIMM 219 */ 925 <MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x1f>, /* SODIMM 217 */ 926 <MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15 0x1f>, /* SODIMM 215 */ 927 <MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x1f>, /* SODIMM 211 */ 928 <MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x1f>, /* SODIMM 213 */ 929 <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x184>; /* SODIMM 189 */ 930 }; 931 932 pinctrl_flexcan1: flexcan1grp { 933 fsl,pins = 934 <MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154>, /* SODIMM 22 */ 935 <MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154>; /* SODIMM 20 */ 936 }; 937 938 pinctrl_flexcan2: flexcan2grp { 939 fsl,pins = 940 <MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154>, /* SODIMM 26 */ 941 <MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154>; /* SODIMM 24 */ 942 }; 943 944 pinctrl_flexspi0: flexspi0grp { 945 fsl,pins = 946 <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2>, /* SODIMM 52 */ 947 <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>, /* SODIMM 54 */ 948 <MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x82>, /* SODIMM 66 */ 949 <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>, /* SODIMM 56 */ 950 <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>, /* SODIMM 58 */ 951 <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>, /* SODIMM 60 */ 952 <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>, /* SODIMM 62 */ 953 <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x82>; /* SODIMM 64 */ 954 }; 955 956 pinctrl_gpio1: gpio1grp { 957 fsl,pins = 958 <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x184>; /* SODIMM 206 */ 959 }; 960 961 pinctrl_gpio2: gpio2grp { 962 fsl,pins = 963 <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x1c4>; /* SODIMM 208 */ 964 }; 965 966 pinctrl_gpio3: gpio3grp { 967 fsl,pins = 968 <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x184>; /* SODIMM 210 */ 969 }; 970 971 pinctrl_gpio4: gpio4grp { 972 fsl,pins = 973 <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x184>; /* SODIMM 212 */ 974 }; 975 976 pinctrl_gpio5: gpio5grp { 977 fsl,pins = 978 <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x184>; /* SODIMM 216 */ 979 }; 980 981 pinctrl_gpio6: gpio6grp { 982 fsl,pins = 983 <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x184>; /* SODIMM 218 */ 984 }; 985 986 pinctrl_gpio7: gpio7grp { 987 fsl,pins = 988 <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x184>; /* SODIMM 220 */ 989 }; 990 991 pinctrl_gpio8: gpio8grp { 992 fsl,pins = 993 <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x184>; /* SODIMM 222 */ 994 }; 995 996 /* Verdin GPIO_9_DSI (pulled-up as active-low) */ 997 pinctrl_gpio_9_dsi: gpio9dsigrp { 998 fsl,pins = 999 <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x1c4>; /* SODIMM 17 */ 1000 }; 1001 1002 /* Verdin GPIO_10_DSI */ 1003 pinctrl_gpio_10_dsi: gpio10dsigrp { 1004 fsl,pins = 1005 <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1c4>; /* SODIMM 21 */ 1006 }; 1007 1008 /* Non-wifi MSP usage only */ 1009 pinctrl_gpio_hog1: gpiohog1grp { 1010 fsl,pins = 1011 <MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1c4>, /* SODIMM 116 */ 1012 <MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x1c4>, /* SODIMM 152 */ 1013 <MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x1c4>, /* SODIMM 164 */ 1014 <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c4>; /* SODIMM 128 */ 1015 }; 1016 1017 /* USB_2_OC# */ 1018 pinctrl_gpio_hog2: gpiohog2grp { 1019 fsl,pins = 1020 <MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1c4>; /* SODIMM 187 */ 1021 }; 1022 1023 pinctrl_gpio_hog3: gpiohog3grp { 1024 fsl,pins = 1025 <MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x1c4>, /* SODIMM 157 */ 1026 /* CSI_1_MCLK */ 1027 <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1c4>; /* SODIMM 91 */ 1028 }; 1029 1030 /* Wifi usage only */ 1031 pinctrl_gpio_hog4: gpiohog4grp { 1032 fsl,pins = 1033 <MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x1c4>, /* SODIMM 151 */ 1034 <MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29 0x1c4>; /* SODIMM 153 */ 1035 }; 1036 1037 pinctrl_gpio_keys: gpiokeysgrp { 1038 fsl,pins = 1039 <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x1c4>; /* SODIMM 252 */ 1040 }; 1041 1042 pinctrl_hdmi_hog: hdmihoggrp { 1043 fsl,pins = 1044 <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019>, /* SODIMM 63 */ 1045 <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3>, /* SODIMM 59 */ 1046 <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3>, /* SODIMM 57 */ 1047 <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019>; /* SODIMM 61 */ 1048 }; 1049 1050 /* On-module I2C */ 1051 pinctrl_i2c1: i2c1grp { 1052 fsl,pins = 1053 <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c6>, /* PMIC_I2C_SCL */ 1054 <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c6>; /* PMIC_I2C_SDA */ 1055 }; 1056 1057 pinctrl_i2c1_gpio: i2c1gpiogrp { 1058 fsl,pins = 1059 <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c6>, /* PMIC_I2C_SCL */ 1060 <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c6>; /* PMIC_I2C_SDA */ 1061 }; 1062 1063 /* Verdin I2C_2_DSI */ 1064 pinctrl_i2c2: i2c2grp { 1065 fsl,pins = 1066 <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c6>, /* SODIMM 55 */ 1067 <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c6>; /* SODIMM 53 */ 1068 }; 1069 1070 pinctrl_i2c2_gpio: i2c2gpiogrp { 1071 fsl,pins = 1072 <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c6>, /* SODIMM 55 */ 1073 <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c6>; /* SODIMM 53 */ 1074 }; 1075 1076 /* Verdin I2C_4_CSI */ 1077 pinctrl_i2c3: i2c3grp { 1078 fsl,pins = 1079 <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c6>, /* SODIMM 95 */ 1080 <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c6>; /* SODIMM 93 */ 1081 }; 1082 1083 pinctrl_i2c3_gpio: i2c3gpiogrp { 1084 fsl,pins = 1085 <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c6>, /* SODIMM 95 */ 1086 <MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c6>; /* SODIMM 93 */ 1087 }; 1088 1089 /* Verdin I2C_1 */ 1090 pinctrl_i2c4: i2c4grp { 1091 fsl,pins = 1092 <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c6>, /* SODIMM 14 */ 1093 <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c6>; /* SODIMM 12 */ 1094 }; 1095 1096 pinctrl_i2c4_gpio: i2c4gpiogrp { 1097 fsl,pins = 1098 <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c6>, /* SODIMM 14 */ 1099 <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c6>; /* SODIMM 12 */ 1100 }; 1101 1102 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ 1103 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { 1104 fsl,pins = 1105 <MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x184>; /* SODIMM 42 */ 1106 }; 1107 1108 /* Verdin I2S_2_D_OUT shared with SAI3 */ 1109 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { 1110 fsl,pins = 1111 <MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x184>; /* SODIMM 46 */ 1112 }; 1113 1114 pinctrl_pcie: pciegrp { 1115 fsl,pins = 1116 <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x4>, /* SODIMM 244 */ 1117 <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x1c4>; /* PMIC_EN_PCIe_CLK, unused */ 1118 }; 1119 1120 pinctrl_pmic: pmicirqgrp { 1121 fsl,pins = 1122 <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c4>; /* PMIC_INT# */ 1123 }; 1124 1125 pinctrl_pwm_1: pwm1grp { 1126 fsl,pins = 1127 <MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x6>; /* SODIMM 15 */ 1128 }; 1129 1130 pinctrl_pwm_2: pwm2grp { 1131 fsl,pins = 1132 <MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x6>; /* SODIMM 16 */ 1133 }; 1134 1135 /* Verdin PWM_3_DSI shared with GPIO3_IO20 */ 1136 pinctrl_pwm_3: pwm3grp { 1137 fsl,pins = 1138 <MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x6>; /* SODIMM 19 */ 1139 }; 1140 1141 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM3_OUT */ 1142 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsi1hpdgpiogrp { 1143 fsl,pins = 1144 <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x184>; /* SODIMM 19 */ 1145 }; 1146 1147 pinctrl_reg_eth: regethgrp { 1148 fsl,pins = 1149 <MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x184>; /* PMIC_EN_ETH */ 1150 }; 1151 1152 pinctrl_sai1: sai1grp { 1153 fsl,pins = 1154 <MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x96>, /* SODIMM 38 */ 1155 <MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x1d6>, /* SODIMM 36 */ 1156 <MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x1d6>, /* SODIMM 30 */ 1157 <MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x1d6>, /* SODIMM 32 */ 1158 <MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x96>; /* SODIMM 34 */ 1159 }; 1160 1161 pinctrl_sai3: sai3grp { 1162 fsl,pins = 1163 <MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x1d6>, /* SODIMM 48 */ 1164 <MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x1d6>, /* SODIMM 42 */ 1165 <MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x96>, /* SODIMM 46 */ 1166 <MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x1d6>; /* SODIMM 44 */ 1167 }; 1168 1169 pinctrl_uart1: uart1grp { 1170 fsl,pins = 1171 <MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1c4>, /* SODIMM 135 */ 1172 <MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1c4>, /* SODIMM 133 */ 1173 <MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x1c4>, /* SODIMM 129 */ 1174 <MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x1c4>; /* SODIMM 131 */ 1175 }; 1176 1177 pinctrl_uart2: uart2grp { 1178 fsl,pins = 1179 <MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x1c4>, /* SODIMM 143 */ 1180 <MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x1c4>, /* SODIMM 141 */ 1181 <MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x1c4>, /* SODIMM 137 */ 1182 <MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x1c4>; /* SODIMM 139 */ 1183 }; 1184 1185 pinctrl_uart3: uart3grp { 1186 fsl,pins = 1187 <MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x1c4>, /* SODIMM 147 */ 1188 <MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x1c4>; /* SODIMM 149 */ 1189 }; 1190 1191 /* Non-wifi usage only */ 1192 pinctrl_uart4: uart4grp { 1193 fsl,pins = 1194 <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x1c4>, /* SODIMM 151 */ 1195 <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x1c4>; /* SODIMM 153 */ 1196 }; 1197 1198 pinctrl_usb1_vbus: usb1vbusgrp { 1199 fsl,pins = 1200 <MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x19>; /* SODIMM 155 */ 1201 }; 1202 1203 /* USB_1_ID */ 1204 pinctrl_usb_1_id: usb1idgrp { 1205 fsl,pins = 1206 <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x1c4>; /* SODIMM 161 */ 1207 }; 1208 1209 pinctrl_usb2_vbus: usb2vbusgrp { 1210 fsl,pins = 1211 <MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x19>; /* SODIMM 185 */ 1212 }; 1213 1214 /* On-module Wi-Fi */ 1215 pinctrl_usdhc1: usdhc1grp { 1216 fsl,pins = 1217 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190>, 1218 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0>, 1219 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0>, 1220 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0>, 1221 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0>, 1222 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0>; 1223 }; 1224 1225 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 1226 fsl,pins = 1227 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194>, 1228 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4>, 1229 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4>, 1230 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4>, 1231 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4>, 1232 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4>; 1233 }; 1234 1235 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1236 fsl,pins = 1237 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196>, 1238 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6>, 1239 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6>, 1240 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6>, 1241 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6>, 1242 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6>; 1243 }; 1244 1245 pinctrl_usdhc2_cd: usdhc2cdgrp { 1246 fsl,pins = 1247 <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4>; /* SODIMM 84 */ 1248 }; 1249 1250 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { 1251 fsl,pins = 1252 <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0>; /* SODIMM 84 */ 1253 }; 1254 1255 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { 1256 fsl,pins = 1257 <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x4>; /* SODIMM 76 */ 1258 }; 1259 1260 pinctrl_usdhc2: usdhc2grp { 1261 fsl,pins = 1262 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>, /* PMIC_USDHC_VSELECT */ 1263 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190>, /* SODIMM 78 */ 1264 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0>, /* SODIMM 74 */ 1265 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0>, /* SODIMM 80 */ 1266 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0>, /* SODIMM 82 */ 1267 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0>, /* SODIMM 70 */ 1268 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0>; /* SODIMM 72 */ 1269 }; 1270 1271 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 1272 fsl,pins = 1273 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>, 1274 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, 1275 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, 1276 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 1277 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 1278 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 1279 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>; 1280 }; 1281 1282 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1283 fsl,pins = 1284 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>, 1285 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196>, 1286 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6>, 1287 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6>, 1288 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6>, 1289 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6>, 1290 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6>; 1291 }; 1292 1293 /* Avoid backfeeding with removed card power */ 1294 pinctrl_usdhc2_sleep: usdhc2slpgrp { 1295 fsl,pins = 1296 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x0>, 1297 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x100>, 1298 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x100>, 1299 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x100>, 1300 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x100>, 1301 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x100>, 1302 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x100>; 1303 }; 1304 1305 pinctrl_usdhc3: usdhc3grp { 1306 fsl,pins = 1307 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>, 1308 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190>, 1309 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0>, 1310 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0>, 1311 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0>, 1312 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0>, 1313 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0>, 1314 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0>, 1315 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0>, 1316 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0>, 1317 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190>, 1318 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0>; 1319 }; 1320 1321 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 1322 fsl,pins = 1323 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>, 1324 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194>, 1325 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>, 1326 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>, 1327 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>, 1328 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>, 1329 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>, 1330 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>, 1331 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>, 1332 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>, 1333 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>, 1334 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>; 1335 }; 1336 1337 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1338 fsl,pins = 1339 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>, 1340 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196>, 1341 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2>, 1342 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2>, 1343 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2>, 1344 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2>, 1345 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2>, 1346 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2>, 1347 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2>, 1348 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2>, 1349 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196>, 1350 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6>; 1351 }; 1352 1353 pinctrl_wdog: wdoggrp { 1354 fsl,pins = 1355 <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6>; /* PMIC_WDI */ 1356 }; 1357 1358 pinctrl_bluetooth_ctrl: bluetoothctrlgrp { 1359 fsl,pins = 1360 <MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x1c4>; /* WIFI_WKUP_BT */ 1361 }; 1362 1363 pinctrl_wifi_ctrl: wifictrlgrp { 1364 fsl,pins = 1365 <MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x1c4>; /* WIFI_WKUP_WLAN */ 1366 }; 1367 1368 pinctrl_wifi_i2s: wifii2sgrp { 1369 fsl,pins = 1370 <MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x1d6>, /* WIFI_TX_SYNC */ 1371 <MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x96>, /* WIFI_RX_DATA0 */ 1372 <MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x1d6>, /* WIFI_TX_BCLK */ 1373 <MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x1d6>; /* WIFI_TX_DATA0 */ 1374 }; 1375 1376 pinctrl_wifi_pwr_en: wifipwrengrp { 1377 fsl,pins = 1378 <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x184>; /* PMIC_EN_WIFI */ 1379 }; 1380};