cachepc-linux

imx8mq-tqma8mq-mba8mx.dts (9309B)

// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
/*
 * Copyright 2019-2021 TQ-Systems GmbH
 */

/dts-v1/;

#include "imx8mq-tqma8mq.dtsi"
#include "mba8mx.dtsi"

/ {
	model = "TQ-Systems GmbH i.MX8MQ TQMa8MQ on MBa8Mx";
	compatible = "tq,imx8mq-tqma8mq-mba8mx", "tq,imx8mq-tqma8mq", "fsl,imx8mq";

	aliases {
		eeprom0 = &eeprom3;
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		rtc0 = &pcf85063;
		rtc1 = &snvs_rtc;
	};

	extcon_usbotg: extcon-usbotg0 {
		compatible = "linux,extcon-usb-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usbcon0>;
		id-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
	};

	pcie0_refclk: pcie0-refclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};

	pcie1_refclk: pcie1-refclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};

	reg_otg_vbus: regulator-otg-vbus {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_regotgvbus>;
		regulator-name = "MBA8MQ_OTG_VBUS";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	reg_usdhc2_vmmc: regulator-vmmc {
		compatible = "regulator-fixed";
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};
};

&btn2 {
	gpios = <&gpio3 17 GPIO_ACTIVE_LOW>;
};

&gpio_leds {
	led3 {
		label = "led3";
		gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
	};
};

&i2c1 {
	expander2: gpio@25 {
		compatible = "nxp,pca9555";
		reg = <0x25>;
		gpio-controller;
		#gpio-cells = <2>;
		vcc-supply = <&reg_vcc_3v3>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_expander>;
		interrupt-parent = <&gpio1>;
		interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
		interrupt-controller;
		#interrupt-cells = <2>;

		mpcie-rst-hog {
			gpio-hog;
			gpios = <13 0>;
			output-high;
			line-name = "MPCIE_RST#";
		};
	};
};

&irqsteer {
	status = "okay";
};

&led2 {
	gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
};

&pcie0 {
	reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
	clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
		 <&clk IMX8MQ_CLK_PCIE1_AUX>,
		 <&clk IMX8MQ_CLK_PCIE1_PHY>,
		 <&pcie0_refclk>;
	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
	epdev_on-supply = <&reg_vcc_3v3>;
	hard-wired = <1>;
	status = "okay";
};

/*
 * miniPCIe, also usable for cards with USB. Therefore configure the reset as
 * static gpio hog.
 */
&pcie1 {
	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
		 <&pcie1_refclk>;
	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
	epdev_on-supply = <&reg_vcc_3v3>;
	hard-wired = <1>;
	status = "okay";
};

&sai3 {
	assigned-clocks = <&clk IMX8MQ_CLK_SAI3>;
	assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
	clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, <&clk IMX8MQ_CLK_DUMMY>,
		<&clk IMX8MQ_CLK_SAI3_ROOT>, <&clk IMX8MQ_CLK_DUMMY>,
		<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>,
		<&clk IMX8MQ_AUDIO_PLL2_OUT>;
};

&tlv320aic3x04 {
	clock-names = "mclk";
	clocks = <&clk IMX8MQ_CLK_SAI3_ROOT>;
};

&uart1 {
	assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
};

&uart2 {
	assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
};

/* console */
&uart3 {
	assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
};

&usb3_phy0 {
	vbus-supply = <&reg_otg_vbus>;
	status = "okay";
};

&usb_dwc3_0 {
	/* we implement dual role but not full featured OTG */
	extcon = <&extcon_usbotg>;
	hnp-disable;
	srp-disable;
	adp-disable;
	/* OC not supported due to non matching active polarity */
	disable-over-current;
	dr_mode = "otg";
	status = "okay";
};

&usb3_phy1 {
	status = "okay";
};

&usb_dwc3_1 {
	status = "okay";
	dr_mode = "host";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&iomuxc {
	pinctrl_ecspi1: ecspi1grp {
		fsl,pins = <MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK	0x0000004e>,
			   <MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI	0x0000004e>,
			   <MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO	0x0000004e>,
			   <MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x0000004e>;
	};

	pinctrl_ecspi2: ecspi2grp {
		fsl,pins = <MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0x0000004e>,
			   <MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0x0000004e>,
			   <MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0x0000004e>,
			   <MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13		0x0000004e>;
	};

	pinctrl_expander: expandergrp {
		fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9		0xd6>;
	};

	pinctrl_fec1: fec1grp {
		fsl,pins = <MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC		0x3>,
			   <MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO		0x23>,
			   <MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f>,
			   <MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f>,
			   <MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f>,
			   <MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f>,
			   <MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91>,
			   <MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91>,
			   <MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91>,
			   <MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91>,
			   <MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f>,
			   <MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91>,
			   <MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91>,
			   <MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f>;
	};

	pinctrl_gpiobutton: gpiobuttongrp {
		fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5		0x41>,
			   <MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x41>,
			   <MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17		0x41>;
	};

	pinctrl_gpioled: gpioledgrp {
		fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x41>,
			   <MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8		0x41>,
			   <MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16	0x41>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL		0x40000067>,
			   <MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA		0x40000067>;
	};

	pinctrl_i2c2_gpio: i2c2gpiogrp {
		fsl,pins = <MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16		0x40000067>,
			   <MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17		0x40000067>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL		0x40000067>,
			   <MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA		0x40000067>;
	};

	pinctrl_i2c3_gpio: i2c3gpiogrp {
		fsl,pins = <MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18		0x40000067>,
			   <MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19		0x40000067>;
	};

	pinctrl_pwm3: pwm3grp {
		fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT		0x16>;
	};

	pinctrl_pwm4: pwm4grp {
		fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT		0x16>;
	};

	pinctrl_regotgvbus: reggotgvbusgrp {
		/* USB1 OTG PWR as GPIO */
		fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12		0x06>;
	};

	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
		fsl,pins = <MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19		0xc1>;
	};

	pinctrl_sai3: sai3grp {
		fsl,pins = <MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK		0xd6>,
			   <MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK		0xd6>,
			   <MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC		0xd6>,
			   <MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0		0xd6>,
			   <MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC		0xd6>,
			   <MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0		0xd6>,
			   <MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK		0xd6>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x79>,
			   <MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x79>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x79>,
			   <MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x79>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX		0x79>,
			   <MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX		0x79>;
	};

	pinctrl_uart4: uart4grp {
		fsl,pins = <MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX		0x79>,
			   <MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX		0x79>;
	};

	pinctrl_usbcon0: usb0congrp {
		/* ID: floating / high: device, low: host -> use PU */
		fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10		0xe6>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x83>,
			   <MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc3>,
			   <MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3>,
			   <MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3>,
			   <MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3>,
			   <MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3>,
			   <MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc1>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x85>,
			   <MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc5>,
			   <MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc5>,
			   <MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc5>,
			   <MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc5>,
			   <MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc5>,
			   <MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc1>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK		0x9f>,
			   <MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD		0xc7>,
			   <MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc7>,
			   <MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc7>,
			   <MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc7>,
			   <MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc7>,
			   <MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0xc1>;
	};

	pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
		fsl,pins = <MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12		0x41>;
	};
};