cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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imx8qm-mek.dts (3676B)

      1// SPDX-License-Identifier: GPL-2.0+
      2/*
      3 * Copyright 2018-2019 NXP
      4 *	Dong Aisheng <aisheng.dong@nxp.com>
      5 */
      6
      7/dts-v1/;
      8
      9#include "imx8qm.dtsi"
     10
     11/ {
     12	model = "Freescale i.MX8QM MEK";
     13	compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
     14
     15	chosen {
     16		stdout-path = &lpuart0;
     17	};
     18
     19	cpus {
     20		/delete-node/ cpu-map;
     21		/delete-node/ cpu@100;
     22		/delete-node/ cpu@101;
     23	};
     24
     25	memory@80000000 {
     26		device_type = "memory";
     27		reg = <0x00000000 0x80000000 0 0x40000000>;
     28	};
     29
     30	reg_usdhc2_vmmc: usdhc2-vmmc {
     31		compatible = "regulator-fixed";
     32		regulator-name = "SD1_SPWR";
     33		regulator-min-microvolt = <3000000>;
     34		regulator-max-microvolt = <3000000>;
     35		gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
     36		enable-active-high;
     37	};
     38};
     39
     40&lpuart0 {
     41	pinctrl-names = "default";
     42	pinctrl-0 = <&pinctrl_lpuart0>;
     43	status = "okay";
     44};
     45
     46&fec1 {
     47	pinctrl-names = "default";
     48	pinctrl-0 = <&pinctrl_fec1>;
     49	phy-mode = "rgmii-id";
     50	phy-handle = <&ethphy0>;
     51	fsl,magic-packet;
     52	status = "okay";
     53
     54	mdio {
     55		#address-cells = <1>;
     56		#size-cells = <0>;
     57
     58		ethphy0: ethernet-phy@0 {
     59			compatible = "ethernet-phy-ieee802.3-c22";
     60			reg = <0>;
     61		};
     62
     63		ethphy1: ethernet-phy@1 {
     64			compatible = "ethernet-phy-ieee802.3-c22";
     65			reg = <1>;
     66		};
     67	};
     68};
     69
     70&usdhc1 {
     71	pinctrl-names = "default";
     72	pinctrl-0 = <&pinctrl_usdhc1>;
     73	bus-width = <8>;
     74	no-sd;
     75	no-sdio;
     76	non-removable;
     77	status = "okay";
     78};
     79
     80&usdhc2 {
     81	pinctrl-names = "default";
     82	pinctrl-0 = <&pinctrl_usdhc2>;
     83	bus-width = <4>;
     84	vmmc-supply = <&reg_usdhc2_vmmc>;
     85	cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
     86	wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
     87	status = "okay";
     88};
     89
     90&iomuxc {
     91	pinctrl_fec1: fec1grp {
     92		fsl,pins = <
     93			IMX8QM_ENET0_MDC_CONN_ENET0_MDC				0x06000020
     94			IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
     95			IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
     96			IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC		0x06000020
     97			IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0		0x06000020
     98			IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1		0x06000020
     99			IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2		0x06000020
    100			IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3		0x06000020
    101			IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC		0x06000020
    102			IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
    103			IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0		0x06000020
    104			IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1		0x06000020
    105			IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2		0x06000020
    106			IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3		0x06000020
    107		>;
    108	};
    109
    110	pinctrl_lpuart0: lpuart0grp {
    111		fsl,pins = <
    112			IMX8QM_UART0_RX_DMA_UART0_RX				0x06000020
    113			IMX8QM_UART0_TX_DMA_UART0_TX				0x06000020
    114		>;
    115	};
    116
    117	pinctrl_usdhc1: usdhc1grp {
    118		fsl,pins = <
    119			IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK				0x06000041
    120			IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD				0x00000021
    121			IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0			0x00000021
    122			IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1			0x00000021
    123			IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2			0x00000021
    124			IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3			0x00000021
    125			IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4			0x00000021
    126			IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5			0x00000021
    127			IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6			0x00000021
    128			IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7			0x00000021
    129			IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE			0x00000041
    130		>;
    131	};
    132
    133	pinctrl_usdhc2: usdhc2grp {
    134		fsl,pins = <
    135			IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041
    136			IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD			0x00000021
    137			IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0			0x00000021
    138			IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1			0x00000021
    139			IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2			0x00000021
    140			IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3			0x00000021
    141			IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x00000021
    142		>;
    143	};
    144};