cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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hip05-d02.dts (1425B)

      1// SPDX-License-Identifier: GPL-2.0-only
      2/**
      3 * dts file for Hisilicon D02 Development Board
      4 *
      5 * Copyright (C) 2014,2015 HiSilicon Ltd.
      6 */
      7
      8/dts-v1/;
      9
     10#include <dt-bindings/gpio/gpio.h>
     11#include "hip05.dtsi"
     12
     13/ {
     14	model = "Hisilicon Hip05 D02 Development Board";
     15	compatible = "hisilicon,hip05-d02";
     16
     17	memory@0 {
     18		device_type = "memory";
     19		reg = <0x0 0x00000000 0x0 0x80000000>;
     20	};
     21
     22	aliases {
     23		serial0 = &uart0;
     24	};
     25
     26	chosen {
     27		stdout-path = "serial0:115200n8";
     28	};
     29
     30	gpio_keys {
     31		compatible = "gpio-keys";
     32		#address-cells = <1>;
     33		#size-cells = <0>;
     34
     35		pwrbutton {
     36			label = "Power Button";
     37			gpios = <&porta 8 GPIO_ACTIVE_LOW>;
     38			linux,code = <116>;
     39			debounce-interval = <0>;
     40		};
     41	};
     42};
     43
     44&uart0 {
     45	status = "okay";
     46};
     47
     48&peri_gpio0 {
     49	status = "okay";
     50};
     51
     52&lbc {
     53	status = "okay";
     54	#address-cells = <2>;
     55	#size-cells = <1>;
     56	ranges = <0 0 0x0 0x90000000 0x08000000>,
     57		 <1 0 0x0 0x98000000 0x08000000>;
     58
     59	nor-flash@0,0 {
     60		#address-cells = <1>;
     61		#size-cells = <1>;
     62		compatible = "numonyx,js28f00a", "cfi-flash";
     63		reg = <0 0x0 0x08000000>;
     64		bank-width = <2>;
     65		/* The three parts may not used */
     66		partition@0 {
     67			label = "BIOS";
     68			reg = <0x0 0x300000>;
     69		};
     70		partition@300000 {
     71			label = "Linux";
     72			reg = <0x300000 0xa00000>;
     73		};
     74		partition@1000000 {
     75			label = "Rootfs";
     76			reg = <0x01000000 0x02000000>;
     77		};
     78	};
     79
     80	cpld@1,0 {
     81		compatible = "hisilicon,hip05-cpld";
     82		reg = <1 0x0 0x100>;
     83	};
     84};