cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

armada-3720-espressobin-ultra.dts (2849B)

      1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      2/*
      3 * Device Tree file for ESPRESSObin-Ultra board.
      4 * Copyright (C) 2019 Globalscale technologies, Inc.
      5 *
      6 * Jason Hung <jhung@globalscaletechnologies.com>
      7 */
      8
      9/dts-v1/;
     10
     11#include "armada-3720-espressobin.dtsi"
     12
     13/ {
     14	model = "Globalscale Marvell ESPRESSOBin Ultra Board";
     15	compatible = "globalscale,espressobin-ultra", "marvell,armada3720",
     16		     "marvell,armada3710";
     17
     18	aliases {
     19		/* ethernet1 is WAN port */
     20		ethernet1 = &switch0port5;
     21		ethernet2 = &switch0port1;
     22		ethernet3 = &switch0port2;
     23		ethernet4 = &switch0port3;
     24		ethernet5 = &switch0port4;
     25	};
     26
     27	reg_usb3_vbus: usb3-vbus {
     28		compatible = "regulator-fixed";
     29		regulator-name = "usb3-vbus";
     30		regulator-min-microvolt = <5000000>;
     31		regulator-max-microvolt = <5000000>;
     32		enable-active-high;
     33		gpio = <&gpionb 19 GPIO_ACTIVE_HIGH>;
     34	};
     35
     36	usb3_phy: usb3-phy {
     37		compatible = "usb-nop-xceiv";
     38		vcc-supply = <&reg_usb3_vbus>;
     39	};
     40
     41	gpio-leds {
     42		pinctrl-names = "default";
     43		compatible = "gpio-leds";
     44		/* No assigned functions to the LEDs by default */
     45		led1 {
     46			label = "ebin-ultra:blue:led1";
     47			gpios = <&gpionb 11 GPIO_ACTIVE_LOW>;
     48		};
     49		led2 {
     50			label = "ebin-ultra:green:led2";
     51			gpios = <&gpionb 12 GPIO_ACTIVE_LOW>;
     52		};
     53		led3 {
     54			label = "ebin-ultra:red:led3";
     55			gpios = <&gpionb 13 GPIO_ACTIVE_LOW>;
     56		};
     57		led4 {
     58			label = "ebin-ultra:yellow:led4";
     59			gpios = <&gpionb 14 GPIO_ACTIVE_LOW>;
     60		};
     61	};
     62};
     63
     64&sdhci0 {
     65	status = "okay";
     66};
     67
     68&sdhci1 {
     69	status = "disabled";
     70};
     71
     72&spi0 {
     73	flash@0 {
     74		partitions {
     75			compatible = "fixed-partitions";
     76			#address-cells = <1>;
     77			#size-cells = <1>;
     78
     79			partition@0 {
     80				label = "firmware";
     81				reg = <0x0 0x3e0000>;
     82			};
     83			partition@3e0000 {
     84				label = "hw-info";
     85				reg = <0x3e0000 0x10000>;
     86				read-only;
     87			};
     88			partition@3f0000 {
     89				label = "u-boot-env";
     90				reg = <0x3f0000 0x10000>;
     91			};
     92		};
     93	};
     94};
     95
     96&i2c0 {
     97	status = "okay";
     98	pinctrl-names = "default";
     99	pinctrl-0 = <&i2c1_pins>;
    100
    101	clock-frequency = <100000>;
    102
    103	rtc@51 {
    104		compatible = "nxp,pcf8563";
    105		reg = <0x51>;
    106	};
    107};
    108
    109&usb3 {
    110	usb-phy = <&usb3_phy>;
    111};
    112
    113&mdio {
    114	extphy: ethernet-phy@1 {
    115		reg = <1>;
    116
    117		reset-gpios = <&gpionb 2 GPIO_ACTIVE_LOW>;
    118	};
    119};
    120
    121&switch0 {
    122	reg = <3>;
    123
    124	reset-gpios = <&gpiosb 23 GPIO_ACTIVE_LOW>;
    125
    126	ports {
    127		switch0port1: port@1 {
    128			reg = <1>;
    129			label = "lan0";
    130			phy-handle = <&switch0phy0>;
    131		};
    132
    133		switch0port2: port@2 {
    134			reg = <2>;
    135			label = "lan1";
    136			phy-handle = <&switch0phy1>;
    137		};
    138
    139		switch0port3: port@3 {
    140			reg = <3>;
    141			label = "lan2";
    142			phy-handle = <&switch0phy2>;
    143		};
    144
    145		switch0port4: port@4 {
    146			reg = <4>;
    147			label = "lan3";
    148			phy-handle = <&switch0phy3>;
    149		};
    150
    151		switch0port5: port@5 {
    152			reg = <5>;
    153			label = "wan";
    154			phy-handle = <&extphy>;
    155			phy-mode = "sgmii";
    156		};
    157	};
    158
    159	mdio {
    160		switch0phy3: switch0phy3@14 {
    161			reg = <0x14>;
    162		};
    163	};
    164};