cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
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armada-37xx.dtsi (13194B)


      1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      2/*
      3 * Device Tree Include file for Marvell Armada 37xx family of SoCs.
      4 *
      5 * Copyright (C) 2016 Marvell
      6 *
      7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
      8 *
      9 */
     10
     11#include <dt-bindings/interrupt-controller/arm-gic.h>
     12
     13/ {
     14	model = "Marvell Armada 37xx SoC";
     15	compatible = "marvell,armada3700";
     16	interrupt-parent = <&gic>;
     17	#address-cells = <2>;
     18	#size-cells = <2>;
     19
     20	aliases {
     21		serial0 = &uart0;
     22		serial1 = &uart1;
     23	};
     24
     25	reserved-memory {
     26		#address-cells = <2>;
     27		#size-cells = <2>;
     28		ranges;
     29
     30		/*
     31		 * The PSCI firmware region depicted below is the default one
     32		 * and should be updated by the bootloader.
     33		 */
     34		psci-area@4000000 {
     35			reg = <0 0x4000000 0 0x200000>;
     36			no-map;
     37		};
     38	};
     39
     40	cpus {
     41		#address-cells = <1>;
     42		#size-cells = <0>;
     43		cpu0: cpu@0 {
     44			device_type = "cpu";
     45			compatible = "arm,cortex-a53";
     46			reg = <0>;
     47			clocks = <&nb_periph_clk 16>;
     48			enable-method = "psci";
     49		};
     50	};
     51
     52	psci {
     53		compatible = "arm,psci-0.2";
     54		method = "smc";
     55	};
     56
     57	timer {
     58		compatible = "arm,armv8-timer";
     59		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
     60			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
     61			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
     62			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
     63	};
     64
     65	pmu {
     66		compatible = "arm,armv8-pmuv3";
     67		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
     68	};
     69
     70	soc {
     71		compatible = "simple-bus";
     72		#address-cells = <2>;
     73		#size-cells = <2>;
     74		ranges;
     75
     76		internal-regs@d0000000 {
     77			#address-cells = <1>;
     78			#size-cells = <1>;
     79			compatible = "simple-bus";
     80			/* 32M internal register @ 0xd000_0000 */
     81			ranges = <0x0 0x0 0xd0000000 0x2000000>;
     82
     83			wdt: watchdog@8300 {
     84				compatible = "marvell,armada-3700-wdt";
     85				reg = <0x8300 0x40>;
     86				marvell,system-controller = <&cpu_misc>;
     87				clocks = <&xtalclk>;
     88			};
     89
     90			cpu_misc: system-controller@d000 {
     91				compatible = "marvell,armada-3700-cpu-misc",
     92					     "syscon";
     93				reg = <0xd000 0x1000>;
     94			};
     95
     96			spi0: spi@10600 {
     97				compatible = "marvell,armada-3700-spi";
     98				#address-cells = <1>;
     99				#size-cells = <0>;
    100				reg = <0x10600 0xA00>;
    101				clocks = <&nb_periph_clk 7>;
    102				interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
    103				num-cs = <4>;
    104				status = "disabled";
    105			};
    106
    107			i2c0: i2c@11000 {
    108				compatible = "marvell,armada-3700-i2c";
    109				reg = <0x11000 0x24>;
    110				#address-cells = <1>;
    111				#size-cells = <0>;
    112				clocks = <&nb_periph_clk 10>;
    113				interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
    114				mrvl,i2c-fast-mode;
    115				status = "disabled";
    116			};
    117
    118			i2c1: i2c@11080 {
    119				compatible = "marvell,armada-3700-i2c";
    120				reg = <0x11080 0x24>;
    121				#address-cells = <1>;
    122				#size-cells = <0>;
    123				clocks = <&nb_periph_clk 9>;
    124				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
    125				mrvl,i2c-fast-mode;
    126				status = "disabled";
    127			};
    128
    129			avs: avs@11500 {
    130				compatible = "marvell,armada-3700-avs",
    131					     "syscon";
    132				reg = <0x11500 0x40>;
    133			};
    134
    135			uartclk: clock-controller@12010 {
    136				compatible = "marvell,armada-3700-uart-clock";
    137				reg = <0x12010 0x4>, <0x12210 0x4>;
    138				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
    139					 <&tbg 3>, <&xtalclk>;
    140				clock-names = "TBG-A-P", "TBG-B-P", "TBG-A-S",
    141					      "TBG-B-S", "xtal";
    142				#clock-cells = <1>;
    143			};
    144
    145			uart0: serial@12000 {
    146				compatible = "marvell,armada-3700-uart";
    147				reg = <0x12000 0x18>;
    148				clocks = <&uartclk 0>;
    149				interrupts =
    150				<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
    151				<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
    152				<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
    153				interrupt-names = "uart-sum", "uart-tx", "uart-rx";
    154				status = "disabled";
    155			};
    156
    157			uart1: serial@12200 {
    158				compatible = "marvell,armada-3700-uart-ext";
    159				reg = <0x12200 0x30>;
    160				clocks = <&uartclk 1>;
    161				interrupts =
    162				<GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
    163				<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
    164				interrupt-names = "uart-tx", "uart-rx";
    165				status = "disabled";
    166			};
    167
    168			nb_periph_clk: nb-periph-clk@13000 {
    169				compatible = "marvell,armada-3700-periph-clock-nb",
    170					     "syscon";
    171				reg = <0x13000 0x100>;
    172				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
    173				<&tbg 3>, <&xtalclk>;
    174				#clock-cells = <1>;
    175			};
    176
    177			sb_periph_clk: sb-periph-clk@18000 {
    178				compatible = "marvell,armada-3700-periph-clock-sb";
    179				reg = <0x18000 0x100>;
    180				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
    181				<&tbg 3>, <&xtalclk>;
    182				#clock-cells = <1>;
    183			};
    184
    185			tbg: tbg@13200 {
    186				compatible = "marvell,armada-3700-tbg-clock";
    187				reg = <0x13200 0x100>;
    188				clocks = <&xtalclk>;
    189				#clock-cells = <1>;
    190			};
    191
    192			pinctrl_nb: pinctrl@13800 {
    193				compatible = "marvell,armada3710-nb-pinctrl",
    194					     "syscon", "simple-mfd";
    195				reg = <0x13800 0x100>, <0x13C00 0x20>;
    196				/* MPP1[19:0] */
    197				gpionb: gpio {
    198					#gpio-cells = <2>;
    199					gpio-ranges = <&pinctrl_nb 0 0 36>;
    200					gpio-controller;
    201					interrupt-controller;
    202					#interrupt-cells = <2>;
    203					interrupts =
    204					<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
    205					<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
    206					<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
    207					<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
    208					<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
    209					<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
    210					<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
    211					<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
    212					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
    213					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
    214					<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
    215					<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
    216				};
    217
    218				xtalclk: xtal-clk {
    219					compatible = "marvell,armada-3700-xtal-clock";
    220					clock-output-names = "xtal";
    221					#clock-cells = <0>;
    222				};
    223
    224				spi_quad_pins: spi-quad-pins {
    225					groups = "spi_quad";
    226					function = "spi";
    227				};
    228
    229				spi_cs1_pins: spi-cs1-pins {
    230					groups = "spi_cs1";
    231					function = "spi";
    232				};
    233
    234				i2c1_pins: i2c1-pins {
    235					groups = "i2c1";
    236					function = "i2c";
    237				};
    238
    239				i2c2_pins: i2c2-pins {
    240					groups = "i2c2";
    241					function = "i2c";
    242				};
    243
    244				uart1_pins: uart1-pins {
    245					groups = "uart1";
    246					function = "uart";
    247				};
    248
    249				uart2_pins: uart2-pins {
    250					groups = "uart2";
    251					function = "uart";
    252				};
    253
    254				mmc_pins: mmc-pins {
    255					groups = "emmc_nb";
    256					function = "emmc";
    257				};
    258			};
    259
    260			nb_pm: syscon@14000 {
    261				compatible = "marvell,armada-3700-nb-pm",
    262					     "syscon";
    263				reg = <0x14000 0x60>;
    264			};
    265
    266			comphy: phy@18300 {
    267				compatible = "marvell,comphy-a3700";
    268				reg = <0x18300 0x300>,
    269				      <0x1F000 0x400>,
    270				      <0x5C000 0x400>,
    271				      <0xe0178 0x8>;
    272				reg-names = "comphy",
    273					    "lane1_pcie_gbe",
    274					    "lane0_usb3_gbe",
    275					    "lane2_sata_usb3";
    276				#address-cells = <1>;
    277				#size-cells = <0>;
    278				clocks = <&xtalclk>;
    279				clock-names = "xtal";
    280
    281				comphy0: phy@0 {
    282					reg = <0>;
    283					#phy-cells = <1>;
    284				};
    285
    286				comphy1: phy@1 {
    287					reg = <1>;
    288					#phy-cells = <1>;
    289				};
    290
    291				comphy2: phy@2 {
    292					reg = <2>;
    293					#phy-cells = <1>;
    294				};
    295			};
    296
    297			pinctrl_sb: pinctrl@18800 {
    298				compatible = "marvell,armada3710-sb-pinctrl",
    299					     "syscon", "simple-mfd";
    300				reg = <0x18800 0x100>, <0x18C00 0x20>;
    301				/* MPP2[23:0] */
    302				gpiosb: gpio {
    303					#gpio-cells = <2>;
    304					gpio-ranges = <&pinctrl_sb 0 0 30>;
    305					gpio-controller;
    306					interrupt-controller;
    307					#interrupt-cells = <2>;
    308					interrupts =
    309					<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
    310					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
    311					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
    312					<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
    313					<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
    314				};
    315
    316				rgmii_pins: mii-pins {
    317					groups = "rgmii";
    318					function = "mii";
    319				};
    320
    321				smi_pins: smi-pins {
    322					groups = "smi";
    323					function = "smi";
    324				};
    325
    326				sdio_pins: sdio-pins {
    327					groups = "sdio_sb";
    328					function = "sdio";
    329				};
    330
    331				pcie_reset_pins: pcie-reset-pins {
    332					groups = "pcie1"; /* this actually controls "pcie1_reset" */
    333					function = "gpio";
    334				};
    335
    336				pcie_clkreq_pins: pcie-clkreq-pins {
    337					groups = "pcie1_clkreq";
    338					function = "pcie";
    339				};
    340			};
    341
    342			eth0: ethernet@30000 {
    343				   compatible = "marvell,armada-3700-neta";
    344				   reg = <0x30000 0x4000>;
    345				   interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
    346				   clocks = <&sb_periph_clk 8>;
    347				   status = "disabled";
    348			};
    349
    350			mdio: mdio@32004 {
    351				#address-cells = <1>;
    352				#size-cells = <0>;
    353				compatible = "marvell,orion-mdio";
    354				reg = <0x32004 0x4>;
    355			};
    356
    357			eth1: ethernet@40000 {
    358				compatible = "marvell,armada-3700-neta";
    359				reg = <0x40000 0x4000>;
    360				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
    361				clocks = <&sb_periph_clk 7>;
    362				status = "disabled";
    363			};
    364
    365			usb3: usb@58000 {
    366				compatible = "marvell,armada3700-xhci",
    367				"generic-xhci";
    368				reg = <0x58000 0x4000>;
    369				marvell,usb-misc-reg = <&usb32_syscon>;
    370				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
    371				clocks = <&sb_periph_clk 12>;
    372				phys = <&comphy0 0>, <&usb2_utmi_otg_phy>;
    373				phy-names = "usb3-phy", "usb2-utmi-otg-phy";
    374				status = "disabled";
    375			};
    376
    377			usb2_utmi_otg_phy: phy@5d000 {
    378				compatible = "marvell,a3700-utmi-otg-phy";
    379				reg = <0x5d000 0x800>;
    380				marvell,usb-misc-reg = <&usb32_syscon>;
    381				#phy-cells = <0>;
    382			};
    383
    384			usb32_syscon: system-controller@5d800 {
    385				compatible = "marvell,armada-3700-usb2-host-device-misc",
    386				"syscon";
    387				reg = <0x5d800 0x800>;
    388			};
    389
    390			usb2: usb@5e000 {
    391				compatible = "marvell,armada-3700-ehci";
    392				reg = <0x5e000 0x1000>;
    393				marvell,usb-misc-reg = <&usb2_syscon>;
    394				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
    395				phys = <&usb2_utmi_host_phy>;
    396				phy-names = "usb2-utmi-host-phy";
    397				status = "disabled";
    398			};
    399
    400			usb2_utmi_host_phy: phy@5f000 {
    401				compatible = "marvell,a3700-utmi-host-phy";
    402				reg = <0x5f000 0x800>;
    403				marvell,usb-misc-reg = <&usb2_syscon>;
    404				#phy-cells = <0>;
    405			};
    406
    407			usb2_syscon: system-controller@5f800 {
    408				compatible = "marvell,armada-3700-usb2-host-misc",
    409				"syscon";
    410				reg = <0x5f800 0x800>;
    411			};
    412
    413			xor@60900 {
    414				compatible = "marvell,armada-3700-xor";
    415				reg = <0x60900 0x100>,
    416				      <0x60b00 0x100>;
    417
    418				xor10 {
    419					interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
    420				};
    421				xor11 {
    422					interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
    423				};
    424			};
    425
    426			crypto: crypto@90000 {
    427				compatible = "inside-secure,safexcel-eip97ies";
    428				reg = <0x90000 0x20000>;
    429				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
    430					     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
    431					     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
    432					     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
    433					     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
    434					     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
    435				interrupt-names = "mem", "ring0", "ring1",
    436						  "ring2", "ring3", "eip";
    437				clocks = <&nb_periph_clk 15>;
    438			};
    439
    440			rwtm: mailbox@b0000 {
    441				compatible = "marvell,armada-3700-rwtm-mailbox";
    442				reg = <0xb0000 0x100>;
    443				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
    444				#mbox-cells = <1>;
    445			};
    446
    447			sdhci1: mmc@d0000 {
    448				compatible = "marvell,armada-3700-sdhci",
    449					     "marvell,sdhci-xenon";
    450				reg = <0xd0000 0x300>,
    451				      <0x1e808 0x4>;
    452				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
    453				clocks = <&nb_periph_clk 0>;
    454				clock-names = "core";
    455				status = "disabled";
    456			};
    457
    458			sdhci0: mmc@d8000 {
    459				compatible = "marvell,armada-3700-sdhci",
    460					     "marvell,sdhci-xenon";
    461				reg = <0xd8000 0x300>,
    462				      <0x17808 0x4>;
    463				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
    464				clocks = <&nb_periph_clk 0>;
    465				clock-names = "core";
    466				status = "disabled";
    467			};
    468
    469			sata: sata@e0000 {
    470				compatible = "marvell,armada-3700-ahci";
    471				reg = <0xe0000 0x178>;
    472				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
    473				clocks = <&nb_periph_clk 1>;
    474				phys = <&comphy2 0>;
    475				phy-names = "sata-phy";
    476				status = "disabled";
    477			};
    478
    479			gic: interrupt-controller@1d00000 {
    480				compatible = "arm,gic-v3";
    481				#interrupt-cells = <3>;
    482				interrupt-controller;
    483				reg = <0x1d00000 0x10000>, /* GICD */
    484				      <0x1d40000 0x40000>, /* GICR */
    485				      <0x1d80000 0x2000>,  /* GICC */
    486				      <0x1d90000 0x2000>,  /* GICH */
    487				      <0x1da0000 0x20000>; /* GICV */
    488				interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
    489			};
    490		};
    491
    492		pcie0: pcie@d0070000 {
    493			compatible = "marvell,armada-3700-pcie";
    494			device_type = "pci";
    495			status = "disabled";
    496			reg = <0 0xd0070000 0 0x20000>;
    497			#address-cells = <3>;
    498			#size-cells = <2>;
    499			bus-range = <0x00 0xff>;
    500			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
    501			#interrupt-cells = <1>;
    502			clocks = <&sb_periph_clk 13>;
    503			msi-parent = <&pcie0>;
    504			msi-controller;
    505			/*
    506			 * The 128 MiB address range [0xe8000000-0xf0000000] is
    507			 * dedicated for PCIe and can be assigned to 8 windows
    508			 * with size a power of two. Use one 64 KiB window for
    509			 * IO at the end and the remaining seven windows
    510			 * (totaling 127 MiB) for MEM.
    511			 */
    512			ranges = <0x82000000 0 0xe8000000   0 0xe8000000   0 0x07f00000   /* Port 0 MEM */
    513				  0x81000000 0 0x00000000   0 0xefff0000   0 0x00010000>; /* Port 0 IO */
    514			interrupt-map-mask = <0 0 0 7>;
    515			interrupt-map = <0 0 0 1 &pcie_intc 0>,
    516					<0 0 0 2 &pcie_intc 1>,
    517					<0 0 0 3 &pcie_intc 2>,
    518					<0 0 0 4 &pcie_intc 3>;
    519			max-link-speed = <2>;
    520			phys = <&comphy1 0>;
    521			pcie_intc: interrupt-controller {
    522				interrupt-controller;
    523				#interrupt-cells = <1>;
    524			};
    525		};
    526	};
    527
    528	firmware {
    529		armada-3700-rwtm {
    530			compatible = "marvell,armada-3700-rwtm-firmware";
    531			mboxes = <&rwtm 0>;
    532			status = "okay";
    533		};
    534	};
    535};