cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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armada-7040-mochabin.dts (8053B)


      1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
      2/*
      3 * Device Tree file for Globalscale MOCHAbin
      4 * Copyright (C) 2019 Globalscale technologies, Inc.
      5 * Copyright (C) 2021 Sartura Ltd.
      6 *
      7 */
      8
      9/dts-v1/;
     10
     11#include <dt-bindings/gpio/gpio.h>
     12#include "armada-7040.dtsi"
     13
     14/ {
     15	model = "Globalscale MOCHAbin";
     16	compatible = "globalscale,mochabin", "marvell,armada7040",
     17		     "marvell,armada-ap806-quad", "marvell,armada-ap806";
     18
     19	chosen {
     20		stdout-path = "serial0:115200n8";
     21	};
     22
     23	aliases {
     24		ethernet0 = &cp0_eth0;
     25		ethernet1 = &cp0_eth1;
     26		ethernet2 = &cp0_eth2;
     27		ethernet3 = &swport1;
     28		ethernet4 = &swport2;
     29		ethernet5 = &swport3;
     30		ethernet6 = &swport4;
     31	};
     32
     33	/* SFP+ 10G */
     34	sfp_eth0: sfp-eth0 {
     35		compatible = "sff,sfp";
     36		i2c-bus = <&cp0_i2c1>;
     37		los-gpio = <&sfp_gpio 3 GPIO_ACTIVE_HIGH>;
     38		mod-def0-gpio = <&sfp_gpio 2 GPIO_ACTIVE_LOW>;
     39		tx-disable-gpio = <&sfp_gpio 1 GPIO_ACTIVE_HIGH>;
     40		tx-fault-gpio  = <&sfp_gpio 0 GPIO_ACTIVE_HIGH>;
     41	};
     42
     43	/* SFP 1G */
     44	sfp_eth2: sfp-eth2 {
     45		compatible = "sff,sfp";
     46		i2c-bus = <&cp0_i2c0>;
     47		los-gpio = <&sfp_gpio 7 GPIO_ACTIVE_HIGH>;
     48		mod-def0-gpio = <&sfp_gpio 6 GPIO_ACTIVE_LOW>;
     49		tx-disable-gpio = <&sfp_gpio 5 GPIO_ACTIVE_HIGH>;
     50		tx-fault-gpio  = <&sfp_gpio 4 GPIO_ACTIVE_HIGH>;
     51	};
     52};
     53
     54/* microUSB UART console */
     55&uart0 {
     56	status = "okay";
     57
     58	pinctrl-0 = <&uart0_pins>;
     59	pinctrl-names = "default";
     60};
     61
     62/* eMMC */
     63&ap_sdhci0 {
     64	status = "okay";
     65
     66	bus-width = <4>;
     67	non-removable;
     68	/delete-property/ marvell,xenon-phy-slow-mode;
     69	no-1-8-v;
     70};
     71
     72&cp0_pinctrl {
     73	cp0_uart0_pins: cp0-uart0-pins {
     74		marvell,pins = "mpp6", "mpp7";
     75		marvell,function = "uart0";
     76	};
     77
     78	cp0_spi0_pins: cp0-spi0-pins {
     79		marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
     80		marvell,function = "spi0";
     81	};
     82
     83	cp0_spi1_pins: cp0-spi1-pins {
     84		marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
     85		marvell,function = "spi1";
     86	};
     87
     88	cp0_i2c0_pins: cp0-i2c0-pins {
     89		marvell,pins = "mpp37", "mpp38";
     90		marvell,function = "i2c0";
     91	};
     92
     93	cp0_i2c1_pins: cp0-i2c1-pins {
     94		marvell,pins = "mpp2", "mpp3";
     95		marvell,function = "i2c1";
     96	};
     97
     98	pca9554_int_pins: pca9554-int-pins {
     99		marvell,pins = "mpp27";
    100		marvell,function = "gpio";
    101	};
    102
    103	cp0_rgmii1_pins: cp0-rgmii1-pins {
    104		marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47", "mpp48", "mpp49",
    105			       "mpp50", "mpp51", "mpp52", "mpp53", "mpp54", "mpp55";
    106		marvell,function = "ge1";
    107	};
    108
    109	is31_sdb_pins: is31-sdb-pins {
    110		marvell,pins = "mpp30";
    111		marvell,function = "gpio";
    112	};
    113
    114	cp0_pcie_reset_pins: cp0-pcie-reset-pins {
    115		marvell,pins = "mpp9";
    116		marvell,function = "gpio";
    117	};
    118
    119	cp0_pcie_clkreq_pins: cp0-pcie-clkreq-pins {
    120		marvell,pins = "mpp5";
    121		marvell,function = "pcie1";
    122	};
    123
    124	cp0_switch_pins: cp0-switch-pins {
    125		marvell,pins = "mpp0", "mpp1";
    126		marvell,function = "gpio";
    127	};
    128
    129	cp0_phy_pins: cp0-phy-pins {
    130		marvell,pins = "mpp12";
    131		marvell,function = "gpio";
    132	};
    133};
    134
    135/* mikroBUS UART */
    136&cp0_uart0 {
    137	status = "okay";
    138
    139	pinctrl-names = "default";
    140	pinctrl-0 = <&cp0_uart0_pins>;
    141};
    142
    143/* mikroBUS SPI */
    144&cp0_spi0 {
    145	status = "okay";
    146
    147	pinctrl-names = "default";
    148	pinctrl-0 = <&cp0_spi0_pins>;
    149};
    150
    151/* SPI-NOR */
    152&cp0_spi1{
    153	status = "okay";
    154
    155	pinctrl-names = "default";
    156	pinctrl-0 = <&cp0_spi1_pins>;
    157
    158	flash@0 {
    159		#address-cells = <1>;
    160		#size-cells = <1>;
    161		compatible = "jedec,spi-nor";
    162		reg = <0>;
    163		spi-max-frequency = <20000000>;
    164
    165		partitions {
    166			compatible = "fixed-partitions";
    167			#address-cells = <1>;
    168			#size-cells = <1>;
    169
    170			partition@0 {
    171				label = "firmware";
    172				reg = <0x0 0x3e0000>;
    173				read-only;
    174			};
    175
    176			partition@3e0000 {
    177				label = "hw-info";
    178				reg = <0x3e0000 0x10000>;
    179				read-only;
    180			};
    181
    182			partition@3f0000 {
    183				label = "u-boot-env";
    184				reg = <0x3f0000 0x10000>;
    185			};
    186		};
    187	};
    188};
    189
    190/* mikroBUS, 1G SFP and GPIO expander */
    191&cp0_i2c0 {
    192	status = "okay";
    193
    194	pinctrl-names = "default";
    195	pinctrl-0 = <&cp0_i2c0_pins>;
    196	clock-frequency = <100000>;
    197
    198	sfp_gpio: pca9554@39 {
    199		compatible = "nxp,pca9554";
    200		pinctrl-names = "default";
    201		pinctrl-0 = <&pca9554_int_pins>;
    202		reg = <0x39>;
    203
    204		interrupt-parent = <&cp0_gpio1>;
    205		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
    206		interrupt-controller;
    207		#interrupt-cells = <2>;
    208
    209		gpio-controller;
    210		#gpio-cells = <2>;
    211
    212		/*
    213		 * IO0_0: SFP+_TX_FAULT
    214		 * IO0_1: SFP+_TX_DISABLE
    215		 * IO0_2: SFP+_PRSNT
    216		 * IO0_3: SFP+_LOSS
    217		 * IO0_4: SFP_TX_FAULT
    218		 * IO0_5: SFP_TX_DISABLE
    219		 * IO0_6: SFP_PRSNT
    220		 * IO0_7: SFP_LOSS
    221		 */
    222	};
    223};
    224
    225/* IS31FL3199, mini-PCIe and 10G SFP+ */
    226&cp0_i2c1 {
    227	status = "okay";
    228
    229	pinctrl-names = "default";
    230	pinctrl-0 = <&cp0_i2c1_pins>;
    231	clock-frequency = <100000>;
    232
    233	leds@64 {
    234		compatible = "issi,is31fl3199";
    235		#address-cells = <1>;
    236		#size-cells = <0>;
    237		pinctrl-names = "default";
    238		pinctrl-0 = <&is31_sdb_pins>;
    239		shutdown-gpios = <&cp0_gpio1 30 GPIO_ACTIVE_HIGH>;
    240		reg = <0x64>;
    241
    242		led1_red: led@1 {
    243			label = "red:led1";
    244			reg = <1>;
    245			led-max-microamp = <20000>;
    246		};
    247
    248		led1_green: led@2 {
    249			label = "green:led1";
    250			reg = <2>;
    251		};
    252
    253		led1_blue: led@3 {
    254			label = "blue:led1";
    255			reg = <3>;
    256		};
    257
    258		led2_red: led@4 {
    259			label = "red:led2";
    260			reg = <4>;
    261		};
    262
    263		led2_green: led@5 {
    264			label = "green:led2";
    265			reg = <5>;
    266		};
    267
    268		led2_blue: led@6 {
    269			label = "blue:led2";
    270			reg = <6>;
    271		};
    272
    273		led3_red: led@7 {
    274			label = "red:led3";
    275			reg = <7>;
    276		};
    277
    278		led3_green: led@8 {
    279			label = "green:led3";
    280			reg = <8>;
    281		};
    282
    283		led3_blue: led@9 {
    284			label = "blue:led3";
    285			reg = <9>;
    286		};
    287	};
    288};
    289
    290&cp0_mdio {
    291	status = "okay";
    292
    293	/* 88E1512 PHY */
    294	eth2phy: ethernet-phy@1 {
    295		reg = <1>;
    296		sfp = <&sfp_eth2>;
    297
    298		pinctrl-names = "default";
    299		pinctrl-0 = <&cp0_phy_pins>;
    300		reset-gpios = <&cp0_gpio1 12 GPIO_ACTIVE_LOW>;
    301	};
    302
    303	/* 88E6141 Topaz switch */
    304	switch: switch@3 {
    305		compatible = "marvell,mv88e6085";
    306		#address-cells = <1>;
    307		#size-cells = <0>;
    308		reg = <3>;
    309
    310		pinctrl-names = "default";
    311		pinctrl-0 = <&cp0_switch_pins>;
    312		reset-gpios = <&cp0_gpio1 0 GPIO_ACTIVE_LOW>;
    313
    314		interrupt-parent = <&cp0_gpio1>;
    315		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
    316
    317		ports {
    318			#address-cells = <1>;
    319			#size-cells = <0>;
    320
    321			swport1: port@1 {
    322				reg = <1>;
    323				label = "lan0";
    324				phy-handle = <&swphy1>;
    325			};
    326
    327			swport2: port@2 {
    328				reg = <2>;
    329				label = "lan1";
    330				phy-handle = <&swphy2>;
    331			};
    332
    333			swport3: port@3 {
    334				reg = <3>;
    335				label = "lan2";
    336				phy-handle = <&swphy3>;
    337			};
    338
    339			swport4: port@4 {
    340				reg = <4>;
    341				label = "lan3";
    342				phy-handle = <&swphy4>;
    343			};
    344
    345			port@5 {
    346				reg = <5>;
    347				label = "cpu";
    348				ethernet = <&cp0_eth1>;
    349				phy-mode = "2500base-x";
    350				managed = "in-band-status";
    351			};
    352		};
    353
    354		mdio {
    355			#address-cells = <1>;
    356			#size-cells = <0>;
    357
    358			swphy1: swphy1@17 {
    359				reg = <17>;
    360			};
    361
    362			swphy2: swphy2@18 {
    363				reg = <18>;
    364			};
    365
    366			swphy3: swphy3@19 {
    367				reg = <19>;
    368			};
    369
    370			swphy4: swphy4@20 {
    371				reg = <20>;
    372			};
    373		};
    374	};
    375};
    376
    377&cp0_ethernet {
    378	status = "okay";
    379};
    380
    381/* 10G SFP+ */
    382&cp0_eth0 {
    383	status = "okay";
    384
    385	phy-mode = "10gbase-r";
    386	phys = <&cp0_comphy4 0>;
    387	managed = "in-band-status";
    388	sfp = <&sfp_eth0>;
    389};
    390
    391/* Topaz switch uplink */
    392&cp0_eth1 {
    393	status = "okay";
    394
    395	phy-mode = "2500base-x";
    396	phys = <&cp0_comphy0 1>;
    397
    398	fixed-link {
    399		speed = <2500>;
    400		full-duplex;
    401	};
    402};
    403
    404/* 1G SFP or 1G RJ45 */
    405&cp0_eth2 {
    406	status = "okay";
    407
    408	pinctrl-names = "default";
    409	pinctrl-0 = <&cp0_rgmii1_pins>;
    410
    411	phy = <&eth2phy>;
    412	phy-mode = "rgmii-id";
    413};
    414
    415&cp0_utmi {
    416	status = "okay";
    417};
    418
    419/* SMSC USB5434B hub */
    420&cp0_usb3_0 {
    421	status = "okay";
    422
    423	phys = <&cp0_comphy1 0>, <&cp0_utmi0>;
    424	phy-names = "cp0-usb3h0-comphy", "utmi";
    425};
    426
    427/* miniPCI-E USB */
    428&cp0_usb3_1 {
    429	status = "okay";
    430};
    431
    432&cp0_sata0 {
    433	status = "okay";
    434
    435	/* 7 + 12 SATA connector (J24) */
    436	sata-port@0 {
    437		phys = <&cp0_comphy2 0>;
    438		phy-names = "cp0-sata0-0-phy";
    439	};
    440
    441	/* M.2-2250 B-key (J39) */
    442	sata-port@1 {
    443		phys = <&cp0_comphy3 1>;
    444		phy-names = "cp0-sata0-1-phy";
    445	};
    446};
    447
    448/* miniPCI-E (J5) */
    449&cp0_pcie2 {
    450	status = "okay";
    451
    452	pinctrl-names = "default", "clkreq";
    453	pinctrl-0 = <&cp0_pcie_reset_pins>;
    454	pinctrl-1 = <&cp0_pcie_clkreq_pins>;
    455	phys = <&cp0_comphy5 2>;
    456	phy-names = "cp0-pcie2-x1-phy";
    457	reset-gpios = <&cp0_gpio1 9 GPIO_ACTIVE_LOW>;
    458};