cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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armada-ap810-ap0-octa-core.dtsi (1313B)

      1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      2/*
      3 * Copyright (C) 2017 Marvell Technology Group Ltd.
      4 *
      5 * Device Tree file for Marvell Armada AP810 OCTA cores.
      6 */
      7
      8#include "armada-ap810-ap0.dtsi"
      9
     10/ {
     11	cpus {
     12		#address-cells = <1>;
     13		#size-cells = <0>;
     14		compatible = "marvell,armada-ap810-octa";
     15
     16		cpu0: cpu@0 {
     17			device_type = "cpu";
     18			compatible = "arm,cortex-a72";
     19			reg = <0x000>;
     20			enable-method = "psci";
     21		};
     22		cpu1: cpu@1 {
     23			device_type = "cpu";
     24			compatible = "arm,cortex-a72";
     25			reg = <0x001>;
     26			enable-method = "psci";
     27		};
     28		cpu2: cpu@100 {
     29			device_type = "cpu";
     30			compatible = "arm,cortex-a72";
     31			reg = <0x100>;
     32			enable-method = "psci";
     33		};
     34		cpu3: cpu@101 {
     35			device_type = "cpu";
     36			compatible = "arm,cortex-a72";
     37			reg = <0x101>;
     38			enable-method = "psci";
     39		};
     40		cpu4: cpu@200 {
     41			device_type = "cpu";
     42			compatible = "arm,cortex-a72";
     43			reg = <0x200>;
     44			enable-method = "psci";
     45		};
     46		cpu5: cpu@201 {
     47			device_type = "cpu";
     48			compatible = "arm,cortex-a72";
     49			reg = <0x201>;
     50			enable-method = "psci";
     51		};
     52		cpu6: cpu@300 {
     53			device_type = "cpu";
     54			compatible = "arm,cortex-a72";
     55			reg = <0x300>;
     56			enable-method = "psci";
     57		};
     58		cpu7: cpu@301 {
     59			device_type = "cpu";
     60			compatible = "arm,cortex-a72";
     61			reg = <0x301>;
     62			enable-method = "psci";
     63		};
     64	};
     65};