cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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cn9130-db-B.dts (524B)

      1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      2/*
      3 * Copyright (C) 2020 Marvell International Ltd.
      4 *
      5 * Device tree for the CN9130-DB board (setup "B").
      6 */
      7
      8#include "cn9130-db.dtsi"
      9
     10/ {
     11	model = "Marvell Armada CN9130-DB setup B";
     12};
     13
     14/* Setup B has NAND flash as a boot device, while regular setup uses SPI flash.
     15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
     16 * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
     17 */
     18
     19&cp0_nand_controller {
     20	status = "okay";
     21};
     22