cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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cn9130-db.dtsi (8179B)


      1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      2/*
      3 * Copyright (C) 2019 Marvell International Ltd.
      4 *
      5 * Device tree for the CN9130-DB board.
      6 */
      7
      8#include "cn9130.dtsi"
      9
     10#include <dt-bindings/gpio/gpio.h>
     11
     12/ {
     13	chosen {
     14		stdout-path = "serial0:115200n8";
     15	};
     16
     17	aliases {
     18		gpio1 = &cp0_gpio1;
     19		gpio2 = &cp0_gpio2;
     20		i2c0 = &cp0_i2c0;
     21		ethernet0 = &cp0_eth0;
     22		ethernet1 = &cp0_eth1;
     23		ethernet2 = &cp0_eth2;
     24		spi1 = &cp0_spi0;
     25		spi2 = &cp0_spi1;
     26	};
     27
     28	memory@0 {
     29		device_type = "memory";
     30		reg = <0x0 0x0 0x0 0x80000000>;
     31	};
     32
     33	ap0_reg_sd_vccq: ap0_sd_vccq@0 {
     34		compatible = "regulator-gpio";
     35		regulator-name = "ap0_sd_vccq";
     36		regulator-min-microvolt = <1800000>;
     37		regulator-max-microvolt = <3300000>;
     38		gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
     39		states = <1800000 0x1 3300000 0x0>;
     40	};
     41
     42	cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
     43		compatible = "regulator-fixed";
     44		regulator-name = "cp0-xhci0-vbus";
     45		regulator-min-microvolt = <5000000>;
     46		regulator-max-microvolt = <5000000>;
     47		enable-active-high;
     48		gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
     49	};
     50
     51	cp0_usb3_0_phy0: cp0_usb3_phy@0 {
     52		compatible = "usb-nop-xceiv";
     53		vcc-supply = <&cp0_reg_usb3_vbus0>;
     54	};
     55
     56	cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
     57		compatible = "regulator-fixed";
     58		regulator-name = "cp0-xhci1-vbus";
     59		regulator-min-microvolt = <5000000>;
     60		regulator-max-microvolt = <5000000>;
     61		enable-active-high;
     62		gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
     63	};
     64
     65	cp0_usb3_0_phy1: cp0_usb3_phy@1 {
     66		compatible = "usb-nop-xceiv";
     67		vcc-supply = <&cp0_reg_usb3_vbus1>;
     68	};
     69
     70	cp0_reg_sd_vccq: cp0_sd_vccq@0 {
     71		compatible = "regulator-gpio";
     72		regulator-name = "cp0_sd_vccq";
     73		regulator-min-microvolt = <1800000>;
     74		regulator-max-microvolt = <3300000>;
     75		gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
     76		states = <1800000 0x1
     77			  3300000 0x0>;
     78	};
     79
     80	cp0_reg_sd_vcc: cp0_sd_vcc@0 {
     81		compatible = "regulator-fixed";
     82		regulator-name = "cp0_sd_vcc";
     83		regulator-min-microvolt = <3300000>;
     84		regulator-max-microvolt = <3300000>;
     85		gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
     86		enable-active-high;
     87		regulator-always-on;
     88	};
     89
     90	cp0_sfp_eth0: sfp-eth@0 {
     91		compatible = "sff,sfp";
     92		i2c-bus = <&cp0_sfpp0_i2c>;
     93		los-gpio = <&cp0_module_expander1 11 GPIO_ACTIVE_HIGH>;
     94		mod-def0-gpio = <&cp0_module_expander1 10 GPIO_ACTIVE_LOW>;
     95		tx-disable-gpio = <&cp0_module_expander1 9 GPIO_ACTIVE_HIGH>;
     96		tx-fault-gpio = <&cp0_module_expander1 8 GPIO_ACTIVE_HIGH>;
     97		/*
     98		 * SFP cages are unconnected on early PCBs because of an the I2C
     99		 * lanes not being connected. Prevent the port for being
    100		 * unusable by disabling the SFP node.
    101		 */
    102		status = "disabled";
    103	};
    104};
    105
    106&uart0 {
    107	status = "okay";
    108};
    109
    110/* on-board eMMC - U9 */
    111&ap_sdhci0 {
    112	pinctrl-names = "default";
    113	bus-width = <8>;
    114	vqmmc-supply = <&ap0_reg_sd_vccq>;
    115	status = "okay";
    116};
    117
    118&cp0_crypto {
    119	status = "disabled";
    120};
    121
    122&cp0_ethernet {
    123	status = "okay";
    124};
    125
    126/* SLM-1521-V2, CON9 */
    127&cp0_eth0 {
    128	status = "okay";
    129	phy-mode = "10gbase-r";
    130	/* Generic PHY, providing serdes lanes */
    131	phys = <&cp0_comphy4 0>;
    132	managed = "in-band-status";
    133	sfp = <&cp0_sfp_eth0>;
    134};
    135
    136/* CON56 */
    137&cp0_eth1 {
    138	status = "okay";
    139	phy = <&phy0>;
    140	phy-mode = "rgmii-id";
    141};
    142
    143/* CON57 */
    144&cp0_eth2 {
    145	status = "okay";
    146	phy = <&phy1>;
    147	phy-mode = "rgmii-id";
    148};
    149
    150&cp0_gpio1 {
    151	status = "okay";
    152};
    153
    154&cp0_gpio2 {
    155	status = "okay";
    156};
    157
    158&cp0_i2c0 {
    159	status = "okay";
    160	pinctrl-names = "default";
    161	pinctrl-0 = <&cp0_i2c0_pins>;
    162	clock-frequency = <100000>;
    163
    164	/* U36 */
    165	expander0: pca953x@21 {
    166		compatible = "nxp,pca9555";
    167		pinctrl-names = "default";
    168		gpio-controller;
    169		#gpio-cells = <2>;
    170		reg = <0x21>;
    171		status = "okay";
    172	};
    173
    174	/* U42 */
    175	eeprom0: eeprom@50 {
    176		compatible = "atmel,24c64";
    177		reg = <0x50>;
    178		pagesize = <0x20>;
    179	};
    180
    181	/* U38 */
    182	eeprom1: eeprom@57 {
    183		compatible = "atmel,24c64";
    184		reg = <0x57>;
    185		pagesize = <0x20>;
    186	};
    187};
    188
    189&cp0_i2c1 {
    190	status = "okay";
    191	clock-frequency = <100000>;
    192
    193	/* SLM-1521-V2 - U3 */
    194	i2c-mux@72 { /* verify address - depends on dpr */
    195		compatible = "nxp,pca9544";
    196		#address-cells = <1>;
    197		#size-cells = <0>;
    198		reg = <0x72>;
    199		cp0_sfpp0_i2c: i2c@0 {
    200			#address-cells = <1>;
    201			#size-cells = <0>;
    202			reg = <0>;
    203		};
    204
    205		i2c@1 {
    206			#address-cells = <1>;
    207			#size-cells = <0>;
    208			reg = <1>;
    209			/* U12 */
    210			cp0_module_expander1: pca9555@21 {
    211				compatible = "nxp,pca9555";
    212				pinctrl-names = "default";
    213				gpio-controller;
    214				#gpio-cells = <2>;
    215				reg = <0x21>;
    216			};
    217
    218		};
    219	};
    220};
    221
    222&cp0_mdio {
    223	status = "okay";
    224
    225	phy0: ethernet-phy@0 {
    226		reg = <0>;
    227	};
    228
    229	phy1: ethernet-phy@1 {
    230		reg = <1>;
    231	};
    232};
    233
    234/* U54 */
    235&cp0_nand_controller {
    236	status = "disabled";
    237	pinctrl-names = "default";
    238	pinctrl-0 = <&nand_pins &nand_rb>;
    239
    240	nand@0 {
    241		reg = <0>;
    242		label = "main-storage";
    243		nand-rb = <0>;
    244		nand-ecc-mode = "hw";
    245		nand-on-flash-bbt;
    246		nand-ecc-strength = <8>;
    247		nand-ecc-step-size = <512>;
    248
    249		partitions {
    250			compatible = "fixed-partitions";
    251			#address-cells = <1>;
    252			#size-cells = <1>;
    253
    254			partition@0 {
    255				label = "U-Boot";
    256				reg = <0 0x200000>;
    257			};
    258			partition@200000 {
    259				label = "Linux";
    260				reg = <0x200000 0xe00000>;
    261			};
    262			partition@1000000 {
    263				label = "Filesystem";
    264				reg = <0x1000000 0x3f000000>;
    265			};
    266		};
    267	};
    268};
    269
    270/* SLM-1521-V2, CON6 */
    271&cp0_pcie0 {
    272	status = "okay";
    273	num-lanes = <4>;
    274	num-viewport = <8>;
    275	/* Generic PHY, providing serdes lanes */
    276	phys = <&cp0_comphy0 0
    277		&cp0_comphy1 0
    278		&cp0_comphy2 0
    279		&cp0_comphy3 0>;
    280};
    281
    282&cp0_sata0 {
    283	status = "okay";
    284
    285	/* SLM-1521-V2, CON2 */
    286	sata-port@1 {
    287		status = "okay";
    288		/* Generic PHY, providing serdes lanes */
    289		phys = <&cp0_comphy5 1>;
    290	};
    291};
    292
    293/* CON 28 */
    294&cp0_sdhci0 {
    295	status = "okay";
    296	pinctrl-names = "default";
    297	pinctrl-0 = <&cp0_sdhci_pins
    298		     &cp0_sdhci_cd_pins>;
    299	bus-width = <4>;
    300	cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
    301	no-1-8-v;
    302	vqmmc-supply = <&cp0_reg_sd_vccq>;
    303	vmmc-supply = <&cp0_reg_sd_vcc>;
    304};
    305
    306/* U55 */
    307&cp0_spi1 {
    308	status = "disabled";
    309	pinctrl-names = "default";
    310	pinctrl-0 = <&cp0_spi0_pins>;
    311	reg = <0x700680 0x50>;
    312
    313	flash@0 {
    314		#address-cells = <0x1>;
    315		#size-cells = <0x1>;
    316		compatible = "jedec,spi-nor";
    317		reg = <0x0>;
    318		/* On-board MUX does not allow higher frequencies */
    319		spi-max-frequency = <40000000>;
    320
    321		partitions {
    322			compatible = "fixed-partitions";
    323			#address-cells = <1>;
    324			#size-cells = <1>;
    325
    326			partition@0 {
    327				label = "U-Boot-0";
    328				reg = <0x0 0x200000>;
    329			};
    330
    331			partition@400000 {
    332				label = "Filesystem-0";
    333				reg = <0x200000 0xe00000>;
    334			};
    335		};
    336	};
    337};
    338
    339&cp0_syscon0 {
    340	cp0_pinctrl: pinctrl {
    341		compatible = "marvell,cp115-standalone-pinctrl";
    342
    343		cp0_i2c0_pins: cp0-i2c-pins-0 {
    344			marvell,pins = "mpp37", "mpp38";
    345			marvell,function = "i2c0";
    346		};
    347		cp0_i2c1_pins: cp0-i2c-pins-1 {
    348			marvell,pins = "mpp35", "mpp36";
    349			marvell,function = "i2c1";
    350		};
    351		cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
    352			marvell,pins = "mpp0", "mpp1", "mpp2",
    353				       "mpp3", "mpp4", "mpp5",
    354				       "mpp6", "mpp7", "mpp8",
    355				       "mpp9", "mpp10", "mpp11";
    356			marvell,function = "ge0";
    357		};
    358		cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
    359			marvell,pins = "mpp44", "mpp45", "mpp46",
    360				       "mpp47", "mpp48", "mpp49",
    361				       "mpp50", "mpp51", "mpp52",
    362				       "mpp53", "mpp54", "mpp55";
    363			marvell,function = "ge1";
    364		};
    365		cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
    366			marvell,pins = "mpp43";
    367			marvell,function = "gpio";
    368		};
    369		cp0_sdhci_pins: cp0-sdhi-pins-0 {
    370			marvell,pins = "mpp56", "mpp57", "mpp58",
    371				       "mpp59", "mpp60", "mpp61";
    372			marvell,function = "sdio";
    373		};
    374		cp0_spi0_pins: cp0-spi-pins-0 {
    375			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
    376			marvell,function = "spi1";
    377		};
    378		nand_pins: nand-pins {
    379			marvell,pins = "mpp15", "mpp16", "mpp17", "mpp18",
    380				       "mpp19", "mpp20", "mpp21", "mpp22",
    381				       "mpp23", "mpp24", "mpp25", "mpp26",
    382				       "mpp27";
    383			marvell,function = "dev";
    384		};
    385		nand_rb: nand-rb {
    386			marvell,pins = "mpp13";
    387			marvell,function = "nf";
    388		};
    389	};
    390};
    391
    392&cp0_utmi {
    393	status = "okay";
    394};
    395
    396&cp0_usb3_0 {
    397	status = "okay";
    398	usb-phy = <&cp0_usb3_0_phy0>;
    399	phys = <&cp0_utmi0>;
    400	phy-names = "utmi";
    401	dr_mode = "host";
    402};
    403
    404&cp0_usb3_1 {
    405	status = "okay";
    406	usb-phy = <&cp0_usb3_0_phy1>;
    407	phys =  <&cp0_utmi1>;
    408	phy-names = "utmi";
    409	dr_mode = "host";
    410};