cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mt6797.dtsi (11384B)


      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * Copyright (c) 2017 MediaTek Inc.
      4 * Author: Mars.C <mars.cheng@mediatek.com>
      5 */
      6
      7#include <dt-bindings/clock/mt6797-clk.h>
      8#include <dt-bindings/interrupt-controller/irq.h>
      9#include <dt-bindings/interrupt-controller/arm-gic.h>
     10#include <dt-bindings/pinctrl/mt6797-pinfunc.h>
     11
     12/ {
     13	compatible = "mediatek,mt6797";
     14	interrupt-parent = <&sysirq>;
     15	#address-cells = <2>;
     16	#size-cells = <2>;
     17
     18	psci {
     19		compatible = "arm,psci-0.2";
     20		method = "smc";
     21	};
     22
     23	cpus {
     24		#address-cells = <1>;
     25		#size-cells = <0>;
     26
     27		cpu0: cpu@0 {
     28			device_type = "cpu";
     29			compatible = "arm,cortex-a53";
     30			enable-method = "psci";
     31			reg = <0x000>;
     32		};
     33
     34		cpu1: cpu@1 {
     35			device_type = "cpu";
     36			compatible = "arm,cortex-a53";
     37			enable-method = "psci";
     38			reg = <0x001>;
     39		};
     40
     41		cpu2: cpu@2 {
     42			device_type = "cpu";
     43			compatible = "arm,cortex-a53";
     44			enable-method = "psci";
     45			reg = <0x002>;
     46		};
     47
     48		cpu3: cpu@3 {
     49			device_type = "cpu";
     50			compatible = "arm,cortex-a53";
     51			enable-method = "psci";
     52			reg = <0x003>;
     53		};
     54
     55		cpu4: cpu@100 {
     56			device_type = "cpu";
     57			compatible = "arm,cortex-a53";
     58			enable-method = "psci";
     59			reg = <0x100>;
     60		};
     61
     62		cpu5: cpu@101 {
     63			device_type = "cpu";
     64			compatible = "arm,cortex-a53";
     65			enable-method = "psci";
     66			reg = <0x101>;
     67		};
     68
     69		cpu6: cpu@102 {
     70			device_type = "cpu";
     71			compatible = "arm,cortex-a53";
     72			enable-method = "psci";
     73			reg = <0x102>;
     74		};
     75
     76		cpu7: cpu@103 {
     77			device_type = "cpu";
     78			compatible = "arm,cortex-a53";
     79			enable-method = "psci";
     80			reg = <0x103>;
     81		};
     82
     83		cpu8: cpu@200 {
     84			device_type = "cpu";
     85			compatible = "arm,cortex-a72";
     86			enable-method = "psci";
     87			reg = <0x200>;
     88		};
     89
     90		cpu9: cpu@201 {
     91			device_type = "cpu";
     92			compatible = "arm,cortex-a72";
     93			enable-method = "psci";
     94			reg = <0x201>;
     95		};
     96	};
     97
     98	clk26m: oscillator@0 {
     99		compatible = "fixed-clock";
    100		#clock-cells = <0>;
    101		clock-frequency = <26000000>;
    102		clock-output-names = "clk26m";
    103	};
    104
    105	timer {
    106		compatible = "arm,armv8-timer";
    107		interrupt-parent = <&gic>;
    108		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
    109			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
    110			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
    111			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
    112	};
    113
    114	topckgen: topckgen@10000000 {
    115		compatible = "mediatek,mt6797-topckgen";
    116		reg = <0 0x10000000 0 0x1000>;
    117		#clock-cells = <1>;
    118	};
    119
    120	infrasys: infracfg_ao@10001000 {
    121		compatible = "mediatek,mt6797-infracfg", "syscon";
    122		reg = <0 0x10001000 0 0x1000>;
    123		#clock-cells = <1>;
    124	};
    125
    126	pio: pinctrl@10005000 {
    127		compatible = "mediatek,mt6797-pinctrl";
    128		reg = <0 0x10005000 0 0x1000>,
    129		      <0 0x10002000 0 0x400>,
    130		      <0 0x10002400 0 0x400>,
    131		      <0 0x10002800 0 0x400>,
    132		      <0 0x10002C00 0 0x400>;
    133		reg-names = "gpio", "iocfgl", "iocfgb",
    134			    "iocfgr", "iocfgt";
    135		gpio-controller;
    136		#gpio-cells = <2>;
    137
    138		uart0_pins_a: uart0 {
    139			pins0 {
    140				pinmux = <MT6797_GPIO234__FUNC_UTXD0>,
    141					 <MT6797_GPIO235__FUNC_URXD0>;
    142			};
    143		};
    144
    145		uart1_pins_a: uart1 {
    146			pins1 {
    147				pinmux = <MT6797_GPIO232__FUNC_URXD1>,
    148					 <MT6797_GPIO233__FUNC_UTXD1>;
    149			};
    150		};
    151
    152		i2c0_pins_a: i2c0 {
    153			pins0 {
    154				pinmux = <MT6797_GPIO37__FUNC_SCL0_0>,
    155					 <MT6797_GPIO38__FUNC_SDA0_0>;
    156			};
    157		};
    158
    159		i2c1_pins_a: i2c1 {
    160			pins1 {
    161				pinmux = <MT6797_GPIO55__FUNC_SCL1_0>,
    162					 <MT6797_GPIO56__FUNC_SDA1_0>;
    163			};
    164		};
    165
    166		i2c2_pins_a: i2c2 {
    167			pins2 {
    168				pinmux = <MT6797_GPIO96__FUNC_SCL2_0>,
    169					 <MT6797_GPIO95__FUNC_SDA2_0>;
    170			};
    171		};
    172
    173		i2c3_pins_a: i2c3 {
    174			pins3 {
    175				pinmux = <MT6797_GPIO75__FUNC_SDA3_0>,
    176					 <MT6797_GPIO74__FUNC_SCL3_0>;
    177			};
    178		};
    179
    180		i2c4_pins_a: i2c4 {
    181			pins4 {
    182				pinmux = <MT6797_GPIO238__FUNC_SDA4_0>,
    183					 <MT6797_GPIO239__FUNC_SCL4_0>;
    184			};
    185		};
    186
    187		i2c5_pins_a: i2c5 {
    188			pins5 {
    189				pinmux = <MT6797_GPIO240__FUNC_SDA5_0>,
    190					 <MT6797_GPIO241__FUNC_SCL5_0>;
    191			};
    192		};
    193
    194		i2c6_pins_a: i2c6 {
    195			pins6 {
    196				pinmux = <MT6797_GPIO152__FUNC_SDA6_0>,
    197					 <MT6797_GPIO151__FUNC_SCL6_0>;
    198			};
    199		};
    200
    201		i2c7_pins_a: i2c7 {
    202			pins7 {
    203				pinmux = <MT6797_GPIO154__FUNC_SDA7_0>,
    204					 <MT6797_GPIO153__FUNC_SCL7_0>;
    205			};
    206		};
    207	};
    208
    209	scpsys: power-controller@10006000 {
    210		compatible = "mediatek,mt6797-scpsys";
    211		#power-domain-cells = <1>;
    212		reg = <0 0x10006000 0 0x1000>;
    213		clocks = <&topckgen CLK_TOP_MUX_MFG>,
    214			 <&topckgen CLK_TOP_MUX_MM>,
    215			 <&topckgen CLK_TOP_MUX_VDEC>;
    216		clock-names = "mfg", "mm", "vdec";
    217		infracfg = <&infrasys>;
    218	};
    219
    220	watchdog: watchdog@10007000 {
    221		compatible = "mediatek,mt6797-wdt", "mediatek,mt6589-wdt";
    222		reg = <0 0x10007000 0 0x100>;
    223	};
    224
    225	apmixedsys: apmixed@1000c000 {
    226		compatible = "mediatek,mt6797-apmixedsys";
    227		reg = <0 0x1000c000 0 0x1000>;
    228		#clock-cells = <1>;
    229	};
    230
    231	sysirq: intpol-controller@10200620 {
    232		compatible = "mediatek,mt6797-sysirq",
    233			     "mediatek,mt6577-sysirq";
    234		interrupt-controller;
    235		#interrupt-cells = <3>;
    236		interrupt-parent = <&gic>;
    237		reg = <0 0x10220620 0 0x20>,
    238		      <0 0x10220690 0 0x10>;
    239	};
    240
    241	uart0: serial@11002000 {
    242		compatible = "mediatek,mt6797-uart",
    243			     "mediatek,mt6577-uart";
    244		reg = <0 0x11002000 0 0x400>;
    245		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
    246		clocks = <&infrasys CLK_INFRA_UART0>,
    247			 <&infrasys CLK_INFRA_AP_DMA>;
    248		clock-names = "baud", "bus";
    249		status = "disabled";
    250	};
    251
    252	uart1: serial@11003000 {
    253		compatible = "mediatek,mt6797-uart",
    254			     "mediatek,mt6577-uart";
    255		reg = <0 0x11003000 0 0x400>;
    256		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
    257		clocks = <&infrasys CLK_INFRA_UART1>,
    258			 <&infrasys CLK_INFRA_AP_DMA>;
    259		clock-names = "baud", "bus";
    260		status = "disabled";
    261	};
    262
    263	uart2: serial@11004000 {
    264		compatible = "mediatek,mt6797-uart",
    265			     "mediatek,mt6577-uart";
    266		reg = <0 0x11004000 0 0x400>;
    267		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
    268		clocks = <&infrasys CLK_INFRA_UART2>,
    269			 <&infrasys CLK_INFRA_AP_DMA>;
    270		clock-names = "baud", "bus";
    271		status = "disabled";
    272	};
    273
    274	uart3: serial@11005000 {
    275		compatible = "mediatek,mt6797-uart",
    276			     "mediatek,mt6577-uart";
    277		reg = <0 0x11005000 0 0x400>;
    278		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
    279		clocks = <&infrasys CLK_INFRA_UART3>,
    280			 <&infrasys CLK_INFRA_AP_DMA>;
    281		clock-names = "baud", "bus";
    282		status = "disabled";
    283	};
    284
    285	i2c0: i2c@11007000 {
    286		compatible = "mediatek,mt6797-i2c",
    287			     "mediatek,mt6577-i2c";
    288		id = <0>;
    289		reg = <0 0x11007000 0 0x1000>,
    290		      <0 0x11000100 0 0x80>;
    291		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
    292		clocks = <&infrasys CLK_INFRA_I2C0>,
    293			 <&infrasys CLK_INFRA_AP_DMA>;
    294		clock-names = "main", "dma";
    295		clock-div = <10>;
    296		#address-cells = <1>;
    297		#size-cells = <0>;
    298		status = "disabled";
    299	};
    300
    301	i2c1: i2c@11008000 {
    302		compatible = "mediatek,mt6797-i2c",
    303			     "mediatek,mt6577-i2c";
    304		id = <1>;
    305		reg = <0 0x11008000 0 0x1000>,
    306		      <0 0x11000180 0 0x80>;
    307		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
    308		clocks = <&infrasys CLK_INFRA_I2C1>,
    309			 <&infrasys CLK_INFRA_AP_DMA>;
    310		clock-names = "main", "dma";
    311		clock-div = <10>;
    312		#address-cells = <1>;
    313		#size-cells = <0>;
    314		status = "disabled";
    315	};
    316
    317	i2c8: i2c@11009000 {
    318		compatible = "mediatek,mt6797-i2c",
    319			     "mediatek,mt6577-i2c";
    320		id = <8>;
    321		reg = <0 0x11009000 0 0x1000>,
    322		      <0 0x11000200 0 0x80>;
    323		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
    324		clocks = <&infrasys CLK_INFRA_I2C2>,
    325			 <&infrasys CLK_INFRA_AP_DMA>,
    326			 <&infrasys CLK_INFRA_I2C2_ARB>;
    327		clock-names = "main", "dma", "arb";
    328		clock-div = <10>;
    329		#address-cells = <1>;
    330		#size-cells = <0>;
    331		status = "disabled";
    332	};
    333
    334	i2c9: i2c@1100d000 {
    335		compatible = "mediatek,mt6797-i2c",
    336			     "mediatek,mt6577-i2c";
    337		id = <9>;
    338		reg = <0 0x1100d000 0 0x1000>,
    339		      <0 0x11000280 0 0x80>;
    340		interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
    341		clocks = <&infrasys CLK_INFRA_I2C3>,
    342			 <&infrasys CLK_INFRA_AP_DMA>,
    343			 <&infrasys CLK_INFRA_I2C3_ARB>;
    344		clock-names = "main", "dma", "arb";
    345		clock-div = <10>;
    346		#address-cells = <1>;
    347		#size-cells = <0>;
    348		status = "disabled";
    349	};
    350
    351	i2c6: i2c@1100e000 {
    352		compatible = "mediatek,mt6797-i2c",
    353			     "mediatek,mt6577-i2c";
    354		id = <6>;
    355		reg = <0 0x1100e000 0 0x1000>,
    356		      <0 0x11000500 0 0x80>;
    357		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
    358		clocks = <&infrasys CLK_INFRA_I2C_APPM>,
    359			 <&infrasys CLK_INFRA_AP_DMA>;
    360		clock-names = "main", "dma";
    361		clock-div = <10>;
    362		#address-cells = <1>;
    363		#size-cells = <0>;
    364		status = "disabled";
    365	};
    366
    367	i2c7: i2c@11010000 {
    368		compatible = "mediatek,mt6797-i2c",
    369			     "mediatek,mt6577-i2c";
    370		id = <7>;
    371		reg = <0 0x11010000 0 0x1000>,
    372		      <0 0x11000580 0 0x80>;
    373		interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
    374		clocks = <&infrasys CLK_INFRA_I2C_GPUPM>,
    375			 <&infrasys CLK_INFRA_AP_DMA>;
    376		clock-names = "main", "dma";
    377		clock-div = <10>;
    378		#address-cells = <1>;
    379		#size-cells = <0>;
    380		status = "disabled";
    381	};
    382
    383	i2c4: i2c@11011000 {
    384		compatible = "mediatek,mt6797-i2c",
    385			     "mediatek,mt6577-i2c";
    386		id = <4>;
    387		reg = <0 0x11011000 0 0x1000>,
    388		      <0 0x11000300 0 0x80>;
    389		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
    390		clocks = <&infrasys CLK_INFRA_I2C4>,
    391			 <&infrasys CLK_INFRA_AP_DMA>;
    392		clock-names = "main", "dma";
    393		clock-div = <10>;
    394		#address-cells = <1>;
    395		#size-cells = <0>;
    396		status = "disabled";
    397	};
    398
    399	i2c2: i2c@11013000 {
    400		compatible = "mediatek,mt6797-i2c",
    401			     "mediatek,mt6577-i2c";
    402		id = <2>;
    403		reg = <0 0x11013000 0 0x1000>,
    404		      <0 0x11000400 0 0x80>;
    405		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
    406		clocks = <&infrasys CLK_INFRA_I2C2_IMM>,
    407			 <&infrasys CLK_INFRA_AP_DMA>,
    408			 <&infrasys CLK_INFRA_I2C2_ARB>;
    409		clock-names = "main", "dma", "arb";
    410		clock-div = <10>;
    411		#address-cells = <1>;
    412		#size-cells = <0>;
    413		status = "disabled";
    414	};
    415
    416	i2c3: i2c@11014000 {
    417		compatible = "mediatek,mt6797-i2c",
    418			     "mediatek,mt6577-i2c";
    419		id = <3>;
    420		reg = <0 0x11014000 0 0x1000>,
    421		      <0 0x11000480 0 0x80>;
    422		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
    423		clocks = <&infrasys CLK_INFRA_I2C3_IMM>,
    424			 <&infrasys CLK_INFRA_AP_DMA>,
    425			 <&infrasys CLK_INFRA_I2C3_ARB>;
    426		clock-names = "main", "dma", "arb";
    427		clock-div = <10>;
    428		#address-cells = <1>;
    429		#size-cells = <0>;
    430		status = "disabled";
    431	};
    432
    433	i2c5: i2c@1101c000 {
    434		compatible = "mediatek,mt6797-i2c",
    435			     "mediatek,mt6577-i2c";
    436		id = <5>;
    437		reg = <0 0x1101c000 0 0x1000>,
    438		      <0 0x11000380 0 0x80>;
    439		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
    440		clocks = <&infrasys CLK_INFRA_I2C5>,
    441			 <&infrasys CLK_INFRA_AP_DMA>;
    442		clock-names = "main", "dma";
    443		clock-div = <10>;
    444		#address-cells = <1>;
    445		#size-cells = <0>;
    446		status = "disabled";
    447	};
    448
    449	mmsys: syscon@14000000 {
    450		compatible = "mediatek,mt6797-mmsys", "syscon";
    451		reg = <0 0x14000000 0 0x1000>;
    452		#clock-cells = <1>;
    453	};
    454
    455	imgsys: imgsys_config@15000000  {
    456		compatible = "mediatek,mt6797-imgsys", "syscon";
    457		reg = <0 0x15000000 0 0x1000>;
    458		#clock-cells = <1>;
    459	};
    460
    461	vdecsys: vdec_gcon@16000000 {
    462		compatible = "mediatek,mt6797-vdecsys", "syscon";
    463		reg = <0 0x16000000 0 0x10000>;
    464		#clock-cells = <1>;
    465	};
    466
    467	vencsys: venc_gcon@17000000 {
    468		compatible = "mediatek,mt6797-vencsys", "syscon";
    469		reg = <0 0x17000000 0 0x1000>;
    470		#clock-cells = <1>;
    471	};
    472
    473	gic: interrupt-controller@19000000 {
    474		compatible = "arm,gic-v3";
    475		#interrupt-cells = <3>;
    476		interrupt-parent = <&gic>;
    477		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
    478		interrupt-controller;
    479		reg = <0 0x19000000 0 0x10000>,    /* GICD */
    480		      <0 0x19200000 0 0x200000>,   /* GICR */
    481		      <0 0x10240000 0 0x2000>;     /* GICC */
    482	};
    483};