cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mt8183-evb.dts (8493B)

      1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
      2/*
      3 * Copyright (c) 2018 MediaTek Inc.
      4 * Author: Ben Ho <ben.ho@mediatek.com>
      5 *	   Erin Lo <erin.lo@mediatek.com>
      6 */
      7
      8/dts-v1/;
      9#include "mt8183.dtsi"
     10#include "mt6358.dtsi"
     11
     12/ {
     13	model = "MediaTek MT8183 evaluation board";
     14	compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
     15
     16	aliases {
     17		serial0 = &uart0;
     18	};
     19
     20	memory@40000000 {
     21		device_type = "memory";
     22		reg = <0 0x40000000 0 0x80000000>;
     23	};
     24
     25	chosen {
     26		stdout-path = "serial0:921600n8";
     27	};
     28
     29	reserved-memory {
     30		#address-cells = <2>;
     31		#size-cells = <2>;
     32		ranges;
     33		scp_mem_reserved: scp_mem_region {
     34			compatible = "shared-dma-pool";
     35			reg = <0 0x50000000 0 0x2900000>;
     36			no-map;
     37		};
     38	};
     39
     40	ntc@0 {
     41		compatible = "murata,ncp03wf104";
     42		pullup-uv = <1800000>;
     43		pullup-ohm = <390000>;
     44		pulldown-ohm = <0>;
     45		io-channels = <&auxadc 0>;
     46	};
     47};
     48
     49&auxadc {
     50	status = "okay";
     51};
     52
     53&gpu {
     54	mali-supply = <&mt6358_vgpu_reg>;
     55	sram-supply = <&mt6358_vsram_gpu_reg>;
     56};
     57
     58&i2c0 {
     59	pinctrl-names = "default";
     60	pinctrl-0 = <&i2c_pins_0>;
     61	status = "okay";
     62	clock-frequency = <100000>;
     63};
     64
     65&i2c1 {
     66	pinctrl-names = "default";
     67	pinctrl-0 = <&i2c_pins_1>;
     68	status = "okay";
     69	clock-frequency = <100000>;
     70};
     71
     72&i2c2 {
     73	pinctrl-names = "default";
     74	pinctrl-0 = <&i2c_pins_2>;
     75	status = "okay";
     76	clock-frequency = <100000>;
     77};
     78
     79&i2c3 {
     80	pinctrl-names = "default";
     81	pinctrl-0 = <&i2c_pins_3>;
     82	status = "okay";
     83	clock-frequency = <100000>;
     84};
     85
     86&i2c4 {
     87	pinctrl-names = "default";
     88	pinctrl-0 = <&i2c_pins_4>;
     89	status = "okay";
     90	clock-frequency = <1000000>;
     91};
     92
     93&i2c5 {
     94	pinctrl-names = "default";
     95	pinctrl-0 = <&i2c_pins_5>;
     96	status = "okay";
     97	clock-frequency = <1000000>;
     98};
     99
    100&mmc0 {
    101	status = "okay";
    102	pinctrl-names = "default", "state_uhs";
    103	pinctrl-0 = <&mmc0_pins_default>;
    104	pinctrl-1 = <&mmc0_pins_uhs>;
    105	bus-width = <8>;
    106	max-frequency = <200000000>;
    107	cap-mmc-highspeed;
    108	mmc-hs200-1_8v;
    109	mmc-hs400-1_8v;
    110	cap-mmc-hw-reset;
    111	no-sdio;
    112	no-sd;
    113	hs400-ds-delay = <0x12814>;
    114	vmmc-supply = <&mt6358_vemc_reg>;
    115	vqmmc-supply = <&mt6358_vio18_reg>;
    116	assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>;
    117	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>;
    118	non-removable;
    119};
    120
    121&mmc1 {
    122	status = "okay";
    123	pinctrl-names = "default", "state_uhs";
    124	pinctrl-0 = <&mmc1_pins_default>;
    125	pinctrl-1 = <&mmc1_pins_uhs>;
    126	bus-width = <4>;
    127	max-frequency = <200000000>;
    128	cap-sd-highspeed;
    129	sd-uhs-sdr50;
    130	sd-uhs-sdr104;
    131	cap-sdio-irq;
    132	no-mmc;
    133	no-sd;
    134	vmmc-supply = <&mt6358_vmch_reg>;
    135	vqmmc-supply = <&mt6358_vmc_reg>;
    136	keep-power-in-suspend;
    137	enable-sdio-wakeup;
    138	non-removable;
    139};
    140
    141&pio {
    142	i2c_pins_0: i2c0{
    143		pins_i2c{
    144			pinmux = <PINMUX_GPIO82__FUNC_SDA0>,
    145				 <PINMUX_GPIO83__FUNC_SCL0>;
    146			mediatek,pull-up-adv = <3>;
    147			mediatek,drive-strength-adv = <00>;
    148		};
    149	};
    150
    151	i2c_pins_1: i2c1{
    152		pins_i2c{
    153			pinmux = <PINMUX_GPIO81__FUNC_SDA1>,
    154				 <PINMUX_GPIO84__FUNC_SCL1>;
    155			mediatek,pull-up-adv = <3>;
    156			mediatek,drive-strength-adv = <00>;
    157		};
    158	};
    159
    160	i2c_pins_2: i2c2{
    161		pins_i2c{
    162			pinmux = <PINMUX_GPIO103__FUNC_SCL2>,
    163				 <PINMUX_GPIO104__FUNC_SDA2>;
    164			mediatek,pull-up-adv = <3>;
    165			mediatek,drive-strength-adv = <00>;
    166		};
    167	};
    168
    169	i2c_pins_3: i2c3{
    170		pins_i2c{
    171			pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
    172				 <PINMUX_GPIO51__FUNC_SDA3>;
    173			mediatek,pull-up-adv = <3>;
    174			mediatek,drive-strength-adv = <00>;
    175		};
    176	};
    177
    178	i2c_pins_4: i2c4{
    179		pins_i2c{
    180			pinmux = <PINMUX_GPIO105__FUNC_SCL4>,
    181				 <PINMUX_GPIO106__FUNC_SDA4>;
    182			mediatek,pull-up-adv = <3>;
    183			mediatek,drive-strength-adv = <00>;
    184		};
    185	};
    186
    187	i2c_pins_5: i2c5{
    188		pins_i2c{
    189			pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
    190				 <PINMUX_GPIO49__FUNC_SDA5>;
    191			mediatek,pull-up-adv = <3>;
    192			mediatek,drive-strength-adv = <00>;
    193		};
    194	};
    195
    196	spi_pins_0: spi0{
    197		pins_spi{
    198			pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>,
    199				 <PINMUX_GPIO86__FUNC_SPI0_CSB>,
    200				 <PINMUX_GPIO87__FUNC_SPI0_MO>,
    201				 <PINMUX_GPIO88__FUNC_SPI0_CLK>;
    202			bias-disable;
    203		};
    204	};
    205
    206	mmc0_pins_default: mmc0default {
    207		pins_cmd_dat {
    208			pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
    209				 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
    210				 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
    211				 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
    212				 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
    213				 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
    214				 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
    215				 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
    216				 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
    217			input-enable;
    218			bias-pull-up;
    219		};
    220
    221		pins_clk {
    222			pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
    223			bias-pull-down;
    224		};
    225
    226		pins_rst {
    227			pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
    228			bias-pull-up;
    229		};
    230	};
    231
    232	mmc0_pins_uhs: mmc0 {
    233		pins_cmd_dat {
    234			pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>,
    235				 <PINMUX_GPIO128__FUNC_MSDC0_DAT1>,
    236				 <PINMUX_GPIO125__FUNC_MSDC0_DAT2>,
    237				 <PINMUX_GPIO132__FUNC_MSDC0_DAT3>,
    238				 <PINMUX_GPIO126__FUNC_MSDC0_DAT4>,
    239				 <PINMUX_GPIO129__FUNC_MSDC0_DAT5>,
    240				 <PINMUX_GPIO127__FUNC_MSDC0_DAT6>,
    241				 <PINMUX_GPIO130__FUNC_MSDC0_DAT7>,
    242				 <PINMUX_GPIO122__FUNC_MSDC0_CMD>;
    243			input-enable;
    244			drive-strength = <MTK_DRIVE_10mA>;
    245			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
    246		};
    247
    248		pins_clk {
    249			pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>;
    250			drive-strength = <MTK_DRIVE_10mA>;
    251			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
    252		};
    253
    254		pins_ds {
    255			pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>;
    256			drive-strength = <MTK_DRIVE_10mA>;
    257			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
    258		};
    259
    260		pins_rst {
    261			pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>;
    262			drive-strength = <MTK_DRIVE_10mA>;
    263			bias-pull-up;
    264		};
    265	};
    266
    267	mmc1_pins_default: mmc1default {
    268		pins_cmd_dat {
    269			pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
    270				   <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
    271				   <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
    272				   <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
    273				   <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
    274			input-enable;
    275			bias-pull-up;
    276		};
    277
    278		pins_clk {
    279			pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
    280			input-enable;
    281			bias-pull-down;
    282		};
    283
    284		pins_pmu {
    285			pinmux = <PINMUX_GPIO178__FUNC_GPIO178>,
    286				   <PINMUX_GPIO166__FUNC_GPIO166>;
    287			output-high;
    288		};
    289	};
    290
    291	mmc1_pins_uhs: mmc1 {
    292		pins_cmd_dat {
    293			pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>,
    294				   <PINMUX_GPIO32__FUNC_MSDC1_DAT0>,
    295				   <PINMUX_GPIO34__FUNC_MSDC1_DAT1>,
    296				   <PINMUX_GPIO33__FUNC_MSDC1_DAT2>,
    297				   <PINMUX_GPIO30__FUNC_MSDC1_DAT3>;
    298			drive-strength = <MTK_DRIVE_6mA>;
    299			input-enable;
    300			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
    301		};
    302
    303		pins_clk {
    304			pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>;
    305			drive-strength = <MTK_DRIVE_6mA>;
    306			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
    307			input-enable;
    308		};
    309	};
    310
    311	spi_pins_1: spi1{
    312		pins_spi{
    313			pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>,
    314				 <PINMUX_GPIO162__FUNC_SPI1_A_CSB>,
    315				 <PINMUX_GPIO163__FUNC_SPI1_A_MO>,
    316				 <PINMUX_GPIO164__FUNC_SPI1_A_CLK>;
    317			bias-disable;
    318		};
    319	};
    320
    321	spi_pins_2: spi2{
    322		pins_spi{
    323			pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>,
    324				 <PINMUX_GPIO1__FUNC_SPI2_MO>,
    325				 <PINMUX_GPIO2__FUNC_SPI2_CLK>,
    326				 <PINMUX_GPIO94__FUNC_SPI2_MI>;
    327			bias-disable;
    328		};
    329	};
    330
    331	spi_pins_3: spi3{
    332		pins_spi{
    333			pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>,
    334				 <PINMUX_GPIO22__FUNC_SPI3_CSB>,
    335				 <PINMUX_GPIO23__FUNC_SPI3_MO>,
    336				 <PINMUX_GPIO24__FUNC_SPI3_CLK>;
    337			bias-disable;
    338		};
    339	};
    340
    341	spi_pins_4: spi4{
    342		pins_spi{
    343			pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>,
    344				 <PINMUX_GPIO18__FUNC_SPI4_CSB>,
    345				 <PINMUX_GPIO19__FUNC_SPI4_MO>,
    346				 <PINMUX_GPIO20__FUNC_SPI4_CLK>;
    347			bias-disable;
    348		};
    349	};
    350
    351	spi_pins_5: spi5{
    352		pins_spi{
    353			pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>,
    354				 <PINMUX_GPIO14__FUNC_SPI5_CSB>,
    355				 <PINMUX_GPIO15__FUNC_SPI5_MO>,
    356				 <PINMUX_GPIO16__FUNC_SPI5_CLK>;
    357			bias-disable;
    358		};
    359	};
    360
    361	pwm_pins_1: pwm1 {
    362		pins_pwm {
    363			pinmux = <PINMUX_GPIO90__FUNC_PWM_A>;
    364		};
    365	};
    366};
    367
    368&mfg {
    369	domain-supply = <&mt6358_vgpu_reg>;
    370};
    371
    372&spi0 {
    373	pinctrl-names = "default";
    374	pinctrl-0 = <&spi_pins_0>;
    375	mediatek,pad-select = <0>;
    376	status = "okay";
    377};
    378
    379&spi1 {
    380	pinctrl-names = "default";
    381	pinctrl-0 = <&spi_pins_1>;
    382	mediatek,pad-select = <0>;
    383	status = "okay";
    384};
    385
    386&spi2 {
    387	pinctrl-names = "default";
    388	pinctrl-0 = <&spi_pins_2>;
    389	mediatek,pad-select = <0>;
    390	status = "okay";
    391};
    392
    393&spi3 {
    394	pinctrl-names = "default";
    395	pinctrl-0 = <&spi_pins_3>;
    396	mediatek,pad-select = <0>;
    397	status = "okay";
    398};
    399
    400&spi4 {
    401	pinctrl-names = "default";
    402	pinctrl-0 = <&spi_pins_4>;
    403	mediatek,pad-select = <0>;
    404	status = "okay";
    405};
    406
    407&spi5 {
    408	pinctrl-names = "default";
    409	pinctrl-0 = <&spi_pins_5>;
    410	mediatek,pad-select = <0>;
    411	status = "okay";
    412
    413};
    414
    415&uart0 {
    416	status = "okay";
    417};
    418
    419&pwm1 {
    420	status = "okay";
    421	pinctrl-0 = <&pwm_pins_1>;
    422	pinctrl-names = "default";
    423};