cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

mt8183-kukui-kodama.dtsi (5208B)


      1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
      2/*
      3 * Copyright 2021 Google LLC
      4 */
      5
      6/dts-v1/;
      7#include "mt8183-kukui.dtsi"
      8#include "mt8183-kukui-audio-ts3a227e-max98357a.dtsi"
      9
     10/ {
     11	ppvarn_lcd: ppvarn-lcd {
     12		compatible = "regulator-fixed";
     13		regulator-name = "ppvarn_lcd";
     14		pinctrl-names = "default";
     15		pinctrl-0 = <&ppvarn_lcd_en>;
     16
     17		enable-active-high;
     18
     19		gpio = <&pio 66 GPIO_ACTIVE_HIGH>;
     20	};
     21
     22	ppvarp_lcd: ppvarp-lcd {
     23		compatible = "regulator-fixed";
     24		regulator-name = "ppvarp_lcd";
     25		pinctrl-names = "default";
     26		pinctrl-0 = <&ppvarp_lcd_en>;
     27
     28		enable-active-high;
     29
     30		gpio = <&pio 166 GPIO_ACTIVE_HIGH>;
     31	};
     32
     33	pp1800_lcd: pp1800-lcd {
     34		compatible = "regulator-fixed";
     35		regulator-name = "pp1800_lcd";
     36		pinctrl-names = "default";
     37		pinctrl-0 = <&pp1800_lcd_en>;
     38
     39		enable-active-high;
     40
     41		gpio = <&pio 36 GPIO_ACTIVE_HIGH>;
     42	};
     43};
     44
     45&i2c0 {
     46	status = "okay";
     47
     48	touchscreen: touchscreen@10 {
     49		compatible = "hid-over-i2c";
     50		reg = <0x10>;
     51		interrupt-parent = <&pio>;
     52		interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
     53		pinctrl-names = "default";
     54		pinctrl-0 = <&touch_default>;
     55
     56		post-power-on-delay-ms = <10>;
     57		hid-descr-addr = <0x0001>;
     58	};
     59};
     60
     61&i2c2 {
     62        pinctrl-names = "default";
     63	pinctrl-0 = <&i2c2_pins>;
     64	status = "okay";
     65	clock-frequency = <400000>;
     66	vbus-supply = <&mt6358_vcamio_reg>;
     67
     68	eeprom@58 {
     69		compatible = "atmel,24c64";
     70		reg = <0x58>;
     71		pagesize = <32>;
     72		vcc-supply = <&mt6358_vcamio_reg>;
     73	};
     74};
     75
     76&i2c4 {
     77        pinctrl-names = "default";
     78	pinctrl-0 = <&i2c4_pins>;
     79	status = "okay";
     80	clock-frequency = <400000>;
     81	vbus-supply = <&mt6358_vcn18_reg>;
     82
     83	eeprom@54 {
     84		compatible = "atmel,24c64";
     85		reg = <0x54>;
     86		pagesize = <32>;
     87		vcc-supply = <&mt6358_vcn18_reg>;
     88	};
     89};
     90
     91&mt6358_vcama2_reg {
     92	regulator-min-microvolt = <2800000>;
     93	regulator-max-microvolt = <2800000>;
     94};
     95
     96&pio {
     97	/* 192 lines */
     98	gpio-line-names =
     99		"SPI_AP_EC_CS_L",
    100		"SPI_AP_EC_MOSI",
    101		"SPI_AP_EC_CLK",
    102		"I2S3_DO",
    103		"USB_PD_INT_ODL",
    104		"",
    105		"",
    106		"",
    107		"",
    108		"IT6505_HPD_L",
    109		"I2S3_TDM_D3",
    110		"SOC_I2C6_1V8_SCL",
    111		"SOC_I2C6_1V8_SDA",
    112		"DPI_D0",
    113		"DPI_D1",
    114		"DPI_D2",
    115		"DPI_D3",
    116		"DPI_D4",
    117		"DPI_D5",
    118		"DPI_D6",
    119		"DPI_D7",
    120		"DPI_D8",
    121		"DPI_D9",
    122		"DPI_D10",
    123		"DPI_D11",
    124		"DPI_HSYNC",
    125		"DPI_VSYNC",
    126		"DPI_DE",
    127		"DPI_CK",
    128		"AP_MSDC1_CLK",
    129		"AP_MSDC1_DAT3",
    130		"AP_MSDC1_CMD",
    131		"AP_MSDC1_DAT0",
    132		"AP_MSDC1_DAT2",
    133		"AP_MSDC1_DAT1",
    134		"",
    135		"",
    136		"",
    137		"",
    138		"",
    139		"",
    140		"OTG_EN",
    141		"DRVBUS",
    142		"DISP_PWM",
    143		"DSI_TE",
    144		"LCM_RST_1V8",
    145		"AP_CTS_WIFI_RTS",
    146		"AP_RTS_WIFI_CTS",
    147		"SOC_I2C5_1V8_SCL",
    148		"SOC_I2C5_1V8_SDA",
    149		"SOC_I2C3_1V8_SCL",
    150		"SOC_I2C3_1V8_SDA",
    151		"",
    152		"",
    153		"",
    154		"",
    155		"",
    156		"",
    157		"",
    158		"",
    159		"",
    160		"",
    161		"",
    162		"",
    163		"",
    164		"",
    165		"",
    166		"",
    167		"",
    168		"",
    169		"",
    170		"",
    171		"",
    172		"",
    173		"",
    174		"",
    175		"",
    176		"",
    177		"",
    178		"",
    179		"",
    180		"SOC_I2C1_1V8_SDA",
    181		"SOC_I2C0_1V8_SDA",
    182		"SOC_I2C0_1V8_SCL",
    183		"SOC_I2C1_1V8_SCL",
    184		"AP_SPI_H1_MISO",
    185		"AP_SPI_H1_CS_L",
    186		"AP_SPI_H1_MOSI",
    187		"AP_SPI_H1_CLK",
    188		"I2S5_BCK",
    189		"I2S5_LRCK",
    190		"I2S5_DO",
    191		"BOOTBLOCK_EN_L",
    192		"MT8183_KPCOL0",
    193		"SPI_AP_EC_MISO",
    194		"UART_DBG_TX_AP_RX",
    195		"UART_AP_TX_DBG_RX",
    196		"I2S2_MCK",
    197		"I2S2_BCK",
    198		"CLK_5M_WCAM",
    199		"CLK_2M_UCAM",
    200		"I2S2_LRCK",
    201		"I2S2_DI",
    202		"SOC_I2C2_1V8_SCL",
    203		"SOC_I2C2_1V8_SDA",
    204		"SOC_I2C4_1V8_SCL",
    205		"SOC_I2C4_1V8_SDA",
    206		"",
    207		"SCL8",
    208		"SDA8",
    209		"FCAM_PWDN_L",
    210		"",
    211		"",
    212		"",
    213		"",
    214		"",
    215		"",
    216		"",
    217		"",
    218		"",
    219		"",
    220		"",
    221		"",
    222		"",
    223		"",
    224		"",
    225		"",
    226		"",
    227		"",
    228		"",
    229		"",
    230		"",
    231		"",
    232		"",
    233		"",
    234		"",
    235		"I2S_PMIC",
    236		"I2S_PMIC",
    237		"I2S_PMIC",
    238		"I2S_PMIC",
    239		"I2S_PMIC",
    240		"I2S_PMIC",
    241		"I2S_PMIC",
    242		"I2S_PMIC",
    243		"",
    244		"",
    245		"",
    246		"",
    247		"",
    248		"",
    249		/*
    250		 * AP_FLASH_WP_L is crossystem ABI. Rev1 schematics
    251		 * call it BIOS_FLASH_WP_R_L.
    252		 */
    253		"AP_FLASH_WP_L",
    254		"EC_AP_INT_ODL",
    255		"IT6505_INT_ODL",
    256		"H1_INT_OD_L",
    257		"",
    258		"",
    259		"",
    260		"",
    261		"",
    262		"",
    263		"",
    264		"AP_SPI_FLASH_MISO",
    265		"AP_SPI_FLASH_CS_L",
    266		"AP_SPI_FLASH_MOSI",
    267		"AP_SPI_FLASH_CLK",
    268		"DA7219_IRQ",
    269		"",
    270		"",
    271		"",
    272		"",
    273		"",
    274		"",
    275		"",
    276		"",
    277		"",
    278		"",
    279		"",
    280		"",
    281		"",
    282		"",
    283		"",
    284		"",
    285		"",
    286		"",
    287		"",
    288		"",
    289		"",
    290		"",
    291		"",
    292		"",
    293		"",
    294		"";
    295
    296	ppvarp_lcd_en: ppvarp-lcd-en {
    297		pins1 {
    298			pinmux = <PINMUX_GPIO66__FUNC_GPIO66>;
    299			output-low;
    300		};
    301	};
    302
    303	ppvarn_lcd_en: ppvarn-lcd-en {
    304		pins1 {
    305			pinmux = <PINMUX_GPIO166__FUNC_GPIO166>;
    306			output-low;
    307		};
    308	};
    309
    310	pp1800_lcd_en: pp1800-lcd-en {
    311		pins1 {
    312			pinmux = <PINMUX_GPIO36__FUNC_GPIO36>;
    313			output-low;
    314		};
    315	};
    316
    317	touch_default: touchdefault {
    318		pin_irq {
    319			pinmux = <PINMUX_GPIO155__FUNC_GPIO155>;
    320			input-enable;
    321			bias-pull-up;
    322		};
    323
    324		touch_pin_reset: pin_reset {
    325			pinmux = <PINMUX_GPIO156__FUNC_GPIO156>;
    326
    327			/*
    328			 * The touchscreen driver doesn't currently support driving
    329			 * this reset line.  By specifying output-high here
    330			 * we're relying on the fact that this pin has a default
    331			 * pulldown at boot (which makes sure the controller was in
    332			 * reset if it was powered) and then we set it high here
    333			 * to take it out of reset.  Better would be if the touchscreen
    334			 * driver could control this and we could remove
    335			 * "output-high" here.
    336			 */
    337			output-high;
    338		};
    339	};
    340};
    341
    342&qca_wifi {
    343	qcom,ath10k-calibration-variant = "GO_KODAMA";
    344};
    345
    346&i2c_tunnel {
    347        google,remote-bus = <2>;
    348};