mt8195.dtsi (28578B)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8195-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/phy/phy.h> 12#include <dt-bindings/pinctrl/mt8195-pinfunc.h> 13#include <dt-bindings/reset/ti-syscon.h> 14 15/ { 16 compatible = "mediatek,mt8195"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-a55"; 28 reg = <0x000>; 29 enable-method = "psci"; 30 clock-frequency = <1701000000>; 31 capacity-dmips-mhz = <578>; 32 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 33 next-level-cache = <&l2_0>; 34 #cooling-cells = <2>; 35 }; 36 37 cpu1: cpu@100 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a55"; 40 reg = <0x100>; 41 enable-method = "psci"; 42 clock-frequency = <1701000000>; 43 capacity-dmips-mhz = <578>; 44 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 45 next-level-cache = <&l2_0>; 46 #cooling-cells = <2>; 47 }; 48 49 cpu2: cpu@200 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a55"; 52 reg = <0x200>; 53 enable-method = "psci"; 54 clock-frequency = <1701000000>; 55 capacity-dmips-mhz = <578>; 56 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 57 next-level-cache = <&l2_0>; 58 #cooling-cells = <2>; 59 }; 60 61 cpu3: cpu@300 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a55"; 64 reg = <0x300>; 65 enable-method = "psci"; 66 clock-frequency = <1701000000>; 67 capacity-dmips-mhz = <578>; 68 cpu-idle-states = <&cpu_off_l &cluster_off_l>; 69 next-level-cache = <&l2_0>; 70 #cooling-cells = <2>; 71 }; 72 73 cpu4: cpu@400 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a78"; 76 reg = <0x400>; 77 enable-method = "psci"; 78 clock-frequency = <2171000000>; 79 capacity-dmips-mhz = <1024>; 80 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 81 next-level-cache = <&l2_1>; 82 #cooling-cells = <2>; 83 }; 84 85 cpu5: cpu@500 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a78"; 88 reg = <0x500>; 89 enable-method = "psci"; 90 clock-frequency = <2171000000>; 91 capacity-dmips-mhz = <1024>; 92 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 93 next-level-cache = <&l2_1>; 94 #cooling-cells = <2>; 95 }; 96 97 cpu6: cpu@600 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a78"; 100 reg = <0x600>; 101 enable-method = "psci"; 102 clock-frequency = <2171000000>; 103 capacity-dmips-mhz = <1024>; 104 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 105 next-level-cache = <&l2_1>; 106 #cooling-cells = <2>; 107 }; 108 109 cpu7: cpu@700 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a78"; 112 reg = <0x700>; 113 enable-method = "psci"; 114 clock-frequency = <2171000000>; 115 capacity-dmips-mhz = <1024>; 116 cpu-idle-states = <&cpu_off_b &cluster_off_b>; 117 next-level-cache = <&l2_1>; 118 #cooling-cells = <2>; 119 }; 120 121 cpu-map { 122 cluster0 { 123 core0 { 124 cpu = <&cpu0>; 125 }; 126 127 core1 { 128 cpu = <&cpu1>; 129 }; 130 131 core2 { 132 cpu = <&cpu2>; 133 }; 134 135 core3 { 136 cpu = <&cpu3>; 137 }; 138 }; 139 140 cluster1 { 141 core0 { 142 cpu = <&cpu4>; 143 }; 144 145 core1 { 146 cpu = <&cpu5>; 147 }; 148 149 core2 { 150 cpu = <&cpu6>; 151 }; 152 153 core3 { 154 cpu = <&cpu7>; 155 }; 156 }; 157 }; 158 159 idle-states { 160 entry-method = "psci"; 161 162 cpu_off_l: cpu-off-l { 163 compatible = "arm,idle-state"; 164 arm,psci-suspend-param = <0x00010001>; 165 local-timer-stop; 166 entry-latency-us = <50>; 167 exit-latency-us = <95>; 168 min-residency-us = <580>; 169 }; 170 171 cpu_off_b: cpu-off-b { 172 compatible = "arm,idle-state"; 173 arm,psci-suspend-param = <0x00010001>; 174 local-timer-stop; 175 entry-latency-us = <45>; 176 exit-latency-us = <140>; 177 min-residency-us = <740>; 178 }; 179 180 cluster_off_l: cluster-off-l { 181 compatible = "arm,idle-state"; 182 arm,psci-suspend-param = <0x01010002>; 183 local-timer-stop; 184 entry-latency-us = <55>; 185 exit-latency-us = <155>; 186 min-residency-us = <840>; 187 }; 188 189 cluster_off_b: cluster-off-b { 190 compatible = "arm,idle-state"; 191 arm,psci-suspend-param = <0x01010002>; 192 local-timer-stop; 193 entry-latency-us = <50>; 194 exit-latency-us = <200>; 195 min-residency-us = <1000>; 196 }; 197 }; 198 199 l2_0: l2-cache0 { 200 compatible = "cache"; 201 next-level-cache = <&l3_0>; 202 }; 203 204 l2_1: l2-cache1 { 205 compatible = "cache"; 206 next-level-cache = <&l3_0>; 207 }; 208 209 l3_0: l3-cache { 210 compatible = "cache"; 211 }; 212 }; 213 214 dsu-pmu { 215 compatible = "arm,dsu-pmu"; 216 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 217 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 218 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 219 }; 220 221 clk26m: oscillator-26m { 222 compatible = "fixed-clock"; 223 #clock-cells = <0>; 224 clock-frequency = <26000000>; 225 clock-output-names = "clk26m"; 226 }; 227 228 clk32k: oscillator-32k { 229 compatible = "fixed-clock"; 230 #clock-cells = <0>; 231 clock-frequency = <32768>; 232 clock-output-names = "clk32k"; 233 }; 234 235 pmu-a55 { 236 compatible = "arm,cortex-a55-pmu"; 237 interrupt-parent = <&gic>; 238 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 239 }; 240 241 pmu-a78 { 242 compatible = "arm,cortex-a78-pmu"; 243 interrupt-parent = <&gic>; 244 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 245 }; 246 247 psci { 248 compatible = "arm,psci-1.0"; 249 method = "smc"; 250 }; 251 252 timer: timer { 253 compatible = "arm,armv8-timer"; 254 interrupt-parent = <&gic>; 255 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 256 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 257 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 258 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 259 }; 260 261 soc { 262 #address-cells = <2>; 263 #size-cells = <2>; 264 compatible = "simple-bus"; 265 ranges; 266 267 gic: interrupt-controller@c000000 { 268 compatible = "arm,gic-v3"; 269 #interrupt-cells = <4>; 270 #redistributor-regions = <1>; 271 interrupt-parent = <&gic>; 272 interrupt-controller; 273 reg = <0 0x0c000000 0 0x40000>, 274 <0 0x0c040000 0 0x200000>; 275 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 276 277 ppi-partitions { 278 ppi_cluster0: interrupt-partition-0 { 279 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 280 }; 281 282 ppi_cluster1: interrupt-partition-1 { 283 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 284 }; 285 }; 286 }; 287 288 topckgen: syscon@10000000 { 289 compatible = "mediatek,mt8195-topckgen", "syscon"; 290 reg = <0 0x10000000 0 0x1000>; 291 #clock-cells = <1>; 292 }; 293 294 infracfg_ao: syscon@10001000 { 295 compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; 296 reg = <0 0x10001000 0 0x1000>; 297 #clock-cells = <1>; 298 299 infracfg_rst: reset-controller { 300 compatible = "ti,syscon-reset"; 301 #reset-cells = <1>; 302 ti,reset-bits = < 303 0x140 18 0x144 18 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* pcie */ 304 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */ 305 0x730 10 0x734 10 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */ 306 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* svs gpu */ 307 >; 308 }; 309 }; 310 311 pericfg: syscon@10003000 { 312 compatible = "mediatek,mt8195-pericfg", "syscon"; 313 reg = <0 0x10003000 0 0x1000>; 314 #clock-cells = <1>; 315 }; 316 317 pio: pinctrl@10005000 { 318 compatible = "mediatek,mt8195-pinctrl"; 319 reg = <0 0x10005000 0 0x1000>, 320 <0 0x11d10000 0 0x1000>, 321 <0 0x11d30000 0 0x1000>, 322 <0 0x11d40000 0 0x1000>, 323 <0 0x11e20000 0 0x1000>, 324 <0 0x11eb0000 0 0x1000>, 325 <0 0x11f40000 0 0x1000>, 326 <0 0x1000b000 0 0x1000>; 327 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", 328 "iocfg_br", "iocfg_lm", "iocfg_rb", 329 "iocfg_tl", "eint"; 330 gpio-controller; 331 #gpio-cells = <2>; 332 gpio-ranges = <&pio 0 0 144>; 333 interrupt-controller; 334 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; 335 #interrupt-cells = <2>; 336 }; 337 338 watchdog: watchdog@10007000 { 339 compatible = "mediatek,mt8195-wdt", 340 "mediatek,mt6589-wdt"; 341 reg = <0 0x10007000 0 0x100>; 342 }; 343 344 apmixedsys: syscon@1000c000 { 345 compatible = "mediatek,mt8195-apmixedsys", "syscon"; 346 reg = <0 0x1000c000 0 0x1000>; 347 #clock-cells = <1>; 348 }; 349 350 systimer: timer@10017000 { 351 compatible = "mediatek,mt8195-timer", 352 "mediatek,mt6765-timer"; 353 reg = <0 0x10017000 0 0x1000>; 354 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 355 clocks = <&topckgen CLK_TOP_CLK26M_D2>; 356 }; 357 358 pwrap: pwrap@10024000 { 359 compatible = "mediatek,mt8195-pwrap", "syscon"; 360 reg = <0 0x10024000 0 0x1000>; 361 reg-names = "pwrap"; 362 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 363 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 364 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 365 clock-names = "spi", "wrap"; 366 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 367 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 368 }; 369 370 scp_adsp: clock-controller@10720000 { 371 compatible = "mediatek,mt8195-scp_adsp"; 372 reg = <0 0x10720000 0 0x1000>; 373 #clock-cells = <1>; 374 }; 375 376 uart0: serial@11001100 { 377 compatible = "mediatek,mt8195-uart", 378 "mediatek,mt6577-uart"; 379 reg = <0 0x11001100 0 0x100>; 380 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; 381 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 382 clock-names = "baud", "bus"; 383 status = "disabled"; 384 }; 385 386 uart1: serial@11001200 { 387 compatible = "mediatek,mt8195-uart", 388 "mediatek,mt6577-uart"; 389 reg = <0 0x11001200 0 0x100>; 390 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 391 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 392 clock-names = "baud", "bus"; 393 status = "disabled"; 394 }; 395 396 uart2: serial@11001300 { 397 compatible = "mediatek,mt8195-uart", 398 "mediatek,mt6577-uart"; 399 reg = <0 0x11001300 0 0x100>; 400 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 401 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 402 clock-names = "baud", "bus"; 403 status = "disabled"; 404 }; 405 406 uart3: serial@11001400 { 407 compatible = "mediatek,mt8195-uart", 408 "mediatek,mt6577-uart"; 409 reg = <0 0x11001400 0 0x100>; 410 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; 411 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; 412 clock-names = "baud", "bus"; 413 status = "disabled"; 414 }; 415 416 uart4: serial@11001500 { 417 compatible = "mediatek,mt8195-uart", 418 "mediatek,mt6577-uart"; 419 reg = <0 0x11001500 0 0x100>; 420 interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>; 421 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>; 422 clock-names = "baud", "bus"; 423 status = "disabled"; 424 }; 425 426 uart5: serial@11001600 { 427 compatible = "mediatek,mt8195-uart", 428 "mediatek,mt6577-uart"; 429 reg = <0 0x11001600 0 0x100>; 430 interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>; 431 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>; 432 clock-names = "baud", "bus"; 433 status = "disabled"; 434 }; 435 436 auxadc: auxadc@11002000 { 437 compatible = "mediatek,mt8195-auxadc", 438 "mediatek,mt8173-auxadc"; 439 reg = <0 0x11002000 0 0x1000>; 440 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 441 clock-names = "main"; 442 #io-channel-cells = <1>; 443 status = "disabled"; 444 }; 445 446 pericfg_ao: syscon@11003000 { 447 compatible = "mediatek,mt8195-pericfg_ao", "syscon"; 448 reg = <0 0x11003000 0 0x1000>; 449 #clock-cells = <1>; 450 }; 451 452 spi0: spi@1100a000 { 453 compatible = "mediatek,mt8195-spi", 454 "mediatek,mt6765-spi"; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 reg = <0 0x1100a000 0 0x1000>; 458 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; 459 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 460 <&topckgen CLK_TOP_SPI>, 461 <&infracfg_ao CLK_INFRA_AO_SPI0>; 462 clock-names = "parent-clk", "sel-clk", "spi-clk"; 463 status = "disabled"; 464 }; 465 466 spi1: spi@11010000 { 467 compatible = "mediatek,mt8195-spi", 468 "mediatek,mt6765-spi"; 469 #address-cells = <1>; 470 #size-cells = <0>; 471 reg = <0 0x11010000 0 0x1000>; 472 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; 473 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 474 <&topckgen CLK_TOP_SPI>, 475 <&infracfg_ao CLK_INFRA_AO_SPI1>; 476 clock-names = "parent-clk", "sel-clk", "spi-clk"; 477 status = "disabled"; 478 }; 479 480 spi2: spi@11012000 { 481 compatible = "mediatek,mt8195-spi", 482 "mediatek,mt6765-spi"; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 reg = <0 0x11012000 0 0x1000>; 486 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 487 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 488 <&topckgen CLK_TOP_SPI>, 489 <&infracfg_ao CLK_INFRA_AO_SPI2>; 490 clock-names = "parent-clk", "sel-clk", "spi-clk"; 491 status = "disabled"; 492 }; 493 494 spi3: spi@11013000 { 495 compatible = "mediatek,mt8195-spi", 496 "mediatek,mt6765-spi"; 497 #address-cells = <1>; 498 #size-cells = <0>; 499 reg = <0 0x11013000 0 0x1000>; 500 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 501 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 502 <&topckgen CLK_TOP_SPI>, 503 <&infracfg_ao CLK_INFRA_AO_SPI3>; 504 clock-names = "parent-clk", "sel-clk", "spi-clk"; 505 status = "disabled"; 506 }; 507 508 spi4: spi@11018000 { 509 compatible = "mediatek,mt8195-spi", 510 "mediatek,mt6765-spi"; 511 #address-cells = <1>; 512 #size-cells = <0>; 513 reg = <0 0x11018000 0 0x1000>; 514 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 515 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 516 <&topckgen CLK_TOP_SPI>, 517 <&infracfg_ao CLK_INFRA_AO_SPI4>; 518 clock-names = "parent-clk", "sel-clk", "spi-clk"; 519 status = "disabled"; 520 }; 521 522 spi5: spi@11019000 { 523 compatible = "mediatek,mt8195-spi", 524 "mediatek,mt6765-spi"; 525 #address-cells = <1>; 526 #size-cells = <0>; 527 reg = <0 0x11019000 0 0x1000>; 528 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 529 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 530 <&topckgen CLK_TOP_SPI>, 531 <&infracfg_ao CLK_INFRA_AO_SPI5>; 532 clock-names = "parent-clk", "sel-clk", "spi-clk"; 533 status = "disabled"; 534 }; 535 536 spis0: spi@1101d000 { 537 compatible = "mediatek,mt8195-spi-slave"; 538 reg = <0 0x1101d000 0 0x1000>; 539 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; 540 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>; 541 clock-names = "spi"; 542 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 543 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 544 status = "disabled"; 545 }; 546 547 spis1: spi@1101e000 { 548 compatible = "mediatek,mt8195-spi-slave"; 549 reg = <0 0x1101e000 0 0x1000>; 550 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; 551 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>; 552 clock-names = "spi"; 553 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 554 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 555 status = "disabled"; 556 }; 557 558 xhci0: usb@11200000 { 559 compatible = "mediatek,mt8195-xhci", 560 "mediatek,mtk-xhci"; 561 reg = <0 0x11200000 0 0x1000>, 562 <0 0x11203e00 0 0x0100>; 563 reg-names = "mac", "ippc"; 564 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; 565 phys = <&u2port0 PHY_TYPE_USB2>, 566 <&u3port0 PHY_TYPE_USB3>; 567 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, 568 <&topckgen CLK_TOP_SSUSB_XHCI>; 569 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 570 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 571 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, 572 <&topckgen CLK_TOP_SSUSB_REF>, 573 <&apmixedsys CLK_APMIXED_USB1PLL>, 574 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; 575 clock-names = "sys_ck", "ref_ck", "mcu_ck", "xhci_ck"; 576 status = "disabled"; 577 }; 578 579 mmc0: mmc@11230000 { 580 compatible = "mediatek,mt8195-mmc", 581 "mediatek,mt8183-mmc"; 582 reg = <0 0x11230000 0 0x10000>, 583 <0 0x11f50000 0 0x1000>; 584 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 585 clocks = <&topckgen CLK_TOP_MSDC50_0>, 586 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 587 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; 588 clock-names = "source", "hclk", "source_cg"; 589 status = "disabled"; 590 }; 591 592 mmc1: mmc@11240000 { 593 compatible = "mediatek,mt8195-mmc", 594 "mediatek,mt8183-mmc"; 595 reg = <0 0x11240000 0 0x1000>, 596 <0 0x11c70000 0 0x1000>; 597 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 598 clocks = <&topckgen CLK_TOP_MSDC30_1>, 599 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 600 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 601 clock-names = "source", "hclk", "source_cg"; 602 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 603 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 604 status = "disabled"; 605 }; 606 607 mmc2: mmc@11250000 { 608 compatible = "mediatek,mt8195-mmc", 609 "mediatek,mt8183-mmc"; 610 reg = <0 0x11250000 0 0x1000>, 611 <0 0x11e60000 0 0x1000>; 612 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; 613 clocks = <&topckgen CLK_TOP_MSDC30_2>, 614 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>, 615 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>; 616 clock-names = "source", "hclk", "source_cg"; 617 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; 618 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 619 status = "disabled"; 620 }; 621 622 xhci1: usb@11290000 { 623 compatible = "mediatek,mt8195-xhci", 624 "mediatek,mtk-xhci"; 625 reg = <0 0x11290000 0 0x1000>, 626 <0 0x11293e00 0 0x0100>; 627 reg-names = "mac", "ippc"; 628 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>; 629 phys = <&u2port1 PHY_TYPE_USB2>; 630 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>, 631 <&topckgen CLK_TOP_SSUSB_XHCI_1P>; 632 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 633 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 634 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, 635 <&topckgen CLK_TOP_SSUSB_P1_REF>, 636 <&apmixedsys CLK_APMIXED_USB1PLL>, 637 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; 638 clock-names = "sys_ck", "ref_ck", "mcu_ck","xhci_ck"; 639 status = "disabled"; 640 }; 641 642 xhci2: usb@112a0000 { 643 compatible = "mediatek,mt8195-xhci", 644 "mediatek,mtk-xhci"; 645 reg = <0 0x112a0000 0 0x1000>, 646 <0 0x112a3e00 0 0x0100>; 647 reg-names = "mac", "ippc"; 648 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 649 phys = <&u2port2 PHY_TYPE_USB2>; 650 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>, 651 <&topckgen CLK_TOP_SSUSB_XHCI_2P>; 652 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 653 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 654 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, 655 <&topckgen CLK_TOP_SSUSB_P2_REF>, 656 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 657 clock-names = "sys_ck", "ref_ck", "xhci_ck"; 658 status = "disabled"; 659 }; 660 661 xhci3: usb@112b0000 { 662 compatible = "mediatek,mt8195-xhci", 663 "mediatek,mtk-xhci"; 664 reg = <0 0x112b0000 0 0x1000>, 665 <0 0x112b3e00 0 0x0100>; 666 reg-names = "mac", "ippc"; 667 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 668 phys = <&u2port3 PHY_TYPE_USB2>; 669 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>, 670 <&topckgen CLK_TOP_SSUSB_XHCI_3P>; 671 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 672 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 673 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, 674 <&topckgen CLK_TOP_SSUSB_P3_REF>, 675 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 676 clock-names = "sys_ck", "ref_ck", "xhci_ck"; 677 status = "disabled"; 678 }; 679 680 nor_flash: spi@1132c000 { 681 compatible = "mediatek,mt8195-nor", 682 "mediatek,mt8173-nor"; 683 reg = <0 0x1132c000 0 0x1000>; 684 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; 685 clocks = <&topckgen CLK_TOP_SPINOR>, 686 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>, 687 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; 688 clock-names = "spi", "sf", "axi"; 689 #address-cells = <1>; 690 #size-cells = <0>; 691 status = "disabled"; 692 }; 693 694 u3phy2: t-phy@11c40000 { 695 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 696 #address-cells = <1>; 697 #size-cells = <1>; 698 ranges = <0 0 0x11c40000 0x700>; 699 status = "disabled"; 700 701 u2port2: usb-phy@0 { 702 reg = <0x0 0x700>; 703 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; 704 clock-names = "ref"; 705 #phy-cells = <1>; 706 }; 707 }; 708 709 u3phy3: t-phy@11c50000 { 710 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 711 #address-cells = <1>; 712 #size-cells = <1>; 713 ranges = <0 0 0x11c50000 0x700>; 714 status = "disabled"; 715 716 u2port3: usb-phy@0 { 717 reg = <0x0 0x700>; 718 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; 719 clock-names = "ref"; 720 #phy-cells = <1>; 721 }; 722 }; 723 724 i2c5: i2c@11d00000 { 725 compatible = "mediatek,mt8195-i2c", 726 "mediatek,mt8192-i2c"; 727 reg = <0 0x11d00000 0 0x1000>, 728 <0 0x10220580 0 0x80>; 729 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>; 730 clock-div = <1>; 731 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>, 732 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 733 clock-names = "main", "dma"; 734 #address-cells = <1>; 735 #size-cells = <0>; 736 status = "disabled"; 737 }; 738 739 i2c6: i2c@11d01000 { 740 compatible = "mediatek,mt8195-i2c", 741 "mediatek,mt8192-i2c"; 742 reg = <0 0x11d01000 0 0x1000>, 743 <0 0x10220600 0 0x80>; 744 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; 745 clock-div = <1>; 746 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>, 747 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 748 clock-names = "main", "dma"; 749 #address-cells = <1>; 750 #size-cells = <0>; 751 status = "disabled"; 752 }; 753 754 i2c7: i2c@11d02000 { 755 compatible = "mediatek,mt8195-i2c", 756 "mediatek,mt8192-i2c"; 757 reg = <0 0x11d02000 0 0x1000>, 758 <0 0x10220680 0 0x80>; 759 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 760 clock-div = <1>; 761 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 762 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 763 clock-names = "main", "dma"; 764 #address-cells = <1>; 765 #size-cells = <0>; 766 status = "disabled"; 767 }; 768 769 imp_iic_wrap_s: clock-controller@11d03000 { 770 compatible = "mediatek,mt8195-imp_iic_wrap_s"; 771 reg = <0 0x11d03000 0 0x1000>; 772 #clock-cells = <1>; 773 }; 774 775 i2c0: i2c@11e00000 { 776 compatible = "mediatek,mt8195-i2c", 777 "mediatek,mt8192-i2c"; 778 reg = <0 0x11e00000 0 0x1000>, 779 <0 0x10220080 0 0x80>; 780 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>; 781 clock-div = <1>; 782 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>, 783 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 784 clock-names = "main", "dma"; 785 #address-cells = <1>; 786 #size-cells = <0>; 787 status = "okay"; 788 }; 789 790 i2c1: i2c@11e01000 { 791 compatible = "mediatek,mt8195-i2c", 792 "mediatek,mt8192-i2c"; 793 reg = <0 0x11e01000 0 0x1000>, 794 <0 0x10220200 0 0x80>; 795 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; 796 clock-div = <1>; 797 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>, 798 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 799 clock-names = "main", "dma"; 800 #address-cells = <1>; 801 #size-cells = <0>; 802 status = "disabled"; 803 }; 804 805 i2c2: i2c@11e02000 { 806 compatible = "mediatek,mt8195-i2c", 807 "mediatek,mt8192-i2c"; 808 reg = <0 0x11e02000 0 0x1000>, 809 <0 0x10220380 0 0x80>; 810 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 811 clock-div = <1>; 812 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>, 813 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 814 clock-names = "main", "dma"; 815 #address-cells = <1>; 816 #size-cells = <0>; 817 status = "disabled"; 818 }; 819 820 i2c3: i2c@11e03000 { 821 compatible = "mediatek,mt8195-i2c", 822 "mediatek,mt8192-i2c"; 823 reg = <0 0x11e03000 0 0x1000>, 824 <0 0x10220480 0 0x80>; 825 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 826 clock-div = <1>; 827 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>, 828 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 829 clock-names = "main", "dma"; 830 #address-cells = <1>; 831 #size-cells = <0>; 832 status = "disabled"; 833 }; 834 835 i2c4: i2c@11e04000 { 836 compatible = "mediatek,mt8195-i2c", 837 "mediatek,mt8192-i2c"; 838 reg = <0 0x11e04000 0 0x1000>, 839 <0 0x10220500 0 0x80>; 840 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>; 841 clock-div = <1>; 842 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>, 843 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 844 clock-names = "main", "dma"; 845 #address-cells = <1>; 846 #size-cells = <0>; 847 status = "disabled"; 848 }; 849 850 imp_iic_wrap_w: clock-controller@11e05000 { 851 compatible = "mediatek,mt8195-imp_iic_wrap_w"; 852 reg = <0 0x11e05000 0 0x1000>; 853 #clock-cells = <1>; 854 }; 855 856 u3phy1: t-phy@11e30000 { 857 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 858 #address-cells = <1>; 859 #size-cells = <1>; 860 ranges = <0 0 0x11e30000 0xe00>; 861 status = "disabled"; 862 863 u2port1: usb-phy@0 { 864 reg = <0x0 0x700>; 865 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>, 866 <&clk26m>; 867 clock-names = "ref", "da_ref"; 868 #phy-cells = <1>; 869 }; 870 871 u3port1: usb-phy@700 { 872 reg = <0x700 0x700>; 873 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 874 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; 875 clock-names = "ref", "da_ref"; 876 #phy-cells = <1>; 877 }; 878 }; 879 880 u3phy0: t-phy@11e40000 { 881 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 882 #address-cells = <1>; 883 #size-cells = <1>; 884 ranges = <0 0 0x11e40000 0xe00>; 885 status = "disabled"; 886 887 u2port0: usb-phy@0 { 888 reg = <0x0 0x700>; 889 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, 890 <&clk26m>; 891 clock-names = "ref", "da_ref"; 892 #phy-cells = <1>; 893 }; 894 895 u3port0: usb-phy@700 { 896 reg = <0x700 0x700>; 897 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 898 <&topckgen CLK_TOP_SSUSB_PHY_REF>; 899 clock-names = "ref", "da_ref"; 900 #phy-cells = <1>; 901 }; 902 }; 903 904 ufsphy: ufs-phy@11fa0000 { 905 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; 906 reg = <0 0x11fa0000 0 0xc000>; 907 clocks = <&clk26m>, <&clk26m>; 908 clock-names = "unipro", "mp"; 909 #phy-cells = <0>; 910 status = "disabled"; 911 }; 912 913 mfgcfg: clock-controller@13fbf000 { 914 compatible = "mediatek,mt8195-mfgcfg"; 915 reg = <0 0x13fbf000 0 0x1000>; 916 #clock-cells = <1>; 917 }; 918 919 wpesys: clock-controller@14e00000 { 920 compatible = "mediatek,mt8195-wpesys"; 921 reg = <0 0x14e00000 0 0x1000>; 922 #clock-cells = <1>; 923 }; 924 925 wpesys_vpp0: clock-controller@14e02000 { 926 compatible = "mediatek,mt8195-wpesys_vpp0"; 927 reg = <0 0x14e02000 0 0x1000>; 928 #clock-cells = <1>; 929 }; 930 931 wpesys_vpp1: clock-controller@14e03000 { 932 compatible = "mediatek,mt8195-wpesys_vpp1"; 933 reg = <0 0x14e03000 0 0x1000>; 934 #clock-cells = <1>; 935 }; 936 937 imgsys: clock-controller@15000000 { 938 compatible = "mediatek,mt8195-imgsys"; 939 reg = <0 0x15000000 0 0x1000>; 940 #clock-cells = <1>; 941 }; 942 943 imgsys1_dip_top: clock-controller@15110000 { 944 compatible = "mediatek,mt8195-imgsys1_dip_top"; 945 reg = <0 0x15110000 0 0x1000>; 946 #clock-cells = <1>; 947 }; 948 949 imgsys1_dip_nr: clock-controller@15130000 { 950 compatible = "mediatek,mt8195-imgsys1_dip_nr"; 951 reg = <0 0x15130000 0 0x1000>; 952 #clock-cells = <1>; 953 }; 954 955 imgsys1_wpe: clock-controller@15220000 { 956 compatible = "mediatek,mt8195-imgsys1_wpe"; 957 reg = <0 0x15220000 0 0x1000>; 958 #clock-cells = <1>; 959 }; 960 961 ipesys: clock-controller@15330000 { 962 compatible = "mediatek,mt8195-ipesys"; 963 reg = <0 0x15330000 0 0x1000>; 964 #clock-cells = <1>; 965 }; 966 967 camsys: clock-controller@16000000 { 968 compatible = "mediatek,mt8195-camsys"; 969 reg = <0 0x16000000 0 0x1000>; 970 #clock-cells = <1>; 971 }; 972 973 camsys_rawa: clock-controller@1604f000 { 974 compatible = "mediatek,mt8195-camsys_rawa"; 975 reg = <0 0x1604f000 0 0x1000>; 976 #clock-cells = <1>; 977 }; 978 979 camsys_yuva: clock-controller@1606f000 { 980 compatible = "mediatek,mt8195-camsys_yuva"; 981 reg = <0 0x1606f000 0 0x1000>; 982 #clock-cells = <1>; 983 }; 984 985 camsys_rawb: clock-controller@1608f000 { 986 compatible = "mediatek,mt8195-camsys_rawb"; 987 reg = <0 0x1608f000 0 0x1000>; 988 #clock-cells = <1>; 989 }; 990 991 camsys_yuvb: clock-controller@160af000 { 992 compatible = "mediatek,mt8195-camsys_yuvb"; 993 reg = <0 0x160af000 0 0x1000>; 994 #clock-cells = <1>; 995 }; 996 997 camsys_mraw: clock-controller@16140000 { 998 compatible = "mediatek,mt8195-camsys_mraw"; 999 reg = <0 0x16140000 0 0x1000>; 1000 #clock-cells = <1>; 1001 }; 1002 1003 ccusys: clock-controller@17200000 { 1004 compatible = "mediatek,mt8195-ccusys"; 1005 reg = <0 0x17200000 0 0x1000>; 1006 #clock-cells = <1>; 1007 }; 1008 1009 vdecsys_soc: clock-controller@1800f000 { 1010 compatible = "mediatek,mt8195-vdecsys_soc"; 1011 reg = <0 0x1800f000 0 0x1000>; 1012 #clock-cells = <1>; 1013 }; 1014 1015 vdecsys: clock-controller@1802f000 { 1016 compatible = "mediatek,mt8195-vdecsys"; 1017 reg = <0 0x1802f000 0 0x1000>; 1018 #clock-cells = <1>; 1019 }; 1020 1021 vdecsys_core1: clock-controller@1803f000 { 1022 compatible = "mediatek,mt8195-vdecsys_core1"; 1023 reg = <0 0x1803f000 0 0x1000>; 1024 #clock-cells = <1>; 1025 }; 1026 1027 apusys_pll: clock-controller@190f3000 { 1028 compatible = "mediatek,mt8195-apusys_pll"; 1029 reg = <0 0x190f3000 0 0x1000>; 1030 #clock-cells = <1>; 1031 }; 1032 1033 vencsys: clock-controller@1a000000 { 1034 compatible = "mediatek,mt8195-vencsys"; 1035 reg = <0 0x1a000000 0 0x1000>; 1036 #clock-cells = <1>; 1037 }; 1038 1039 vencsys_core1: clock-controller@1b000000 { 1040 compatible = "mediatek,mt8195-vencsys_core1"; 1041 reg = <0 0x1b000000 0 0x1000>; 1042 #clock-cells = <1>; 1043 }; 1044 }; 1045};