cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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tegra132.dtsi (34265B)


      1// SPDX-License-Identifier: GPL-2.0
      2#include <dt-bindings/clock/tegra124-car.h>
      3#include <dt-bindings/gpio/tegra-gpio.h>
      4#include <dt-bindings/memory/tegra124-mc.h>
      5#include <dt-bindings/pinctrl/pinctrl-tegra.h>
      6#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
      7#include <dt-bindings/interrupt-controller/arm-gic.h>
      8#include <dt-bindings/thermal/tegra124-soctherm.h>
      9#include <dt-bindings/soc/tegra-pmc.h>
     10
     11#include "tegra132-peripherals-opp.dtsi"
     12
     13/ {
     14	compatible = "nvidia,tegra132", "nvidia,tegra124";
     15	interrupt-parent = <&lic>;
     16	#address-cells = <2>;
     17	#size-cells = <2>;
     18
     19	pcie@1003000 {
     20		compatible = "nvidia,tegra124-pcie";
     21		device_type = "pci";
     22		reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
     23		      <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
     24		      <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
     25		reg-names = "pads", "afi", "cs";
     26		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
     27			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
     28		interrupt-names = "intr", "msi";
     29
     30		#interrupt-cells = <1>;
     31		interrupt-map-mask = <0 0 0 0>;
     32		interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
     33
     34		bus-range = <0x00 0xff>;
     35		#address-cells = <3>;
     36		#size-cells = <2>;
     37
     38		ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
     39			 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
     40			 <0x01000000 0 0x0        0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
     41			 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
     42			 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
     43
     44		clocks = <&tegra_car TEGRA124_CLK_PCIE>,
     45			 <&tegra_car TEGRA124_CLK_AFI>,
     46			 <&tegra_car TEGRA124_CLK_PLL_E>,
     47			 <&tegra_car TEGRA124_CLK_CML0>;
     48		clock-names = "pex", "afi", "pll_e", "cml";
     49		resets = <&tegra_car 70>,
     50			 <&tegra_car 72>,
     51			 <&tegra_car 74>;
     52		reset-names = "pex", "afi", "pcie_x";
     53		status = "disabled";
     54
     55		pci@1,0 {
     56			device_type = "pci";
     57			assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
     58			reg = <0x000800 0 0 0 0>;
     59			bus-range = <0x00 0xff>;
     60			status = "disabled";
     61
     62			#address-cells = <3>;
     63			#size-cells = <2>;
     64			ranges;
     65
     66			nvidia,num-lanes = <2>;
     67		};
     68
     69		pci@2,0 {
     70			device_type = "pci";
     71			assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
     72			reg = <0x001000 0 0 0 0>;
     73			bus-range = <0x00 0xff>;
     74			status = "disabled";
     75
     76			#address-cells = <3>;
     77			#size-cells = <2>;
     78			ranges;
     79
     80			nvidia,num-lanes = <1>;
     81		};
     82	};
     83
     84	host1x@50000000 {
     85		compatible = "nvidia,tegra132-host1x",
     86			     "nvidia,tegra124-host1x";
     87		reg = <0x0 0x50000000 0x0 0x00034000>;
     88		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
     89			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
     90		interrupt-names = "syncpt", "host1x";
     91		clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
     92		clock-names = "host1x";
     93		resets = <&tegra_car 28>;
     94		reset-names = "host1x";
     95
     96		#address-cells = <2>;
     97		#size-cells = <2>;
     98
     99		ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
    100
    101		dc@54200000 {
    102			compatible = "nvidia,tegra124-dc";
    103			reg = <0x0 0x54200000 0x0 0x00040000>;
    104			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
    105			clocks = <&tegra_car TEGRA124_CLK_DISP1>;
    106			clock-names = "dc";
    107			resets = <&tegra_car 27>;
    108			reset-names = "dc";
    109
    110			iommus = <&mc TEGRA_SWGROUP_DC>;
    111
    112			nvidia,head = <0>;
    113		};
    114
    115		dc@54240000 {
    116			compatible = "nvidia,tegra124-dc";
    117			reg = <0x0 0x54240000 0x0 0x00040000>;
    118			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
    119			clocks = <&tegra_car TEGRA124_CLK_DISP2>;
    120			clock-names = "dc";
    121			resets = <&tegra_car 26>;
    122			reset-names = "dc";
    123
    124			iommus = <&mc TEGRA_SWGROUP_DCB>;
    125
    126			nvidia,head = <1>;
    127		};
    128
    129		hdmi@54280000 {
    130			compatible = "nvidia,tegra124-hdmi";
    131			reg = <0x0 0x54280000 0x0 0x00040000>;
    132			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
    133			clocks = <&tegra_car TEGRA124_CLK_HDMI>,
    134				 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
    135			clock-names = "hdmi", "parent";
    136			resets = <&tegra_car 51>;
    137			reset-names = "hdmi";
    138			status = "disabled";
    139		};
    140
    141		sor@54540000 {
    142			compatible = "nvidia,tegra124-sor";
    143			reg = <0x0 0x54540000 0x0 0x00040000>;
    144			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
    145			clocks = <&tegra_car TEGRA124_CLK_SOR0>,
    146				 <&tegra_car TEGRA124_CLK_SOR0_OUT>,
    147				 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
    148				 <&tegra_car TEGRA124_CLK_PLL_DP>,
    149				 <&tegra_car TEGRA124_CLK_CLK_M>;
    150			clock-names = "sor", "out", "parent", "dp", "safe";
    151			resets = <&tegra_car 182>;
    152			reset-names = "sor";
    153			status = "disabled";
    154		};
    155
    156		dpaux: dpaux@545c0000 {
    157			compatible = "nvidia,tegra124-dpaux";
    158			reg = <0x0 0x545c0000 0x0 0x00040000>;
    159			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
    160			clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
    161				 <&tegra_car TEGRA124_CLK_PLL_DP>;
    162			clock-names = "dpaux", "parent";
    163			resets = <&tegra_car 181>;
    164			reset-names = "dpaux";
    165			status = "disabled";
    166
    167			i2c-bus {
    168				#address-cells = <1>;
    169				#size-cells = <0>;
    170			};
    171		};
    172	};
    173
    174	gic: interrupt-controller@50041000 {
    175		compatible = "arm,cortex-a15-gic";
    176		#interrupt-cells = <3>;
    177		interrupt-controller;
    178		reg = <0x0 0x50041000 0x0 0x1000>,
    179		      <0x0 0x50042000 0x0 0x2000>,
    180		      <0x0 0x50044000 0x0 0x2000>,
    181		      <0x0 0x50046000 0x0 0x2000>;
    182		interrupts = <GIC_PPI 9
    183			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
    184		interrupt-parent = <&gic>;
    185	};
    186
    187	gpu@57000000 {
    188		compatible = "nvidia,gk20a";
    189		reg = <0x0 0x57000000 0x0 0x01000000>,
    190		      <0x0 0x58000000 0x0 0x01000000>;
    191		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
    192			     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
    193		interrupt-names = "stall", "nonstall";
    194		clocks = <&tegra_car TEGRA124_CLK_GPU>,
    195			 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
    196		clock-names = "gpu", "pwr";
    197		resets = <&tegra_car 184>;
    198		reset-names = "gpu";
    199		status = "disabled";
    200	};
    201
    202	lic: interrupt-controller@60004000 {
    203		compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
    204		reg = <0x0 0x60004000 0x0 0x100>,
    205		      <0x0 0x60004100 0x0 0x100>,
    206		      <0x0 0x60004200 0x0 0x100>,
    207		      <0x0 0x60004300 0x0 0x100>,
    208		      <0x0 0x60004400 0x0 0x100>;
    209		interrupt-controller;
    210		#interrupt-cells = <3>;
    211		interrupt-parent = <&gic>;
    212	};
    213
    214	timer@60005000 {
    215		compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer";
    216		reg = <0x0 0x60005000 0x0 0x400>;
    217		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
    218			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
    219			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
    220			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
    221			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
    222			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
    223		clocks = <&tegra_car TEGRA124_CLK_TIMER>;
    224		clock-names = "timer";
    225	};
    226
    227	tegra_car: clock@60006000 {
    228		compatible = "nvidia,tegra132-car";
    229		reg = <0x0 0x60006000 0x0 0x1000>;
    230		#clock-cells = <1>;
    231		#reset-cells = <1>;
    232		nvidia,external-memory-controller = <&emc>;
    233	};
    234
    235	flow-controller@60007000 {
    236		compatible = "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl";
    237		reg = <0x0 0x60007000 0x0 0x1000>;
    238	};
    239
    240	actmon@6000c800 {
    241		compatible = "nvidia,tegra124-actmon";
    242		reg = <0x0 0x6000c800 0x0 0x400>;
    243		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
    244		clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
    245			 <&tegra_car TEGRA124_CLK_EMC>;
    246		clock-names = "actmon", "emc";
    247		resets = <&tegra_car 119>;
    248		reset-names = "actmon";
    249		operating-points-v2 = <&emc_bw_dfs_opp_table>;
    250		interconnects = <&mc TEGRA124_MC_MPCORER &emc>;
    251		interconnect-names = "cpu-read";
    252		#cooling-cells = <2>;
    253	};
    254
    255	gpio: gpio@6000d000 {
    256		compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
    257		reg = <0x0 0x6000d000 0x0 0x1000>;
    258		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
    259			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
    260			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
    261			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
    262			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
    263			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
    264			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
    265			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
    266		#gpio-cells = <2>;
    267		gpio-controller;
    268		#interrupt-cells = <2>;
    269		interrupt-controller;
    270	};
    271
    272	apbdma: dma@60020000 {
    273		compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
    274		reg = <0x0 0x60020000 0x0 0x1400>;
    275		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
    276			     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
    277			     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
    278			     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
    279			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
    280			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
    281			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
    282			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
    283			     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
    284			     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
    285			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
    286			     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
    287			     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
    288			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
    289			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
    290			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
    291			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
    292			     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
    293			     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
    294			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
    295			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
    296			     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
    297			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
    298			     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
    299			     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
    300			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
    301			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
    302			     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
    303			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
    304			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
    305			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
    306			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
    307		clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
    308		clock-names = "dma";
    309		resets = <&tegra_car 34>;
    310		reset-names = "dma";
    311		#dma-cells = <1>;
    312	};
    313
    314	apbmisc@70000800 {
    315		compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
    316		reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
    317		      <0x0 0x7000e864 0x0 0x04>;   /* Strapping options */
    318	};
    319
    320	pinmux: pinmux@70000868 {
    321		compatible = "nvidia,tegra124-pinmux";
    322		reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
    323		      <0x0 0x70003000 0x0 0x434>, /* Mux registers */
    324		      <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
    325	};
    326
    327	/*
    328	 * There are two serial driver i.e. 8250 based simple serial
    329	 * driver and APB DMA based serial driver for higher baudrate
    330	 * and performance. To enable the 8250 based driver, the compatible
    331	 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
    332	 * the APB DMA based serial driver, the compatible is
    333	 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
    334	 */
    335	uarta: serial@70006000 {
    336		compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
    337		reg = <0x0 0x70006000 0x0 0x40>;
    338		reg-shift = <2>;
    339		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
    340		clocks = <&tegra_car TEGRA124_CLK_UARTA>;
    341		clock-names = "serial";
    342		resets = <&tegra_car 6>;
    343		reset-names = "serial";
    344		dmas = <&apbdma 8>, <&apbdma 8>;
    345		dma-names = "rx", "tx";
    346		status = "disabled";
    347	};
    348
    349	uartb: serial@70006040 {
    350		compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
    351		reg = <0x0 0x70006040 0x0 0x40>;
    352		reg-shift = <2>;
    353		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
    354		clocks = <&tegra_car TEGRA124_CLK_UARTB>;
    355		clock-names = "serial";
    356		resets = <&tegra_car 7>;
    357		reset-names = "serial";
    358		dmas = <&apbdma 9>, <&apbdma 9>;
    359		dma-names = "rx", "tx";
    360		status = "disabled";
    361	};
    362
    363	uartc: serial@70006200 {
    364		compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
    365		reg = <0x0 0x70006200 0x0 0x40>;
    366		reg-shift = <2>;
    367		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
    368		clocks = <&tegra_car TEGRA124_CLK_UARTC>;
    369		clock-names = "serial";
    370		resets = <&tegra_car 55>;
    371		reset-names = "serial";
    372		dmas = <&apbdma 10>, <&apbdma 10>;
    373		dma-names = "rx", "tx";
    374		status = "disabled";
    375	};
    376
    377	uartd: serial@70006300 {
    378		compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
    379		reg = <0x0 0x70006300 0x0 0x40>;
    380		reg-shift = <2>;
    381		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
    382		clocks = <&tegra_car TEGRA124_CLK_UARTD>;
    383		clock-names = "serial";
    384		resets = <&tegra_car 65>;
    385		reset-names = "serial";
    386		dmas = <&apbdma 19>, <&apbdma 19>;
    387		dma-names = "rx", "tx";
    388		status = "disabled";
    389	};
    390
    391	pwm: pwm@7000a000 {
    392		compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
    393		reg = <0x0 0x7000a000 0x0 0x100>;
    394		#pwm-cells = <2>;
    395		clocks = <&tegra_car TEGRA124_CLK_PWM>;
    396		clock-names = "pwm";
    397		resets = <&tegra_car 17>;
    398		reset-names = "pwm";
    399		status = "disabled";
    400	};
    401
    402	i2c@7000c000 {
    403		compatible = "nvidia,tegra124-i2c";
    404		reg = <0x0 0x7000c000 0x0 0x100>;
    405		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
    406		#address-cells = <1>;
    407		#size-cells = <0>;
    408		clocks = <&tegra_car TEGRA124_CLK_I2C1>;
    409		clock-names = "div-clk";
    410		resets = <&tegra_car 12>;
    411		reset-names = "i2c";
    412		dmas = <&apbdma 21>, <&apbdma 21>;
    413		dma-names = "rx", "tx";
    414		status = "disabled";
    415	};
    416
    417	i2c@7000c400 {
    418		compatible = "nvidia,tegra124-i2c";
    419		reg = <0x0 0x7000c400 0x0 0x100>;
    420		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
    421		#address-cells = <1>;
    422		#size-cells = <0>;
    423		clocks = <&tegra_car TEGRA124_CLK_I2C2>;
    424		clock-names = "div-clk";
    425		resets = <&tegra_car 54>;
    426		reset-names = "i2c";
    427		dmas = <&apbdma 22>, <&apbdma 22>;
    428		dma-names = "rx", "tx";
    429		status = "disabled";
    430	};
    431
    432	i2c@7000c500 {
    433		compatible = "nvidia,tegra124-i2c";
    434		reg = <0x0 0x7000c500 0x0 0x100>;
    435		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
    436		#address-cells = <1>;
    437		#size-cells = <0>;
    438		clocks = <&tegra_car TEGRA124_CLK_I2C3>;
    439		clock-names = "div-clk";
    440		resets = <&tegra_car 67>;
    441		reset-names = "i2c";
    442		dmas = <&apbdma 23>, <&apbdma 23>;
    443		dma-names = "rx", "tx";
    444		status = "disabled";
    445	};
    446
    447	i2c@7000c700 {
    448		compatible = "nvidia,tegra124-i2c";
    449		reg = <0x0 0x7000c700 0x0 0x100>;
    450		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
    451		#address-cells = <1>;
    452		#size-cells = <0>;
    453		clocks = <&tegra_car TEGRA124_CLK_I2C4>;
    454		clock-names = "div-clk";
    455		resets = <&tegra_car 103>;
    456		reset-names = "i2c";
    457		dmas = <&apbdma 26>, <&apbdma 26>;
    458		dma-names = "rx", "tx";
    459		status = "disabled";
    460	};
    461
    462	i2c@7000d000 {
    463		compatible = "nvidia,tegra124-i2c";
    464		reg = <0x0 0x7000d000 0x0 0x100>;
    465		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
    466		#address-cells = <1>;
    467		#size-cells = <0>;
    468		clocks = <&tegra_car TEGRA124_CLK_I2C5>;
    469		clock-names = "div-clk";
    470		resets = <&tegra_car 47>;
    471		reset-names = "i2c";
    472		dmas = <&apbdma 24>, <&apbdma 24>;
    473		dma-names = "rx", "tx";
    474		status = "disabled";
    475	};
    476
    477	i2c@7000d100 {
    478		compatible = "nvidia,tegra124-i2c";
    479		reg = <0x0 0x7000d100 0x0 0x100>;
    480		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
    481		#address-cells = <1>;
    482		#size-cells = <0>;
    483		clocks = <&tegra_car TEGRA124_CLK_I2C6>;
    484		clock-names = "div-clk";
    485		resets = <&tegra_car 166>;
    486		reset-names = "i2c";
    487		dmas = <&apbdma 30>, <&apbdma 30>;
    488		dma-names = "rx", "tx";
    489		status = "disabled";
    490	};
    491
    492	spi@7000d400 {
    493		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
    494		reg = <0x0 0x7000d400 0x0 0x200>;
    495		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
    496		#address-cells = <1>;
    497		#size-cells = <0>;
    498		clocks = <&tegra_car TEGRA124_CLK_SBC1>;
    499		clock-names = "spi";
    500		resets = <&tegra_car 41>;
    501		reset-names = "spi";
    502		dmas = <&apbdma 15>, <&apbdma 15>;
    503		dma-names = "rx", "tx";
    504		status = "disabled";
    505	};
    506
    507	spi@7000d600 {
    508		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
    509		reg = <0x0 0x7000d600 0x0 0x200>;
    510		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
    511		#address-cells = <1>;
    512		#size-cells = <0>;
    513		clocks = <&tegra_car TEGRA124_CLK_SBC2>;
    514		clock-names = "spi";
    515		resets = <&tegra_car 44>;
    516		reset-names = "spi";
    517		dmas = <&apbdma 16>, <&apbdma 16>;
    518		dma-names = "rx", "tx";
    519		status = "disabled";
    520	};
    521
    522	spi@7000d800 {
    523		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
    524		reg = <0x0 0x7000d800 0x0 0x200>;
    525		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
    526		#address-cells = <1>;
    527		#size-cells = <0>;
    528		clocks = <&tegra_car TEGRA124_CLK_SBC3>;
    529		clock-names = "spi";
    530		resets = <&tegra_car 46>;
    531		reset-names = "spi";
    532		dmas = <&apbdma 17>, <&apbdma 17>;
    533		dma-names = "rx", "tx";
    534		status = "disabled";
    535	};
    536
    537	spi@7000da00 {
    538		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
    539		reg = <0x0 0x7000da00 0x0 0x200>;
    540		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
    541		#address-cells = <1>;
    542		#size-cells = <0>;
    543		clocks = <&tegra_car TEGRA124_CLK_SBC4>;
    544		clock-names = "spi";
    545		resets = <&tegra_car 68>;
    546		reset-names = "spi";
    547		dmas = <&apbdma 18>, <&apbdma 18>;
    548		dma-names = "rx", "tx";
    549		status = "disabled";
    550	};
    551
    552	spi@7000dc00 {
    553		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
    554		reg = <0x0 0x7000dc00 0x0 0x200>;
    555		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
    556		#address-cells = <1>;
    557		#size-cells = <0>;
    558		clocks = <&tegra_car TEGRA124_CLK_SBC5>;
    559		clock-names = "spi";
    560		resets = <&tegra_car 104>;
    561		reset-names = "spi";
    562		dmas = <&apbdma 27>, <&apbdma 27>;
    563		dma-names = "rx", "tx";
    564		status = "disabled";
    565	};
    566
    567	spi@7000de00 {
    568		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
    569		reg = <0x0 0x7000de00 0x0 0x200>;
    570		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
    571		#address-cells = <1>;
    572		#size-cells = <0>;
    573		clocks = <&tegra_car TEGRA124_CLK_SBC6>;
    574		clock-names = "spi";
    575		resets = <&tegra_car 105>;
    576		reset-names = "spi";
    577		dmas = <&apbdma 28>, <&apbdma 28>;
    578		dma-names = "rx", "tx";
    579		status = "disabled";
    580	};
    581
    582	rtc@7000e000 {
    583		compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
    584		reg = <0x0 0x7000e000 0x0 0x100>;
    585		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
    586		clocks = <&tegra_car TEGRA124_CLK_RTC>;
    587		clock-names = "rtc";
    588	};
    589
    590	tegra_pmc: pmc@7000e400 {
    591		compatible = "nvidia,tegra124-pmc";
    592		reg = <0x0 0x7000e400 0x0 0x400>;
    593		clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
    594		clock-names = "pclk", "clk32k_in";
    595		#clock-cells = <1>;
    596	};
    597
    598	fuse@7000f800 {
    599		compatible = "nvidia,tegra124-efuse";
    600		reg = <0x0 0x7000f800 0x0 0x400>;
    601		clocks = <&tegra_car TEGRA124_CLK_FUSE>;
    602		clock-names = "fuse";
    603		resets = <&tegra_car 39>;
    604		reset-names = "fuse";
    605	};
    606
    607	mc: memory-controller@70019000 {
    608		compatible = "nvidia,tegra132-mc";
    609		reg = <0x0 0x70019000 0x0 0x1000>;
    610		clocks = <&tegra_car TEGRA124_CLK_MC>;
    611		clock-names = "mc";
    612
    613		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
    614
    615		#iommu-cells = <1>;
    616		#reset-cells = <1>;
    617		#interconnect-cells = <1>;
    618	};
    619
    620	emc: external-memory-controller@7001b000 {
    621		compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc";
    622		reg = <0x0 0x7001b000 0x0 0x1000>;
    623		clocks = <&tegra_car TEGRA124_CLK_EMC>;
    624		clock-names = "emc";
    625
    626		nvidia,memory-controller = <&mc>;
    627		operating-points-v2 = <&emc_icc_dvfs_opp_table>;
    628
    629		#interconnect-cells = <0>;
    630	};
    631
    632	sata@70020000 {
    633		compatible = "nvidia,tegra124-ahci";
    634		reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
    635		      <0x0 0x70020000 0x0 0x7000>; /* SATA */
    636		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
    637		clocks = <&tegra_car TEGRA124_CLK_SATA>,
    638			 <&tegra_car TEGRA124_CLK_SATA_OOB>;
    639		clock-names = "sata", "sata-oob";
    640		resets = <&tegra_car 124>,
    641			 <&tegra_car 129>,
    642			 <&tegra_car 123>;
    643		reset-names = "sata", "sata-cold", "sata-oob";
    644		status = "disabled";
    645	};
    646
    647	hda@70030000 {
    648		compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda",
    649			     "nvidia,tegra30-hda";
    650		reg = <0x0 0x70030000 0x0 0x10000>;
    651		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
    652		clocks = <&tegra_car TEGRA124_CLK_HDA>,
    653		         <&tegra_car TEGRA124_CLK_HDA2HDMI>,
    654			 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
    655		clock-names = "hda", "hda2hdmi", "hda2codec_2x";
    656		resets = <&tegra_car 125>, /* hda */
    657			 <&tegra_car 128>, /* hda2hdmi */
    658			 <&tegra_car 111>; /* hda2codec_2x */
    659		reset-names = "hda", "hda2hdmi", "hda2codec_2x";
    660		status = "disabled";
    661	};
    662
    663	usb@70090000 {
    664		compatible = "nvidia,tegra132-xusb", "nvidia,tegra124-xusb";
    665		reg = <0x0 0x70090000 0x0 0x8000>,
    666		      <0x0 0x70098000 0x0 0x1000>,
    667		      <0x0 0x70099000 0x0 0x1000>;
    668		reg-names = "hcd", "fpci", "ipfs";
    669
    670		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
    671			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
    672
    673		clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
    674			 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
    675			 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
    676			 <&tegra_car TEGRA124_CLK_XUSB_SS>,
    677			 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
    678			 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
    679			 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
    680			 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
    681			 <&tegra_car TEGRA124_CLK_PLL_U_480M>,
    682			 <&tegra_car TEGRA124_CLK_CLK_M>,
    683			 <&tegra_car TEGRA124_CLK_PLL_E>;
    684		clock-names = "xusb_host", "xusb_host_src",
    685			      "xusb_falcon_src", "xusb_ss",
    686			      "xusb_ss_div2", "xusb_ss_src",
    687			      "xusb_hs_src", "xusb_fs_src",
    688			      "pll_u_480m", "clk_m", "pll_e";
    689		resets = <&tegra_car 89>, <&tegra_car 156>,
    690			 <&tegra_car 143>;
    691		reset-names = "xusb_host", "xusb_ss", "xusb_src";
    692
    693		nvidia,xusb-padctl = <&padctl>;
    694
    695		status = "disabled";
    696	};
    697
    698	padctl: padctl@7009f000 {
    699		compatible = "nvidia,tegra132-xusb-padctl",
    700			     "nvidia,tegra124-xusb-padctl";
    701		reg = <0x0 0x7009f000 0x0 0x1000>;
    702		resets = <&tegra_car 142>;
    703		reset-names = "padctl";
    704
    705		pads {
    706			usb2 {
    707				status = "disabled";
    708
    709				lanes {
    710					usb2-0 {
    711						status = "disabled";
    712						#phy-cells = <0>;
    713					};
    714
    715					usb2-1 {
    716						status = "disabled";
    717						#phy-cells = <0>;
    718					};
    719
    720					usb2-2 {
    721						status = "disabled";
    722						#phy-cells = <0>;
    723					};
    724				};
    725			};
    726
    727			ulpi {
    728				status = "disabled";
    729
    730				lanes {
    731					ulpi-0 {
    732						status = "disabled";
    733						#phy-cells = <0>;
    734					};
    735				};
    736			};
    737
    738			hsic {
    739				status = "disabled";
    740
    741				lanes {
    742					hsic-0 {
    743						status = "disabled";
    744						#phy-cells = <0>;
    745					};
    746
    747					hsic-1 {
    748						status = "disabled";
    749						#phy-cells = <0>;
    750					};
    751				};
    752			};
    753
    754			pcie {
    755				status = "disabled";
    756
    757				lanes {
    758					pcie-0 {
    759						status = "disabled";
    760						#phy-cells = <0>;
    761					};
    762
    763					pcie-1 {
    764						status = "disabled";
    765						#phy-cells = <0>;
    766					};
    767
    768					pcie-2 {
    769						status = "disabled";
    770						#phy-cells = <0>;
    771					};
    772
    773					pcie-3 {
    774						status = "disabled";
    775						#phy-cells = <0>;
    776					};
    777
    778					pcie-4 {
    779						status = "disabled";
    780						#phy-cells = <0>;
    781					};
    782				};
    783			};
    784
    785			sata {
    786				status = "disabled";
    787
    788				lanes {
    789					sata-0 {
    790						status = "disabled";
    791						#phy-cells = <0>;
    792					};
    793				};
    794			};
    795		};
    796
    797		ports {
    798			usb2-0 {
    799				status = "disabled";
    800			};
    801
    802			usb2-1 {
    803				status = "disabled";
    804			};
    805
    806			usb2-2 {
    807				status = "disabled";
    808			};
    809
    810			hsic-0 {
    811				status = "disabled";
    812			};
    813
    814			hsic-1 {
    815				status = "disabled";
    816			};
    817
    818			usb3-0 {
    819				status = "disabled";
    820			};
    821
    822			usb3-1 {
    823				status = "disabled";
    824			};
    825		};
    826	};
    827
    828	mmc@700b0000 {
    829		compatible = "nvidia,tegra124-sdhci";
    830		reg = <0x0 0x700b0000 0x0 0x200>;
    831		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
    832		clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
    833		clock-names = "sdhci";
    834		resets = <&tegra_car 14>;
    835		reset-names = "sdhci";
    836		status = "disabled";
    837	};
    838
    839	mmc@700b0200 {
    840		compatible = "nvidia,tegra124-sdhci";
    841		reg = <0x0 0x700b0200 0x0 0x200>;
    842		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
    843		clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
    844		clock-names = "sdhci";
    845		resets = <&tegra_car 9>;
    846		reset-names = "sdhci";
    847		status = "disabled";
    848	};
    849
    850	mmc@700b0400 {
    851		compatible = "nvidia,tegra124-sdhci";
    852		reg = <0x0 0x700b0400 0x0 0x200>;
    853		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
    854		clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
    855		clock-names = "sdhci";
    856		resets = <&tegra_car 69>;
    857		reset-names = "sdhci";
    858		status = "disabled";
    859	};
    860
    861	mmc@700b0600 {
    862		compatible = "nvidia,tegra124-sdhci";
    863		reg = <0x0 0x700b0600 0x0 0x200>;
    864		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
    865		clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
    866		clock-names = "sdhci";
    867		resets = <&tegra_car 15>;
    868		reset-names = "sdhci";
    869		status = "disabled";
    870	};
    871
    872	soctherm: thermal-sensor@700e2000 {
    873		compatible = "nvidia,tegra132-soctherm";
    874		reg = <0x0 0x700e2000 0x0 0x600>, /* 0: SOC_THERM reg_base */
    875		      <0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */
    876		reg-names = "soctherm-reg", "ccroc-reg";
    877		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
    878			     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
    879		interrupt-names = "thermal", "edp";
    880		clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
    881		         <&tegra_car TEGRA124_CLK_SOC_THERM>;
    882		clock-names = "tsensor", "soctherm";
    883		resets = <&tegra_car 78>;
    884		reset-names = "soctherm";
    885		#thermal-sensor-cells = <1>;
    886
    887		throttle-cfgs {
    888			throttle_heavy: heavy {
    889				nvidia,priority = <100>;
    890				nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
    891
    892				#cooling-cells = <2>;
    893			};
    894		};
    895	};
    896
    897	thermal-zones {
    898		cpu-thermal {
    899			polling-delay-passive = <1000>;
    900			polling-delay = <0>;
    901
    902			thermal-sensors =
    903				<&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
    904
    905			trips {
    906				cpu_shutdown_trip {
    907					temperature = <105000>;
    908					hysteresis = <1000>;
    909					type = "critical";
    910				};
    911
    912				cpu_throttle_trip: throttle-trip {
    913					temperature = <102000>;
    914					hysteresis = <1000>;
    915					type = "hot";
    916				};
    917			};
    918
    919			cooling-maps {
    920				map0 {
    921					trip = <&cpu_throttle_trip>;
    922					cooling-device = <&throttle_heavy 1 1>;
    923				};
    924			};
    925		};
    926
    927		mem-thermal {
    928			polling-delay-passive = <0>;
    929			polling-delay = <0>;
    930
    931			thermal-sensors =
    932				<&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
    933
    934			trips {
    935				mem_shutdown_trip {
    936					temperature = <101000>;
    937					hysteresis = <1000>;
    938					type = "critical";
    939				};
    940				mem_throttle_trip {
    941					temperature = <99000>;
    942					hysteresis = <1000>;
    943					type = "hot";
    944				};
    945			};
    946
    947			cooling-maps {
    948				/*
    949				 * There are currently no cooling maps,
    950				 * because there are no cooling devices.
    951				 */
    952			};
    953		};
    954
    955		gpu-thermal {
    956			polling-delay-passive = <1000>;
    957			polling-delay = <0>;
    958
    959			thermal-sensors =
    960				<&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
    961
    962			trips {
    963				gpu_shutdown_trip {
    964					temperature = <101000>;
    965					hysteresis = <1000>;
    966					type = "critical";
    967				};
    968
    969				gpu_throttle_trip: throttle-trip {
    970					temperature = <99000>;
    971					hysteresis = <1000>;
    972					type = "hot";
    973				};
    974			};
    975
    976			cooling-maps {
    977				map0 {
    978					trip = <&gpu_throttle_trip>;
    979					cooling-device = <&throttle_heavy 1 1>;
    980				};
    981			};
    982		};
    983
    984		pllx-thermal {
    985			polling-delay-passive = <0>;
    986			polling-delay = <0>;
    987
    988			thermal-sensors =
    989				<&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
    990
    991			trips {
    992				pllx_shutdown_trip {
    993					temperature = <105000>;
    994					hysteresis = <1000>;
    995					type = "critical";
    996				};
    997				pllx_throttle_trip {
    998					temperature = <99000>;
    999					hysteresis = <1000>;
   1000					type = "hot";
   1001				};
   1002			};
   1003
   1004			cooling-maps {
   1005				/*
   1006				 * There are currently no cooling maps,
   1007				 * because there are no cooling devices.
   1008				 */
   1009			};
   1010		};
   1011	};
   1012
   1013	ahub@70300000 {
   1014		compatible = "nvidia,tegra124-ahub";
   1015		reg = <0x0 0x70300000 0x0 0x200>,
   1016		      <0x0 0x70300800 0x0 0x800>,
   1017		      <0x0 0x70300200 0x0 0x600>;
   1018		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
   1019		clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
   1020			 <&tegra_car TEGRA124_CLK_APBIF>;
   1021		clock-names = "d_audio", "apbif";
   1022		resets = <&tegra_car 106>, /* d_audio */
   1023			 <&tegra_car 107>, /* apbif */
   1024			 <&tegra_car 30>,  /* i2s0 */
   1025			 <&tegra_car 11>,  /* i2s1 */
   1026			 <&tegra_car 18>,  /* i2s2 */
   1027			 <&tegra_car 101>, /* i2s3 */
   1028			 <&tegra_car 102>, /* i2s4 */
   1029			 <&tegra_car 108>, /* dam0 */
   1030			 <&tegra_car 109>, /* dam1 */
   1031			 <&tegra_car 110>, /* dam2 */
   1032			 <&tegra_car 10>,  /* spdif */
   1033			 <&tegra_car 153>, /* amx */
   1034			 <&tegra_car 185>, /* amx1 */
   1035			 <&tegra_car 154>, /* adx */
   1036			 <&tegra_car 180>, /* adx1 */
   1037			 <&tegra_car 186>, /* afc0 */
   1038			 <&tegra_car 187>, /* afc1 */
   1039			 <&tegra_car 188>, /* afc2 */
   1040			 <&tegra_car 189>, /* afc3 */
   1041			 <&tegra_car 190>, /* afc4 */
   1042			 <&tegra_car 191>; /* afc5 */
   1043		reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
   1044			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
   1045			      "spdif", "amx", "amx1", "adx", "adx1",
   1046			      "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
   1047		dmas = <&apbdma 1>, <&apbdma 1>,
   1048		       <&apbdma 2>, <&apbdma 2>,
   1049		       <&apbdma 3>, <&apbdma 3>,
   1050		       <&apbdma 4>, <&apbdma 4>,
   1051		       <&apbdma 6>, <&apbdma 6>,
   1052		       <&apbdma 7>, <&apbdma 7>,
   1053		       <&apbdma 12>, <&apbdma 12>,
   1054		       <&apbdma 13>, <&apbdma 13>,
   1055		       <&apbdma 14>, <&apbdma 14>,
   1056		       <&apbdma 29>, <&apbdma 29>;
   1057		dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
   1058			    "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
   1059			    "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
   1060			    "rx9", "tx9";
   1061		ranges;
   1062		#address-cells = <2>;
   1063		#size-cells = <2>;
   1064
   1065		tegra_i2s0: i2s@70301000 {
   1066			compatible = "nvidia,tegra124-i2s";
   1067			reg = <0x0 0x70301000 0x0 0x100>;
   1068			nvidia,ahub-cif-ids = <4 4>;
   1069			clocks = <&tegra_car TEGRA124_CLK_I2S0>;
   1070			clock-names = "i2s";
   1071			resets = <&tegra_car 30>;
   1072			reset-names = "i2s";
   1073			status = "disabled";
   1074		};
   1075
   1076		tegra_i2s1: i2s@70301100 {
   1077			compatible = "nvidia,tegra124-i2s";
   1078			reg = <0x0 0x70301100 0x0 0x100>;
   1079			nvidia,ahub-cif-ids = <5 5>;
   1080			clocks = <&tegra_car TEGRA124_CLK_I2S1>;
   1081			clock-names = "i2s";
   1082			resets = <&tegra_car 11>;
   1083			reset-names = "i2s";
   1084			status = "disabled";
   1085		};
   1086
   1087		tegra_i2s2: i2s@70301200 {
   1088			compatible = "nvidia,tegra124-i2s";
   1089			reg = <0x0 0x70301200 0x0 0x100>;
   1090			nvidia,ahub-cif-ids = <6 6>;
   1091			clocks = <&tegra_car TEGRA124_CLK_I2S2>;
   1092			clock-names = "i2s";
   1093			resets = <&tegra_car 18>;
   1094			reset-names = "i2s";
   1095			status = "disabled";
   1096		};
   1097
   1098		tegra_i2s3: i2s@70301300 {
   1099			compatible = "nvidia,tegra124-i2s";
   1100			reg = <0x0 0x70301300 0x0 0x100>;
   1101			nvidia,ahub-cif-ids = <7 7>;
   1102			clocks = <&tegra_car TEGRA124_CLK_I2S3>;
   1103			clock-names = "i2s";
   1104			resets = <&tegra_car 101>;
   1105			reset-names = "i2s";
   1106			status = "disabled";
   1107		};
   1108
   1109		tegra_i2s4: i2s@70301400 {
   1110			compatible = "nvidia,tegra124-i2s";
   1111			reg = <0x0 0x70301400 0x0 0x100>;
   1112			nvidia,ahub-cif-ids = <8 8>;
   1113			clocks = <&tegra_car TEGRA124_CLK_I2S4>;
   1114			clock-names = "i2s";
   1115			resets = <&tegra_car 102>;
   1116			reset-names = "i2s";
   1117			status = "disabled";
   1118		};
   1119	};
   1120
   1121	usb@7d000000 {
   1122		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
   1123		reg = <0x0 0x7d000000 0x0 0x4000>;
   1124		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
   1125		phy_type = "utmi";
   1126		clocks = <&tegra_car TEGRA124_CLK_USBD>;
   1127		clock-names = "usb";
   1128		resets = <&tegra_car 22>;
   1129		reset-names = "usb";
   1130		nvidia,phy = <&phy1>;
   1131		status = "disabled";
   1132	};
   1133
   1134	phy1: usb-phy@7d000000 {
   1135		compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
   1136		reg = <0x0 0x7d000000 0x0 0x4000>,
   1137		      <0x0 0x7d000000 0x0 0x4000>;
   1138		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
   1139		phy_type = "utmi";
   1140		clocks = <&tegra_car TEGRA124_CLK_USBD>,
   1141			 <&tegra_car TEGRA124_CLK_PLL_U>,
   1142			 <&tegra_car TEGRA124_CLK_USBD>;
   1143		clock-names = "reg", "pll_u", "utmi-pads";
   1144		resets = <&tegra_car 22>, <&tegra_car 22>;
   1145		reset-names = "usb", "utmi-pads";
   1146		#phy-cells = <0>;
   1147		nvidia,hssync-start-delay = <0>;
   1148		nvidia,idle-wait-delay = <17>;
   1149		nvidia,elastic-limit = <16>;
   1150		nvidia,term-range-adj = <6>;
   1151		nvidia,xcvr-setup = <9>;
   1152		nvidia,xcvr-lsfslew = <0>;
   1153		nvidia,xcvr-lsrslew = <3>;
   1154		nvidia,hssquelch-level = <2>;
   1155		nvidia,hsdiscon-level = <5>;
   1156		nvidia,xcvr-hsslew = <12>;
   1157		nvidia,has-utmi-pad-registers;
   1158		nvidia,pmc = <&tegra_pmc 0>;
   1159		status = "disabled";
   1160	};
   1161
   1162	usb@7d004000 {
   1163		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
   1164		reg = <0x0 0x7d004000 0x0 0x4000>;
   1165		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
   1166		phy_type = "utmi";
   1167		clocks = <&tegra_car TEGRA124_CLK_USB2>;
   1168		clock-names = "usb";
   1169		resets = <&tegra_car 58>;
   1170		reset-names = "usb";
   1171		nvidia,phy = <&phy2>;
   1172		status = "disabled";
   1173	};
   1174
   1175	phy2: usb-phy@7d004000 {
   1176		compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
   1177		reg = <0x0 0x7d004000 0x0 0x4000>,
   1178		      <0x0 0x7d000000 0x0 0x4000>;
   1179		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
   1180		phy_type = "utmi";
   1181		clocks = <&tegra_car TEGRA124_CLK_USB2>,
   1182			 <&tegra_car TEGRA124_CLK_PLL_U>,
   1183			 <&tegra_car TEGRA124_CLK_USBD>;
   1184		clock-names = "reg", "pll_u", "utmi-pads";
   1185		resets = <&tegra_car 58>, <&tegra_car 22>;
   1186		reset-names = "usb", "utmi-pads";
   1187		#phy-cells = <0>;
   1188		nvidia,hssync-start-delay = <0>;
   1189		nvidia,idle-wait-delay = <17>;
   1190		nvidia,elastic-limit = <16>;
   1191		nvidia,term-range-adj = <6>;
   1192		nvidia,xcvr-setup = <9>;
   1193		nvidia,xcvr-lsfslew = <0>;
   1194		nvidia,xcvr-lsrslew = <3>;
   1195		nvidia,hssquelch-level = <2>;
   1196		nvidia,hsdiscon-level = <5>;
   1197		nvidia,xcvr-hsslew = <12>;
   1198		nvidia,pmc = <&tegra_pmc 1>;
   1199		status = "disabled";
   1200	};
   1201
   1202	usb@7d008000 {
   1203		compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
   1204		reg = <0x0 0x7d008000 0x0 0x4000>;
   1205		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
   1206		phy_type = "utmi";
   1207		clocks = <&tegra_car TEGRA124_CLK_USB3>;
   1208		clock-names = "usb";
   1209		resets = <&tegra_car 59>;
   1210		reset-names = "usb";
   1211		nvidia,phy = <&phy3>;
   1212		status = "disabled";
   1213	};
   1214
   1215	phy3: usb-phy@7d008000 {
   1216		compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
   1217		reg = <0x0 0x7d008000 0x0 0x4000>,
   1218		      <0x0 0x7d000000 0x0 0x4000>;
   1219		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
   1220		phy_type = "utmi";
   1221		clocks = <&tegra_car TEGRA124_CLK_USB3>,
   1222			 <&tegra_car TEGRA124_CLK_PLL_U>,
   1223			 <&tegra_car TEGRA124_CLK_USBD>;
   1224		clock-names = "reg", "pll_u", "utmi-pads";
   1225		resets = <&tegra_car 59>, <&tegra_car 22>;
   1226		reset-names = "usb", "utmi-pads";
   1227		#phy-cells = <0>;
   1228		nvidia,hssync-start-delay = <0>;
   1229		nvidia,idle-wait-delay = <17>;
   1230		nvidia,elastic-limit = <16>;
   1231		nvidia,term-range-adj = <6>;
   1232		nvidia,xcvr-setup = <9>;
   1233		nvidia,xcvr-lsfslew = <0>;
   1234		nvidia,xcvr-lsrslew = <3>;
   1235		nvidia,hssquelch-level = <2>;
   1236		nvidia,hsdiscon-level = <5>;
   1237		nvidia,xcvr-hsslew = <12>;
   1238		nvidia,pmc = <&tegra_pmc 2>;
   1239		status = "disabled";
   1240	};
   1241
   1242	cpus {
   1243		#address-cells = <1>;
   1244		#size-cells = <0>;
   1245
   1246		cpu@0 {
   1247			device_type = "cpu";
   1248			compatible = "nvidia,tegra132-denver";
   1249			reg = <0>;
   1250		};
   1251
   1252		cpu@1 {
   1253			device_type = "cpu";
   1254			compatible = "nvidia,tegra132-denver";
   1255			reg = <1>;
   1256		};
   1257	};
   1258
   1259	timer {
   1260		compatible = "arm,armv7-timer";
   1261		interrupts = <GIC_PPI 13
   1262				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
   1263			     <GIC_PPI 14
   1264				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
   1265			     <GIC_PPI 11
   1266				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
   1267			     <GIC_PPI 10
   1268				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
   1269		interrupt-parent = <&gic>;
   1270	};
   1271};