tegra210-p2371-2180.dts (22984B)
1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include "tegra210-p2180.dtsi" 5#include "tegra210-p2597.dtsi" 6 7/ { 8 model = "NVIDIA Jetson TX1 Developer Kit"; 9 compatible = "nvidia,p2371-2180", "nvidia,tegra210"; 10 11 pcie@1003000 { 12 status = "okay"; 13 14 hvddio-pex-supply = <&vdd_1v8>; 15 dvddio-pex-supply = <&vdd_pex_1v05>; 16 vddio-pex-ctl-supply = <&vdd_1v8>; 17 18 pci@1,0 { 19 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, 20 <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, 21 <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>, 22 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>; 23 phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3"; 24 status = "okay"; 25 }; 26 27 pci@2,0 { 28 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>; 29 phy-names = "pcie-0"; 30 status = "okay"; 31 }; 32 }; 33 34 host1x@50000000 { 35 dsi@54300000 { 36 status = "okay"; 37 38 avdd-dsi-csi-supply = <&vdd_dsi_csi>; 39 40 panel@0 { 41 compatible = "auo,b080uan01"; 42 reg = <0>; 43 44 enable-gpios = <&gpio TEGRA_GPIO(V, 2) 45 GPIO_ACTIVE_HIGH>; 46 power-supply = <&vdd_5v0_io>; 47 backlight = <&backlight>; 48 }; 49 }; 50 }; 51 52 i2c@7000c400 { 53 backlight: backlight@2c { 54 compatible = "ti,lp8557"; 55 reg = <0x2c>; 56 power-supply = <&vdd_3v3_sys>; 57 58 dev-ctrl = /bits/ 8 <0x80>; 59 init-brt = /bits/ 8 <0xff>; 60 61 pwm-period = <29334>; 62 63 pwms = <&pwm 0 29334>; 64 pwm-names = "lp8557"; 65 66 /* 3 LED string */ 67 rom_14h { 68 rom-addr = /bits/ 8 <0x14>; 69 rom-val = /bits/ 8 <0x87>; 70 }; 71 72 /* boost frequency 1 MHz */ 73 rom_13h { 74 rom-addr = /bits/ 8 <0x13>; 75 rom-val = /bits/ 8 <0x01>; 76 }; 77 }; 78 }; 79 80 i2c@7000c500 { 81 /* carrier board ID EEPROM */ 82 eeprom@57 { 83 compatible = "atmel,24c02"; 84 reg = <0x57>; 85 86 label = "system"; 87 vcc-supply = <&vdd_1v8>; 88 address-width = <8>; 89 pagesize = <8>; 90 size = <256>; 91 read-only; 92 }; 93 }; 94 95 clock@70110000 { 96 status = "okay"; 97 98 nvidia,cf = <6>; 99 nvidia,ci = <0>; 100 nvidia,cg = <2>; 101 nvidia,droop-ctrl = <0x00000f00>; 102 nvidia,force-mode = <1>; 103 nvidia,sample-rate = <25000>; 104 105 nvidia,pwm-min-microvolts = <708000>; 106 nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */ 107 nvidia,pwm-to-pmic; 108 nvidia,pwm-tristate-microvolts = <1000000>; 109 nvidia,pwm-voltage-step-microvolts = <19200>; 110 111 pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable"; 112 pinctrl-0 = <&dvfs_pwm_active_state>; 113 pinctrl-1 = <&dvfs_pwm_inactive_state>; 114 }; 115 116 aconnect@702c0000 { 117 status = "okay"; 118 119 dma-controller@702e2000 { 120 status = "okay"; 121 }; 122 123 interrupt-controller@702f9000 { 124 status = "okay"; 125 }; 126 127 ahub@702d0800 { 128 status = "okay"; 129 130 admaif@702d0000 { 131 status = "okay"; 132 }; 133 134 i2s@702d1000 { 135 status = "okay"; 136 137 ports { 138 #address-cells = <1>; 139 #size-cells = <0>; 140 141 port@0 { 142 reg = <0>; 143 144 i2s1_cif_ep: endpoint { 145 remote-endpoint = <&xbar_i2s1_ep>; 146 }; 147 }; 148 149 i2s1_port: port@1 { 150 reg = <1>; 151 152 i2s1_dap_ep: endpoint { 153 dai-format = "i2s"; 154 /* Placeholder for external Codec */ 155 }; 156 }; 157 }; 158 }; 159 160 i2s@702d1100 { 161 status = "okay"; 162 163 ports { 164 #address-cells = <1>; 165 #size-cells = <0>; 166 167 port@0 { 168 reg = <0>; 169 170 i2s2_cif_ep: endpoint { 171 remote-endpoint = <&xbar_i2s2_ep>; 172 }; 173 }; 174 175 i2s2_port: port@1 { 176 reg = <1>; 177 178 i2s2_dap_ep: endpoint { 179 dai-format = "i2s"; 180 /* Placeholder for external Codec */ 181 }; 182 }; 183 }; 184 }; 185 186 i2s@702d1200 { 187 status = "okay"; 188 189 ports { 190 #address-cells = <1>; 191 #size-cells = <0>; 192 193 port@0 { 194 reg = <0>; 195 196 i2s3_cif_ep: endpoint { 197 remote-endpoint = <&xbar_i2s3_ep>; 198 }; 199 }; 200 201 i2s3_port: port@1 { 202 reg = <1>; 203 204 i2s3_dap_ep: endpoint { 205 dai-format = "i2s"; 206 /* Placeholder for external Codec */ 207 }; 208 }; 209 }; 210 }; 211 212 i2s@702d1300 { 213 status = "okay"; 214 215 ports { 216 #address-cells = <1>; 217 #size-cells = <0>; 218 219 port@0 { 220 reg = <0>; 221 222 i2s4_cif_ep: endpoint { 223 remote-endpoint = <&xbar_i2s4_ep>; 224 }; 225 }; 226 227 i2s4_port: port@1 { 228 reg = <1>; 229 230 i2s4_dap_ep: endpoint { 231 dai-format = "i2s"; 232 /* Placeholder for external Codec */ 233 }; 234 }; 235 }; 236 }; 237 238 i2s@702d1400 { 239 status = "okay"; 240 241 ports { 242 #address-cells = <1>; 243 #size-cells = <0>; 244 245 port@0 { 246 reg = <0>; 247 248 i2s5_cif_ep: endpoint { 249 remote-endpoint = <&xbar_i2s5_ep>; 250 }; 251 }; 252 253 i2s5_port: port@1 { 254 reg = <1>; 255 256 i2s5_dap_ep: endpoint { 257 dai-format = "i2s"; 258 /* Placeholder for external Codec */ 259 }; 260 }; 261 }; 262 }; 263 264 dmic@702d4000 { 265 status = "okay"; 266 267 ports { 268 #address-cells = <1>; 269 #size-cells = <0>; 270 271 port@0 { 272 reg = <0>; 273 274 dmic1_cif_ep: endpoint { 275 remote-endpoint = <&xbar_dmic1_ep>; 276 }; 277 }; 278 279 dmic1_port: port@1 { 280 reg = <1>; 281 282 dmic1_dap_ep: endpoint { 283 /* Placeholder for external Codec */ 284 }; 285 }; 286 }; 287 }; 288 289 dmic@702d4100 { 290 status = "okay"; 291 292 ports { 293 #address-cells = <1>; 294 #size-cells = <0>; 295 296 port@0 { 297 reg = <0>; 298 299 dmic2_cif_ep: endpoint { 300 remote-endpoint = <&xbar_dmic2_ep>; 301 }; 302 }; 303 304 dmic2_port: port@1 { 305 reg = <1>; 306 307 dmic2_dap_ep: endpoint { 308 /* Placeholder for external Codec */ 309 }; 310 }; 311 }; 312 }; 313 314 dmic@702d4200 { 315 status = "okay"; 316 317 ports { 318 #address-cells = <1>; 319 #size-cells = <0>; 320 321 port@0 { 322 reg = <0>; 323 324 dmic3_cif_ep: endpoint { 325 remote-endpoint = <&xbar_dmic3_ep>; 326 }; 327 }; 328 329 dmic3_port: port@1 { 330 reg = <1>; 331 332 dmic3_dap_ep: endpoint { 333 /* Placeholder for external Codec */ 334 }; 335 }; 336 }; 337 }; 338 339 sfc@702d2000 { 340 status = "okay"; 341 342 ports { 343 #address-cells = <1>; 344 #size-cells = <0>; 345 346 port@0 { 347 reg = <0>; 348 349 sfc1_cif_in_ep: endpoint { 350 remote-endpoint = <&xbar_sfc1_in_ep>; 351 }; 352 }; 353 354 sfc1_out_port: port@1 { 355 reg = <1>; 356 357 sfc1_cif_out_ep: endpoint { 358 remote-endpoint = <&xbar_sfc1_out_ep>; 359 }; 360 }; 361 }; 362 }; 363 364 sfc@702d2200 { 365 status = "okay"; 366 367 ports { 368 #address-cells = <1>; 369 #size-cells = <0>; 370 371 port@0 { 372 reg = <0>; 373 374 sfc2_cif_in_ep: endpoint { 375 remote-endpoint = <&xbar_sfc2_in_ep>; 376 }; 377 }; 378 379 sfc2_out_port: port@1 { 380 reg = <1>; 381 382 sfc2_cif_out_ep: endpoint { 383 remote-endpoint = <&xbar_sfc2_out_ep>; 384 }; 385 }; 386 }; 387 }; 388 389 sfc@702d2400 { 390 status = "okay"; 391 392 ports { 393 #address-cells = <1>; 394 #size-cells = <0>; 395 396 port@0 { 397 reg = <0>; 398 399 sfc3_cif_in_ep: endpoint { 400 remote-endpoint = <&xbar_sfc3_in_ep>; 401 }; 402 }; 403 404 sfc3_out_port: port@1 { 405 reg = <1>; 406 407 sfc3_cif_out_ep: endpoint { 408 remote-endpoint = <&xbar_sfc3_out_ep>; 409 }; 410 }; 411 }; 412 }; 413 414 sfc@702d2600 { 415 status = "okay"; 416 417 ports { 418 #address-cells = <1>; 419 #size-cells = <0>; 420 421 port@0 { 422 reg = <0>; 423 424 sfc4_cif_in_ep: endpoint { 425 remote-endpoint = <&xbar_sfc4_in_ep>; 426 }; 427 }; 428 429 sfc4_out_port: port@1 { 430 reg = <1>; 431 432 sfc4_cif_out_ep: endpoint { 433 remote-endpoint = <&xbar_sfc4_out_ep>; 434 }; 435 }; 436 }; 437 }; 438 439 mvc@702da000 { 440 status = "okay"; 441 442 ports { 443 #address-cells = <1>; 444 #size-cells = <0>; 445 446 port@0 { 447 reg = <0>; 448 449 mvc1_cif_in_ep: endpoint { 450 remote-endpoint = <&xbar_mvc1_in_ep>; 451 }; 452 }; 453 454 mvc1_out_port: port@1 { 455 reg = <1>; 456 457 mvc1_cif_out_ep: endpoint { 458 remote-endpoint = <&xbar_mvc1_out_ep>; 459 }; 460 }; 461 }; 462 }; 463 464 mvc@702da200 { 465 status = "okay"; 466 467 ports { 468 #address-cells = <1>; 469 #size-cells = <0>; 470 471 port@0 { 472 reg = <0>; 473 474 mvc2_cif_in_ep: endpoint { 475 remote-endpoint = <&xbar_mvc2_in_ep>; 476 }; 477 }; 478 479 mvc2_out_port: port@1 { 480 reg = <1>; 481 482 mvc2_cif_out_ep: endpoint { 483 remote-endpoint = <&xbar_mvc2_out_ep>; 484 }; 485 }; 486 }; 487 }; 488 489 amx@702d3000 { 490 status = "okay"; 491 492 ports { 493 #address-cells = <1>; 494 #size-cells = <0>; 495 496 port@0 { 497 reg = <0>; 498 499 amx1_in1_ep: endpoint { 500 remote-endpoint = <&xbar_amx1_in1_ep>; 501 }; 502 }; 503 504 port@1 { 505 reg = <1>; 506 507 amx1_in2_ep: endpoint { 508 remote-endpoint = <&xbar_amx1_in2_ep>; 509 }; 510 }; 511 512 port@2 { 513 reg = <2>; 514 515 amx1_in3_ep: endpoint { 516 remote-endpoint = <&xbar_amx1_in3_ep>; 517 }; 518 }; 519 520 port@3 { 521 reg = <3>; 522 523 amx1_in4_ep: endpoint { 524 remote-endpoint = <&xbar_amx1_in4_ep>; 525 }; 526 }; 527 528 amx1_out_port: port@4 { 529 reg = <4>; 530 531 amx1_out_ep: endpoint { 532 remote-endpoint = <&xbar_amx1_out_ep>; 533 }; 534 }; 535 }; 536 }; 537 538 amx@702d3100 { 539 status = "okay"; 540 541 ports { 542 #address-cells = <1>; 543 #size-cells = <0>; 544 545 port@0 { 546 reg = <0>; 547 548 amx2_in1_ep: endpoint { 549 remote-endpoint = <&xbar_amx2_in1_ep>; 550 }; 551 }; 552 553 port@1 { 554 reg = <1>; 555 556 amx2_in2_ep: endpoint { 557 remote-endpoint = <&xbar_amx2_in2_ep>; 558 }; 559 }; 560 561 amx2_in3_port: port@2 { 562 reg = <2>; 563 564 amx2_in3_ep: endpoint { 565 remote-endpoint = <&xbar_amx2_in3_ep>; 566 }; 567 }; 568 569 amx2_in4_port: port@3 { 570 reg = <3>; 571 572 amx2_in4_ep: endpoint { 573 remote-endpoint = <&xbar_amx2_in4_ep>; 574 }; 575 }; 576 577 amx2_out_port: port@4 { 578 reg = <4>; 579 580 amx2_out_ep: endpoint { 581 remote-endpoint = <&xbar_amx2_out_ep>; 582 }; 583 }; 584 }; 585 }; 586 587 adx@702d3800 { 588 status = "okay"; 589 590 ports { 591 #address-cells = <1>; 592 #size-cells = <0>; 593 594 port@0 { 595 reg = <0>; 596 597 adx1_in_ep: endpoint { 598 remote-endpoint = <&xbar_adx1_in_ep>; 599 }; 600 }; 601 602 adx1_out1_port: port@1 { 603 reg = <1>; 604 605 adx1_out1_ep: endpoint { 606 remote-endpoint = <&xbar_adx1_out1_ep>; 607 }; 608 }; 609 610 adx1_out2_port: port@2 { 611 reg = <2>; 612 613 adx1_out2_ep: endpoint { 614 remote-endpoint = <&xbar_adx1_out2_ep>; 615 }; 616 }; 617 618 adx1_out3_port: port@3 { 619 reg = <3>; 620 621 adx1_out3_ep: endpoint { 622 remote-endpoint = <&xbar_adx1_out3_ep>; 623 }; 624 }; 625 626 adx1_out4_port: port@4 { 627 reg = <4>; 628 629 adx1_out4_ep: endpoint { 630 remote-endpoint = <&xbar_adx1_out4_ep>; 631 }; 632 }; 633 }; 634 }; 635 636 adx@702d3900 { 637 status = "okay"; 638 639 ports { 640 #address-cells = <1>; 641 #size-cells = <0>; 642 643 port@0 { 644 reg = <0>; 645 646 adx2_in_ep: endpoint { 647 remote-endpoint = <&xbar_adx2_in_ep>; 648 }; 649 }; 650 651 adx2_out1_port: port@1 { 652 reg = <1>; 653 654 adx2_out1_ep: endpoint { 655 remote-endpoint = <&xbar_adx2_out1_ep>; 656 }; 657 }; 658 659 adx2_out2_port: port@2 { 660 reg = <2>; 661 662 adx2_out2_ep: endpoint { 663 remote-endpoint = <&xbar_adx2_out2_ep>; 664 }; 665 }; 666 667 adx2_out3_port: port@3 { 668 reg = <3>; 669 670 adx2_out3_ep: endpoint { 671 remote-endpoint = <&xbar_adx2_out3_ep>; 672 }; 673 }; 674 675 adx2_out4_port: port@4 { 676 reg = <4>; 677 678 adx2_out4_ep: endpoint { 679 remote-endpoint = <&xbar_adx2_out4_ep>; 680 }; 681 }; 682 }; 683 }; 684 685 amixer@702dbb00 { 686 status = "okay"; 687 688 ports { 689 #address-cells = <1>; 690 #size-cells = <0>; 691 692 port@0 { 693 reg = <0x0>; 694 695 mixer_in1_ep: endpoint { 696 remote-endpoint = <&xbar_mixer_in1_ep>; 697 }; 698 }; 699 700 port@1 { 701 reg = <0x1>; 702 703 mixer_in2_ep: endpoint { 704 remote-endpoint = <&xbar_mixer_in2_ep>; 705 }; 706 }; 707 708 port@2 { 709 reg = <0x2>; 710 711 mixer_in3_ep: endpoint { 712 remote-endpoint = <&xbar_mixer_in3_ep>; 713 }; 714 }; 715 716 port@3 { 717 reg = <0x3>; 718 719 mixer_in4_ep: endpoint { 720 remote-endpoint = <&xbar_mixer_in4_ep>; 721 }; 722 }; 723 724 port@4 { 725 reg = <0x4>; 726 727 mixer_in5_ep: endpoint { 728 remote-endpoint = <&xbar_mixer_in5_ep>; 729 }; 730 }; 731 732 port@5 { 733 reg = <0x5>; 734 735 mixer_in6_ep: endpoint { 736 remote-endpoint = <&xbar_mixer_in6_ep>; 737 }; 738 }; 739 740 port@6 { 741 reg = <0x6>; 742 743 mixer_in7_ep: endpoint { 744 remote-endpoint = <&xbar_mixer_in7_ep>; 745 }; 746 }; 747 748 port@7 { 749 reg = <0x7>; 750 751 mixer_in8_ep: endpoint { 752 remote-endpoint = <&xbar_mixer_in8_ep>; 753 }; 754 }; 755 756 port@8 { 757 reg = <0x8>; 758 759 mixer_in9_ep: endpoint { 760 remote-endpoint = <&xbar_mixer_in9_ep>; 761 }; 762 }; 763 764 port@9 { 765 reg = <0x9>; 766 767 mixer_in10_ep: endpoint { 768 remote-endpoint = <&xbar_mixer_in10_ep>; 769 }; 770 }; 771 772 mixer_out1_port: port@a { 773 reg = <0xa>; 774 775 mixer_out1_ep: endpoint { 776 remote-endpoint = <&xbar_mixer_out1_ep>; 777 }; 778 }; 779 780 mixer_out2_port: port@b { 781 reg = <0xb>; 782 783 mixer_out2_ep: endpoint { 784 remote-endpoint = <&xbar_mixer_out2_ep>; 785 }; 786 }; 787 788 mixer_out3_port: port@c { 789 reg = <0xc>; 790 791 mixer_out3_ep: endpoint { 792 remote-endpoint = <&xbar_mixer_out3_ep>; 793 }; 794 }; 795 796 mixer_out4_port: port@d { 797 reg = <0xd>; 798 799 mixer_out4_ep: endpoint { 800 remote-endpoint = <&xbar_mixer_out4_ep>; 801 }; 802 }; 803 804 mixer_out5_port: port@e { 805 reg = <0xe>; 806 807 mixer_out5_ep: endpoint { 808 remote-endpoint = <&xbar_mixer_out5_ep>; 809 }; 810 }; 811 }; 812 }; 813 814 ports { 815 xbar_i2s1_port: port@a { 816 reg = <0xa>; 817 818 xbar_i2s1_ep: endpoint { 819 remote-endpoint = <&i2s1_cif_ep>; 820 }; 821 }; 822 823 xbar_i2s2_port: port@b { 824 reg = <0xb>; 825 826 xbar_i2s2_ep: endpoint { 827 remote-endpoint = <&i2s2_cif_ep>; 828 }; 829 }; 830 831 xbar_i2s3_port: port@c { 832 reg = <0xc>; 833 834 xbar_i2s3_ep: endpoint { 835 remote-endpoint = <&i2s3_cif_ep>; 836 }; 837 }; 838 839 xbar_i2s4_port: port@d { 840 reg = <0xd>; 841 842 xbar_i2s4_ep: endpoint { 843 remote-endpoint = <&i2s4_cif_ep>; 844 }; 845 }; 846 847 xbar_i2s5_port: port@e { 848 reg = <0xe>; 849 850 xbar_i2s5_ep: endpoint { 851 remote-endpoint = <&i2s5_cif_ep>; 852 }; 853 }; 854 855 xbar_dmic1_port: port@f { 856 reg = <0xf>; 857 858 xbar_dmic1_ep: endpoint { 859 remote-endpoint = <&dmic1_cif_ep>; 860 }; 861 }; 862 863 xbar_dmic2_port: port@10 { 864 reg = <0x10>; 865 866 xbar_dmic2_ep: endpoint { 867 remote-endpoint = <&dmic2_cif_ep>; 868 }; 869 }; 870 871 xbar_dmic3_port: port@11 { 872 reg = <0x11>; 873 874 xbar_dmic3_ep: endpoint { 875 remote-endpoint = <&dmic3_cif_ep>; 876 }; 877 }; 878 879 xbar_sfc1_in_port: port@12 { 880 reg = <0x12>; 881 882 xbar_sfc1_in_ep: endpoint { 883 remote-endpoint = <&sfc1_cif_in_ep>; 884 }; 885 }; 886 887 port@13 { 888 reg = <0x13>; 889 890 xbar_sfc1_out_ep: endpoint { 891 remote-endpoint = <&sfc1_cif_out_ep>; 892 }; 893 }; 894 895 xbar_sfc2_in_port: port@14 { 896 reg = <0x14>; 897 898 xbar_sfc2_in_ep: endpoint { 899 remote-endpoint = <&sfc2_cif_in_ep>; 900 }; 901 }; 902 903 port@15 { 904 reg = <0x15>; 905 906 xbar_sfc2_out_ep: endpoint { 907 remote-endpoint = <&sfc2_cif_out_ep>; 908 }; 909 }; 910 911 xbar_sfc3_in_port: port@16 { 912 reg = <0x16>; 913 914 xbar_sfc3_in_ep: endpoint { 915 remote-endpoint = <&sfc3_cif_in_ep>; 916 }; 917 }; 918 919 port@17 { 920 reg = <0x17>; 921 922 xbar_sfc3_out_ep: endpoint { 923 remote-endpoint = <&sfc3_cif_out_ep>; 924 }; 925 }; 926 927 xbar_sfc4_in_port: port@18 { 928 reg = <0x18>; 929 930 xbar_sfc4_in_ep: endpoint { 931 remote-endpoint = <&sfc4_cif_in_ep>; 932 }; 933 }; 934 935 port@19 { 936 reg = <0x19>; 937 938 xbar_sfc4_out_ep: endpoint { 939 remote-endpoint = <&sfc4_cif_out_ep>; 940 }; 941 }; 942 943 xbar_mvc1_in_port: port@1a { 944 reg = <0x1a>; 945 946 xbar_mvc1_in_ep: endpoint { 947 remote-endpoint = <&mvc1_cif_in_ep>; 948 }; 949 }; 950 951 port@1b { 952 reg = <0x1b>; 953 954 xbar_mvc1_out_ep: endpoint { 955 remote-endpoint = <&mvc1_cif_out_ep>; 956 }; 957 }; 958 959 xbar_mvc2_in_port: port@1c { 960 reg = <0x1c>; 961 962 xbar_mvc2_in_ep: endpoint { 963 remote-endpoint = <&mvc2_cif_in_ep>; 964 }; 965 }; 966 967 port@1d { 968 reg = <0x1d>; 969 970 xbar_mvc2_out_ep: endpoint { 971 remote-endpoint = <&mvc2_cif_out_ep>; 972 }; 973 }; 974 975 xbar_amx1_in1_port: port@1e { 976 reg = <0x1e>; 977 978 xbar_amx1_in1_ep: endpoint { 979 remote-endpoint = <&amx1_in1_ep>; 980 }; 981 }; 982 983 xbar_amx1_in2_port: port@1f { 984 reg = <0x1f>; 985 986 xbar_amx1_in2_ep: endpoint { 987 remote-endpoint = <&amx1_in2_ep>; 988 }; 989 }; 990 991 xbar_amx1_in3_port: port@20 { 992 reg = <0x20>; 993 994 xbar_amx1_in3_ep: endpoint { 995 remote-endpoint = <&amx1_in3_ep>; 996 }; 997 }; 998 999 xbar_amx1_in4_port: port@21 { 1000 reg = <0x21>; 1001 1002 xbar_amx1_in4_ep: endpoint { 1003 remote-endpoint = <&amx1_in4_ep>; 1004 }; 1005 }; 1006 1007 port@22 { 1008 reg = <0x22>; 1009 1010 xbar_amx1_out_ep: endpoint { 1011 remote-endpoint = <&amx1_out_ep>; 1012 }; 1013 }; 1014 1015 xbar_amx2_in1_port: port@23 { 1016 reg = <0x23>; 1017 1018 xbar_amx2_in1_ep: endpoint { 1019 remote-endpoint = <&amx2_in1_ep>; 1020 }; 1021 }; 1022 1023 xbar_amx2_in2_port: port@24 { 1024 reg = <0x24>; 1025 1026 xbar_amx2_in2_ep: endpoint { 1027 remote-endpoint = <&amx2_in2_ep>; 1028 }; 1029 }; 1030 1031 xbar_amx2_in3_port: port@25 { 1032 reg = <0x25>; 1033 1034 xbar_amx2_in3_ep: endpoint { 1035 remote-endpoint = <&amx2_in3_ep>; 1036 }; 1037 }; 1038 1039 xbar_amx2_in4_port: port@26 { 1040 reg = <0x26>; 1041 1042 xbar_amx2_in4_ep: endpoint { 1043 remote-endpoint = <&amx2_in4_ep>; 1044 }; 1045 }; 1046 1047 port@27 { 1048 reg = <0x27>; 1049 1050 xbar_amx2_out_ep: endpoint { 1051 remote-endpoint = <&amx2_out_ep>; 1052 }; 1053 }; 1054 1055 xbar_adx1_in_port: port@28 { 1056 reg = <0x28>; 1057 1058 xbar_adx1_in_ep: endpoint { 1059 remote-endpoint = <&adx1_in_ep>; 1060 }; 1061 }; 1062 1063 port@29 { 1064 reg = <0x29>; 1065 1066 xbar_adx1_out1_ep: endpoint { 1067 remote-endpoint = <&adx1_out1_ep>; 1068 }; 1069 }; 1070 1071 port@2a { 1072 reg = <0x2a>; 1073 1074 xbar_adx1_out2_ep: endpoint { 1075 remote-endpoint = <&adx1_out2_ep>; 1076 }; 1077 }; 1078 1079 port@2b { 1080 reg = <0x2b>; 1081 1082 xbar_adx1_out3_ep: endpoint { 1083 remote-endpoint = <&adx1_out3_ep>; 1084 }; 1085 }; 1086 1087 port@2c { 1088 reg = <0x2c>; 1089 1090 xbar_adx1_out4_ep: endpoint { 1091 remote-endpoint = <&adx1_out4_ep>; 1092 }; 1093 }; 1094 1095 xbar_adx2_in_port: port@2d { 1096 reg = <0x2d>; 1097 1098 xbar_adx2_in_ep: endpoint { 1099 remote-endpoint = <&adx2_in_ep>; 1100 }; 1101 }; 1102 1103 port@2e { 1104 reg = <0x2e>; 1105 1106 xbar_adx2_out1_ep: endpoint { 1107 remote-endpoint = <&adx2_out1_ep>; 1108 }; 1109 }; 1110 1111 port@2f { 1112 reg = <0x2f>; 1113 1114 xbar_adx2_out2_ep: endpoint { 1115 remote-endpoint = <&adx2_out2_ep>; 1116 }; 1117 }; 1118 1119 port@30 { 1120 reg = <0x30>; 1121 1122 xbar_adx2_out3_ep: endpoint { 1123 remote-endpoint = <&adx2_out3_ep>; 1124 }; 1125 }; 1126 1127 port@31 { 1128 reg = <0x31>; 1129 1130 xbar_adx2_out4_ep: endpoint { 1131 remote-endpoint = <&adx2_out4_ep>; 1132 }; 1133 }; 1134 1135 xbar_mixer_in1_port: port@32 { 1136 reg = <0x32>; 1137 1138 xbar_mixer_in1_ep: endpoint { 1139 remote-endpoint = <&mixer_in1_ep>; 1140 }; 1141 }; 1142 1143 xbar_mixer_in2_port: port@33 { 1144 reg = <0x33>; 1145 1146 xbar_mixer_in2_ep: endpoint { 1147 remote-endpoint = <&mixer_in2_ep>; 1148 }; 1149 }; 1150 1151 xbar_mixer_in3_port: port@34 { 1152 reg = <0x34>; 1153 1154 xbar_mixer_in3_ep: endpoint { 1155 remote-endpoint = <&mixer_in3_ep>; 1156 }; 1157 }; 1158 1159 xbar_mixer_in4_port: port@35 { 1160 reg = <0x35>; 1161 1162 xbar_mixer_in4_ep: endpoint { 1163 remote-endpoint = <&mixer_in4_ep>; 1164 }; 1165 }; 1166 1167 xbar_mixer_in5_port: port@36 { 1168 reg = <0x36>; 1169 1170 xbar_mixer_in5_ep: endpoint { 1171 remote-endpoint = <&mixer_in5_ep>; 1172 }; 1173 }; 1174 1175 xbar_mixer_in6_port: port@37 { 1176 reg = <0x37>; 1177 1178 xbar_mixer_in6_ep: endpoint { 1179 remote-endpoint = <&mixer_in6_ep>; 1180 }; 1181 }; 1182 1183 xbar_mixer_in7_port: port@38 { 1184 reg = <0x38>; 1185 1186 xbar_mixer_in7_ep: endpoint { 1187 remote-endpoint = <&mixer_in7_ep>; 1188 }; 1189 }; 1190 1191 xbar_mixer_in8_port: port@39 { 1192 reg = <0x39>; 1193 1194 xbar_mixer_in8_ep: endpoint { 1195 remote-endpoint = <&mixer_in8_ep>; 1196 }; 1197 }; 1198 1199 xbar_mixer_in9_port: port@3a { 1200 reg = <0x3a>; 1201 1202 xbar_mixer_in9_ep: endpoint { 1203 remote-endpoint = <&mixer_in9_ep>; 1204 }; 1205 }; 1206 1207 xbar_mixer_in10_port: port@3b { 1208 reg = <0x3b>; 1209 1210 xbar_mixer_in10_ep: endpoint { 1211 remote-endpoint = <&mixer_in10_ep>; 1212 }; 1213 }; 1214 1215 port@3c { 1216 reg = <0x3c>; 1217 1218 xbar_mixer_out1_ep: endpoint { 1219 remote-endpoint = <&mixer_out1_ep>; 1220 }; 1221 }; 1222 1223 port@3d { 1224 reg = <0x3d>; 1225 1226 xbar_mixer_out2_ep: endpoint { 1227 remote-endpoint = <&mixer_out2_ep>; 1228 }; 1229 }; 1230 1231 port@3e { 1232 reg = <0x3e>; 1233 1234 xbar_mixer_out3_ep: endpoint { 1235 remote-endpoint = <&mixer_out3_ep>; 1236 }; 1237 }; 1238 1239 port@3f { 1240 reg = <0x3f>; 1241 1242 xbar_mixer_out4_ep: endpoint { 1243 remote-endpoint = <&mixer_out4_ep>; 1244 }; 1245 }; 1246 1247 port@40 { 1248 reg = <0x40>; 1249 1250 xbar_mixer_out5_ep: endpoint { 1251 remote-endpoint = <&mixer_out5_ep>; 1252 }; 1253 }; 1254 }; 1255 }; 1256 }; 1257 1258 sound { 1259 compatible = "nvidia,tegra210-audio-graph-card"; 1260 status = "okay"; 1261 1262 dais = /* FE */ 1263 <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, 1264 <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, 1265 <&admaif7_port>, <&admaif8_port>, <&admaif9_port>, 1266 <&admaif10_port>, 1267 /* Router */ 1268 <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s3_port>, 1269 <&xbar_i2s4_port>, <&xbar_i2s5_port>, <&xbar_dmic1_port>, 1270 <&xbar_dmic2_port>, <&xbar_dmic3_port>, 1271 <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>, 1272 <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>, 1273 <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>, 1274 <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>, 1275 <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>, 1276 <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>, 1277 <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>, 1278 <&xbar_adx1_in_port>, <&xbar_adx2_in_port>, 1279 <&xbar_mixer_in1_port>, <&xbar_mixer_in2_port>, 1280 <&xbar_mixer_in3_port>, <&xbar_mixer_in4_port>, 1281 <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>, 1282 <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>, 1283 <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>, 1284 /* HW accelerators */ 1285 <&sfc1_out_port>, <&sfc2_out_port>, 1286 <&sfc3_out_port>, <&sfc4_out_port>, 1287 <&mvc1_out_port>, <&mvc2_out_port>, 1288 <&amx1_out_port>, <&amx2_out_port>, 1289 <&adx1_out1_port>, <&adx1_out2_port>, 1290 <&adx1_out3_port>, <&adx1_out4_port>, 1291 <&adx2_out1_port>, <&adx2_out2_port>, 1292 <&adx2_out3_port>, <&adx2_out4_port>, 1293 <&mixer_out1_port>, <&mixer_out2_port>, 1294 <&mixer_out3_port>, <&mixer_out4_port>, 1295 <&mixer_out5_port>, 1296 /* I/O DAP Ports */ 1297 <&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>, 1298 <&i2s5_port>, <&dmic1_port>, <&dmic2_port>, <&dmic3_port>; 1299 1300 label = "NVIDIA Jetson TX1 APE"; 1301 }; 1302};