cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

sc7280-crd-r3.dts (1932B)

      1// SPDX-License-Identifier: BSD-3-Clause
      2/*
      3 * sc7280 CRD board device tree source
      4 *
      5 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
      6 */
      7
      8/dts-v1/;
      9
     10#include "sc7280-idp.dtsi"
     11#include "sc7280-idp-ec-h1.dtsi"
     12
     13/ {
     14	model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev3 - 4)";
     15	compatible = "qcom,sc7280-crd",
     16		     "google,hoglin-rev3", "google,hoglin-rev4",
     17		     "google,piglin-rev3", "google,piglin-rev4",
     18		     "qcom,sc7280";
     19
     20	aliases {
     21		serial0 = &uart5;
     22	};
     23
     24	chosen {
     25		stdout-path = "serial0:115200n8";
     26	};
     27};
     28
     29&apps_rsc {
     30	pmg1110-regulators {
     31		compatible = "qcom,pmg1110-rpmh-regulators";
     32		qcom,pmic-id = "k";
     33
     34		vreg_s1k_1p0: smps1 {
     35			regulator-min-microvolt = <1010000>;
     36			regulator-max-microvolt = <1170000>;
     37		};
     38	};
     39};
     40
     41ap_tp_i2c: &i2c0 {
     42	status = "okay";
     43	clock-frequency = <400000>;
     44
     45	trackpad: trackpad@15 {
     46		compatible = "hid-over-i2c";
     47		reg = <0x15>;
     48		pinctrl-names = "default";
     49		pinctrl-0 = <&tp_int_odl>;
     50
     51		interrupt-parent = <&tlmm>;
     52		interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
     53
     54		post-power-on-delay-ms = <20>;
     55		hid-descr-addr = <0x0001>;
     56		vdd-supply = <&vreg_l18b_1p8>;
     57
     58		wakeup-source;
     59	};
     60};
     61
     62ap_ts_pen_1v8: &i2c13 {
     63	status = "okay";
     64	clock-frequency = <400000>;
     65
     66	ap_ts: touchscreen@5c {
     67		compatible = "hid-over-i2c";
     68		reg = <0x5c>;
     69		pinctrl-names = "default";
     70		pinctrl-0 = <&ts_int_l>, <&ts_reset_l>;
     71
     72		interrupt-parent = <&tlmm>;
     73		interrupts = <55 IRQ_TYPE_LEVEL_LOW>;
     74
     75		post-power-on-delay-ms = <500>;
     76		hid-descr-addr = <0x0000>;
     77
     78		vdd-supply = <&vreg_l19b_1p8>;
     79	};
     80};
     81
     82&nvme_3v3_regulator {
     83	gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>;
     84};
     85
     86&nvme_pwren {
     87	pins = "gpio51";
     88};
     89
     90&tlmm {
     91	tp_int_odl: tp-int-odl {
     92		pins = "gpio7";
     93		function = "gpio";
     94		bias-disable;
     95	};
     96
     97	ts_int_l: ts-int-l {
     98		pins = "gpio55";
     99		function = "gpio";
    100		bias-pull-up;
    101	};
    102
    103	ts_reset_l: ts-reset-l {
    104		pins = "gpio54";
    105		function = "gpio";
    106		bias-disable;
    107	};
    108};