sc7280-herobrine-crd.dts (6600B)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sc7280 CRD 3+ board device tree source 4 * 5 * Copyright 2022 Google LLC. 6 */ 7 8/dts-v1/; 9 10#include "sc7280-herobrine.dtsi" 11 12/ { 13 model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev5+)"; 14 compatible = "google,hoglin", "qcom,sc7280"; 15 16 /* FIXED REGULATORS */ 17 18 /* 19 * On most herobrine boards PPVAR_SYS directly provides VREG_EDP_BL. 20 * However, on CRD there's an extra regulator in the way. Since this 21 * is expected to be uncommon, we'll leave the "vreg_edp_bl" label 22 * in the baseboard herobrine.dtsi point at "ppvar_sys" and then 23 * make a "_crd" specific version here. 24 */ 25 vreg_edp_bl_crd: vreg-edp-bl-crd-regulator { 26 compatible = "regulator-fixed"; 27 regulator-name = "vreg_edp_bl_crd"; 28 29 gpio = <&pm8350c_gpios 6 GPIO_ACTIVE_HIGH>; 30 enable-active-high; 31 pinctrl-names = "default"; 32 pinctrl-0 = <&edp_bl_reg_en>; 33 34 vin-supply = <&ppvar_sys>; 35 }; 36}; 37 38/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ 39 40&apps_rsc { 41 pmg1110-regulators { 42 compatible = "qcom,pmg1110-rpmh-regulators"; 43 qcom,pmic-id = "k"; 44 45 vreg_s1k_1p0: smps1 { 46 regulator-min-microvolt = <1010000>; 47 regulator-max-microvolt = <1170000>; 48 }; 49 }; 50}; 51 52ap_tp_i2c: &i2c0 { 53 status = "okay"; 54 clock-frequency = <400000>; 55 56 trackpad: trackpad@15 { 57 compatible = "hid-over-i2c"; 58 reg = <0x15>; 59 pinctrl-names = "default"; 60 pinctrl-0 = <&tp_int_odl>; 61 62 interrupt-parent = <&tlmm>; 63 interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 64 65 post-power-on-delay-ms = <20>; 66 hid-descr-addr = <0x0001>; 67 vdd-supply = <&pp3300_z1>; 68 69 wakeup-source; 70 }; 71}; 72 73&ap_sar_sensor_i2c { 74 status = "okay"; 75}; 76 77&ap_sar_sensor0 { 78 status = "okay"; 79}; 80 81&ap_sar_sensor1 { 82 status = "okay"; 83}; 84 85ap_ts_pen_1v8: &i2c13 { 86 status = "okay"; 87 clock-frequency = <400000>; 88 89 ap_ts: touchscreen@5c { 90 compatible = "hid-over-i2c"; 91 reg = <0x5c>; 92 pinctrl-names = "default"; 93 pinctrl-0 = <&ts_int_conn>, <&ts_rst_conn>; 94 95 interrupt-parent = <&tlmm>; 96 interrupts = <55 IRQ_TYPE_LEVEL_LOW>; 97 98 post-power-on-delay-ms = <500>; 99 hid-descr-addr = <0x0000>; 100 101 vdd-supply = <&pp3300_left_in_mlb>; 102 }; 103}; 104 105&mdss_edp { 106 status = "okay"; 107}; 108 109&mdss_edp_phy { 110 status = "okay"; 111}; 112 113/* For nvme */ 114&pcie1 { 115 status = "okay"; 116}; 117 118/* For nvme */ 119&pcie1_phy { 120 status = "okay"; 121}; 122 123&pm8350c_pwm_backlight { 124 power-supply = <&vreg_edp_bl_crd>; 125}; 126 127/* For eMMC */ 128&sdhc_1 { 129 status = "okay"; 130}; 131 132/* For SD Card */ 133&sdhc_2 { 134 status = "okay"; 135}; 136 137/* PINCTRL - BOARD-SPECIFIC */ 138 139/* 140 * Methodology for gpio-line-names: 141 * - If a pin goes to CRD board and is named it gets that name. 142 * - If a pin goes to CRD board and is not named, it gets no name. 143 * - If a pin is totally internal to Qcard then it gets Qcard name. 144 * - If a pin is not hooked up on Qcard, it gets no name. 145 */ 146 147&pm8350c_gpios { 148 gpio-line-names = "FLASH_STROBE_1", /* 1 */ 149 "AP_SUSPEND", 150 "PM8008_1_RST_N", 151 "", 152 "", 153 "EDP_BL_REG_EN", 154 "PMIC_EDP_BL_EN", 155 "PMIC_EDP_BL_PWM", 156 ""; 157 158 edp_bl_reg_en: edp-bl-reg-en { 159 pins = "gpio6"; 160 function = "normal"; 161 bias-disable; 162 qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>; 163 }; 164}; 165 166&tlmm { 167 gpio-line-names = "AP_TP_I2C_SDA", /* 0 */ 168 "AP_TP_I2C_SCL", 169 "PCIE1_RESET_N", 170 "PCIE1_WAKE_N", 171 "APPS_I2C_SDA", 172 "APPS_I2C_SCL", 173 "", 174 "TPAD_INT_N", 175 "", 176 "", 177 178 "GNSS_L1_EN", /* 10 */ 179 "GNSS_L5_EN", 180 "QSPI_DATA_0", 181 "QSPI_DATA_1", 182 "QSPI_CLK", 183 "QSPI_CS_N_1", 184 /* 185 * AP_FLASH_WP is crossystem ABI. Schematics call it 186 * BIOS_FLASH_WP_L (the '_L' suffix is misleading, the 187 * signal is active high). 188 */ 189 "AP_FLASH_WP", 190 "", 191 "AP_EC_INT_N", 192 "", 193 194 "CAM0_RST_N", /* 20 */ 195 "CAM1_RST_N", 196 "SM_DBG_UART_TX", 197 "SM_DBG_UART_RX", 198 "", 199 "PM8008_IRQ_1", 200 "HOST2WLAN_SOL", 201 "WLAN2HOST_SOL", 202 "MOS_BT_UART_CTS", 203 "MOS_BT_UART_RFR", 204 205 "MOS_BT_UART_TX", /* 30 */ 206 "MOS_BT_UART_RX", 207 "", 208 "HUB_RST", 209 "", 210 "", 211 "", 212 "", 213 "", 214 "", 215 216 "EC_SPI_MISO_GPIO40", /* 40 */ 217 "EC_SPI_MOSI_GPIO41", 218 "EC_SPI_CLK_GPIO42", 219 "EC_SPI_CS_GPIO43", 220 "", 221 "EARLY_EUD_EN", 222 "", 223 "DP_HOT_PLUG_DETECT", 224 "AP_BRD_ID_0", 225 "AP_BRD_ID_1", 226 227 "AP_BRD_ID_2", /* 50 */ 228 "NVME_PWR_REG_EN", 229 "TS_I2C_SDA_CONN", 230 "TS_I2C_CLK_CONN", 231 "TS_RST_CONN", 232 "TS_INT_CONN", 233 "AP_I2C_TPM_SDA", 234 "AP_I2C_TPM_SCL", 235 "", 236 "", 237 238 "EDP_HOT_PLUG_DET_N", /* 60 */ 239 "", 240 "", 241 "AMP_EN", 242 "CAM0_MCLK_GPIO_64", 243 "CAM1_MCLK_GPIO_65", 244 "", 245 "", 246 "", 247 "CCI_I2C_SDA0", 248 249 "CCI_I2C_SCL0", /* 70 */ 250 "", 251 "", 252 "", 253 "", 254 "", 255 "", 256 "", 257 "", 258 "PCIE1_CLK_REQ_N", 259 260 "EN_PP3300_DX_EDP", /* 80 */ 261 "US_EURO_HS_SEL", 262 "FORCED_USB_BOOT", 263 "WCD_RESET_N", 264 "MOS_WLAN_EN", 265 "MOS_BT_EN", 266 "MOS_SW_CTRL", 267 "MOS_PCIE0_RST", 268 "MOS_PCIE0_CLKREQ_N", 269 "MOS_PCIE0_WAKE_N", 270 271 "MOS_LAA_AS_EN", /* 90 */ 272 "SD_CARD_DET_CONN", 273 "", 274 "", 275 "MOS_BT_WLAN_SLIMBUS_CLK", 276 "MOS_BT_WLAN_SLIMBUS_DAT0", 277 "", 278 "", 279 "", 280 "", 281 282 "", /* 100 */ 283 "", 284 "", 285 "", 286 "H1_AP_INT_N", 287 "", 288 "AMP_BCLK", 289 "AMP_DIN", 290 "AMP_LRCLK", 291 "UIM1_DATA_GPIO_109", 292 293 "UIM1_CLK_GPIO_110", /* 110 */ 294 "UIM1_RESET_GPIO_111", 295 "", 296 "UIM1_DATA", 297 "UIM1_CLK", 298 "UIM1_RESET", 299 "UIM1_PRESENT", 300 "SDM_RFFE0_CLK", 301 "SDM_RFFE0_DATA", 302 "", 303 304 "SDM_RFFE1_DATA", /* 120 */ 305 "SC_GPIO_121", 306 "FASTBOOT_SEL_1", 307 "SC_GPIO_123", 308 "FASTBOOT_SEL_2", 309 "SM_RFFE4_CLK_GRFC_8", 310 "SM_RFFE4_DATA_GRFC_9", 311 "WLAN_COEX_UART1_RX", 312 "WLAN_COEX_UART1_TX", 313 "", 314 315 "", /* 130 */ 316 "", 317 "", 318 "SDR_QLINK_REQ", 319 "SDR_QLINK_EN", 320 "QLINK0_WMSS_RESET_N", 321 "SMR526_QLINK1_REQ", 322 "SMR526_QLINK1_EN", 323 "SMR526_QLINK1_WMSS_RESET_N", 324 "", 325 326 "SAR1_INT_N", /* 140 */ 327 "SAR0_INT_N", 328 "", 329 "", 330 "WCD_SWR_TX_CLK", 331 "WCD_SWR_TX_DATA0", 332 "WCD_SWR_TX_DATA1", 333 "WCD_SWR_RX_CLK", 334 "WCD_SWR_RX_DATA0", 335 "WCD_SWR_RX_DATA1", 336 337 "DMIC01_CLK", /* 150 */ 338 "DMIC01_DATA", 339 "DMIC23_CLK", 340 "DMIC23_DATA", 341 "", 342 "", 343 "EC_IN_RW_N", 344 "EN_PP3300_HUB", 345 "WCD_SWR_TX_DATA2", 346 "", 347 348 "", /* 160 */ 349 "", 350 "", 351 "", 352 "", 353 "", 354 "", 355 "", 356 "", 357 "", 358 359 "", /* 170 */ 360 "MOS_BLE_UART_TX", 361 "MOS_BLE_UART_RX", 362 "", 363 "", 364 ""; 365};