cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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sc7280-idp-ec-h1.dtsi (2194B)

      1// SPDX-License-Identifier: BSD-3-Clause
      2/*
      3 * sc7280 EC/H1 over SPI (common between IDP2 and CRD)
      4 *
      5 * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
      6 */
      7
      8ap_ec_spi: &spi10 {
      9	status = "okay";
     10
     11	pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs_gpio_init_high>, <&qup_spi10_cs_gpio>;
     12	cs-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
     13
     14	cros_ec: ec@0 {
     15		compatible = "google,cros-ec-spi";
     16		reg = <0>;
     17		interrupt-parent = <&tlmm>;
     18		interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
     19		pinctrl-names = "default";
     20		pinctrl-0 = <&ap_ec_int_l>;
     21		spi-max-frequency = <3000000>;
     22
     23		cros_ec_pwm: pwm {
     24			compatible = "google,cros-ec-pwm";
     25			#pwm-cells = <1>;
     26		};
     27
     28		i2c_tunnel: i2c-tunnel {
     29			compatible = "google,cros-ec-i2c-tunnel";
     30			google,remote-bus = <0>;
     31			#address-cells = <1>;
     32			#size-cells = <0>;
     33		};
     34
     35		typec {
     36			compatible = "google,cros-ec-typec";
     37			#address-cells = <1>;
     38			#size-cells = <0>;
     39
     40			usb_c0: connector@0 {
     41				compatible = "usb-c-connector";
     42				reg = <0>;
     43				label = "left";
     44				power-role = "dual";
     45				data-role = "host";
     46				try-power-role = "source";
     47			};
     48
     49			usb_c1: connector@1 {
     50				compatible = "usb-c-connector";
     51				reg = <1>;
     52				label = "right";
     53				power-role = "dual";
     54				data-role = "host";
     55				try-power-role = "source";
     56			};
     57		};
     58	};
     59};
     60
     61#include <arm/cros-ec-keyboard.dtsi>
     62#include <arm/cros-ec-sbs.dtsi>
     63
     64ap_h1_spi: &spi14 {
     65	status = "okay";
     66
     67	pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs_gpio_init_high>, <&qup_spi14_cs_gpio>;
     68	cs-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
     69
     70	cr50: tpm@0 {
     71		compatible = "google,cr50";
     72		reg = <0>;
     73		pinctrl-names = "default";
     74		pinctrl-0 = <&h1_ap_int_odl>;
     75		spi-max-frequency = <800000>;
     76		interrupt-parent = <&tlmm>;
     77		interrupts = <104 IRQ_TYPE_EDGE_RISING>;
     78	};
     79};
     80
     81&tlmm {
     82	ap_ec_int_l: ap-ec-int-l {
     83		pins = "gpio18";
     84		function = "gpio";
     85		input-enable;
     86		bias-pull-up;
     87	};
     88
     89	h1_ap_int_odl: h1-ap-int-odl {
     90		pins = "gpio104";
     91		function = "gpio";
     92		input-enable;
     93		bias-pull-up;
     94	};
     95
     96	qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high {
     97		pins = "gpio43";
     98		output-high;
     99	};
    100
    101	qup_spi14_cs_gpio_init_high: qup-spi14-cs-gpio-init-high {
    102		pins = "gpio59";
    103		output-high;
    104	};
    105};