cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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sc7280.dtsi (146941B)


      1// SPDX-License-Identifier: BSD-3-Clause
      2/*
      3 * sc7280 SoC device tree source
      4 *
      5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
      6 */
      7#include <dt-bindings/clock/qcom,camcc-sc7280.h>
      8#include <dt-bindings/clock/qcom,dispcc-sc7280.h>
      9#include <dt-bindings/clock/qcom,gcc-sc7280.h>
     10#include <dt-bindings/clock/qcom,gpucc-sc7280.h>
     11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
     12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
     13#include <dt-bindings/clock/qcom,rpmh.h>
     14#include <dt-bindings/clock/qcom,videocc-sc7280.h>
     15#include <dt-bindings/dma/qcom-gpi.h>
     16#include <dt-bindings/gpio/gpio.h>
     17#include <dt-bindings/interconnect/qcom,osm-l3.h>
     18#include <dt-bindings/interconnect/qcom,sc7280.h>
     19#include <dt-bindings/interrupt-controller/arm-gic.h>
     20#include <dt-bindings/mailbox/qcom-ipcc.h>
     21#include <dt-bindings/power/qcom-rpmpd.h>
     22#include <dt-bindings/reset/qcom,sdm845-aoss.h>
     23#include <dt-bindings/reset/qcom,sdm845-pdc.h>
     24#include <dt-bindings/soc/qcom,rpmh-rsc.h>
     25#include <dt-bindings/thermal/thermal.h>
     26
     27/ {
     28	interrupt-parent = <&intc>;
     29
     30	#address-cells = <2>;
     31	#size-cells = <2>;
     32
     33	chosen { };
     34
     35	aliases {
     36		i2c0 = &i2c0;
     37		i2c1 = &i2c1;
     38		i2c2 = &i2c2;
     39		i2c3 = &i2c3;
     40		i2c4 = &i2c4;
     41		i2c5 = &i2c5;
     42		i2c6 = &i2c6;
     43		i2c7 = &i2c7;
     44		i2c8 = &i2c8;
     45		i2c9 = &i2c9;
     46		i2c10 = &i2c10;
     47		i2c11 = &i2c11;
     48		i2c12 = &i2c12;
     49		i2c13 = &i2c13;
     50		i2c14 = &i2c14;
     51		i2c15 = &i2c15;
     52		mmc1 = &sdhc_1;
     53		mmc2 = &sdhc_2;
     54		spi0 = &spi0;
     55		spi1 = &spi1;
     56		spi2 = &spi2;
     57		spi3 = &spi3;
     58		spi4 = &spi4;
     59		spi5 = &spi5;
     60		spi6 = &spi6;
     61		spi7 = &spi7;
     62		spi8 = &spi8;
     63		spi9 = &spi9;
     64		spi10 = &spi10;
     65		spi11 = &spi11;
     66		spi12 = &spi12;
     67		spi13 = &spi13;
     68		spi14 = &spi14;
     69		spi15 = &spi15;
     70	};
     71
     72	clocks {
     73		xo_board: xo-board {
     74			compatible = "fixed-clock";
     75			clock-frequency = <76800000>;
     76			#clock-cells = <0>;
     77		};
     78
     79		sleep_clk: sleep-clk {
     80			compatible = "fixed-clock";
     81			clock-frequency = <32000>;
     82			#clock-cells = <0>;
     83		};
     84	};
     85
     86	reserved-memory {
     87		#address-cells = <2>;
     88		#size-cells = <2>;
     89		ranges;
     90
     91		wlan_ce_mem: memory@4cd000 {
     92			no-map;
     93			reg = <0x0 0x004cd000 0x0 0x1000>;
     94		};
     95
     96		hyp_mem: memory@80000000 {
     97			reg = <0x0 0x80000000 0x0 0x600000>;
     98			no-map;
     99		};
    100
    101		xbl_mem: memory@80600000 {
    102			reg = <0x0 0x80600000 0x0 0x200000>;
    103			no-map;
    104		};
    105
    106		aop_mem: memory@80800000 {
    107			reg = <0x0 0x80800000 0x0 0x60000>;
    108			no-map;
    109		};
    110
    111		aop_cmd_db_mem: memory@80860000 {
    112			reg = <0x0 0x80860000 0x0 0x20000>;
    113			compatible = "qcom,cmd-db";
    114			no-map;
    115		};
    116
    117		reserved_xbl_uefi_log: memory@80880000 {
    118			reg = <0x0 0x80884000 0x0 0x10000>;
    119			no-map;
    120		};
    121
    122		sec_apps_mem: memory@808ff000 {
    123			reg = <0x0 0x808ff000 0x0 0x1000>;
    124			no-map;
    125		};
    126
    127		smem_mem: memory@80900000 {
    128			reg = <0x0 0x80900000 0x0 0x200000>;
    129			no-map;
    130		};
    131
    132		cpucp_mem: memory@80b00000 {
    133			no-map;
    134			reg = <0x0 0x80b00000 0x0 0x100000>;
    135		};
    136
    137		wlan_fw_mem: memory@80c00000 {
    138			reg = <0x0 0x80c00000 0x0 0xc00000>;
    139			no-map;
    140		};
    141
    142		video_mem: memory@8b200000 {
    143			reg = <0x0 0x8b200000 0x0 0x500000>;
    144			no-map;
    145		};
    146
    147		ipa_fw_mem: memory@8b700000 {
    148			reg = <0 0x8b700000 0 0x10000>;
    149			no-map;
    150		};
    151
    152		rmtfs_mem: memory@9c900000 {
    153			compatible = "qcom,rmtfs-mem";
    154			reg = <0x0 0x9c900000 0x0 0x280000>;
    155			no-map;
    156
    157			qcom,client-id = <1>;
    158			qcom,vmid = <15>;
    159		};
    160	};
    161
    162	cpus {
    163		#address-cells = <2>;
    164		#size-cells = <0>;
    165
    166		CPU0: cpu@0 {
    167			device_type = "cpu";
    168			compatible = "arm,kryo";
    169			reg = <0x0 0x0>;
    170			enable-method = "psci";
    171			cpu-idle-states = <&LITTLE_CPU_SLEEP_0
    172					   &LITTLE_CPU_SLEEP_1
    173					   &CLUSTER_SLEEP_0>;
    174			next-level-cache = <&L2_0>;
    175			operating-points-v2 = <&cpu0_opp_table>;
    176			interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
    177					<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
    178			qcom,freq-domain = <&cpufreq_hw 0>;
    179			#cooling-cells = <2>;
    180			L2_0: l2-cache {
    181				compatible = "cache";
    182				next-level-cache = <&L3_0>;
    183				L3_0: l3-cache {
    184					compatible = "cache";
    185				};
    186			};
    187		};
    188
    189		CPU1: cpu@100 {
    190			device_type = "cpu";
    191			compatible = "arm,kryo";
    192			reg = <0x0 0x100>;
    193			enable-method = "psci";
    194			cpu-idle-states = <&LITTLE_CPU_SLEEP_0
    195					   &LITTLE_CPU_SLEEP_1
    196					   &CLUSTER_SLEEP_0>;
    197			next-level-cache = <&L2_100>;
    198			operating-points-v2 = <&cpu0_opp_table>;
    199			interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
    200					<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
    201			qcom,freq-domain = <&cpufreq_hw 0>;
    202			#cooling-cells = <2>;
    203			L2_100: l2-cache {
    204				compatible = "cache";
    205				next-level-cache = <&L3_0>;
    206			};
    207		};
    208
    209		CPU2: cpu@200 {
    210			device_type = "cpu";
    211			compatible = "arm,kryo";
    212			reg = <0x0 0x200>;
    213			enable-method = "psci";
    214			cpu-idle-states = <&LITTLE_CPU_SLEEP_0
    215					   &LITTLE_CPU_SLEEP_1
    216					   &CLUSTER_SLEEP_0>;
    217			next-level-cache = <&L2_200>;
    218			operating-points-v2 = <&cpu0_opp_table>;
    219			interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
    220					<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
    221			qcom,freq-domain = <&cpufreq_hw 0>;
    222			#cooling-cells = <2>;
    223			L2_200: l2-cache {
    224				compatible = "cache";
    225				next-level-cache = <&L3_0>;
    226			};
    227		};
    228
    229		CPU3: cpu@300 {
    230			device_type = "cpu";
    231			compatible = "arm,kryo";
    232			reg = <0x0 0x300>;
    233			enable-method = "psci";
    234			cpu-idle-states = <&LITTLE_CPU_SLEEP_0
    235					   &LITTLE_CPU_SLEEP_1
    236					   &CLUSTER_SLEEP_0>;
    237			next-level-cache = <&L2_300>;
    238			operating-points-v2 = <&cpu0_opp_table>;
    239			interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
    240					<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
    241			qcom,freq-domain = <&cpufreq_hw 0>;
    242			#cooling-cells = <2>;
    243			L2_300: l2-cache {
    244				compatible = "cache";
    245				next-level-cache = <&L3_0>;
    246			};
    247		};
    248
    249		CPU4: cpu@400 {
    250			device_type = "cpu";
    251			compatible = "arm,kryo";
    252			reg = <0x0 0x400>;
    253			enable-method = "psci";
    254			cpu-idle-states = <&BIG_CPU_SLEEP_0
    255					   &BIG_CPU_SLEEP_1
    256					   &CLUSTER_SLEEP_0>;
    257			next-level-cache = <&L2_400>;
    258			operating-points-v2 = <&cpu4_opp_table>;
    259			interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
    260					<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
    261			qcom,freq-domain = <&cpufreq_hw 1>;
    262			#cooling-cells = <2>;
    263			L2_400: l2-cache {
    264				compatible = "cache";
    265				next-level-cache = <&L3_0>;
    266			};
    267		};
    268
    269		CPU5: cpu@500 {
    270			device_type = "cpu";
    271			compatible = "arm,kryo";
    272			reg = <0x0 0x500>;
    273			enable-method = "psci";
    274			cpu-idle-states = <&BIG_CPU_SLEEP_0
    275					   &BIG_CPU_SLEEP_1
    276					   &CLUSTER_SLEEP_0>;
    277			next-level-cache = <&L2_500>;
    278			operating-points-v2 = <&cpu4_opp_table>;
    279			interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
    280					<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
    281			qcom,freq-domain = <&cpufreq_hw 1>;
    282			#cooling-cells = <2>;
    283			L2_500: l2-cache {
    284				compatible = "cache";
    285				next-level-cache = <&L3_0>;
    286			};
    287		};
    288
    289		CPU6: cpu@600 {
    290			device_type = "cpu";
    291			compatible = "arm,kryo";
    292			reg = <0x0 0x600>;
    293			enable-method = "psci";
    294			cpu-idle-states = <&BIG_CPU_SLEEP_0
    295					   &BIG_CPU_SLEEP_1
    296					   &CLUSTER_SLEEP_0>;
    297			next-level-cache = <&L2_600>;
    298			operating-points-v2 = <&cpu4_opp_table>;
    299			interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
    300					<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
    301			qcom,freq-domain = <&cpufreq_hw 1>;
    302			#cooling-cells = <2>;
    303			L2_600: l2-cache {
    304				compatible = "cache";
    305				next-level-cache = <&L3_0>;
    306			};
    307		};
    308
    309		CPU7: cpu@700 {
    310			device_type = "cpu";
    311			compatible = "arm,kryo";
    312			reg = <0x0 0x700>;
    313			enable-method = "psci";
    314			cpu-idle-states = <&BIG_CPU_SLEEP_0
    315					   &BIG_CPU_SLEEP_1
    316					   &CLUSTER_SLEEP_0>;
    317			next-level-cache = <&L2_700>;
    318			operating-points-v2 = <&cpu7_opp_table>;
    319			interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
    320					<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
    321			qcom,freq-domain = <&cpufreq_hw 2>;
    322			#cooling-cells = <2>;
    323			L2_700: l2-cache {
    324				compatible = "cache";
    325				next-level-cache = <&L3_0>;
    326			};
    327		};
    328
    329		cpu-map {
    330			cluster0 {
    331				core0 {
    332					cpu = <&CPU0>;
    333				};
    334
    335				core1 {
    336					cpu = <&CPU1>;
    337				};
    338
    339				core2 {
    340					cpu = <&CPU2>;
    341				};
    342
    343				core3 {
    344					cpu = <&CPU3>;
    345				};
    346
    347				core4 {
    348					cpu = <&CPU4>;
    349				};
    350
    351				core5 {
    352					cpu = <&CPU5>;
    353				};
    354
    355				core6 {
    356					cpu = <&CPU6>;
    357				};
    358
    359				core7 {
    360					cpu = <&CPU7>;
    361				};
    362			};
    363		};
    364
    365		idle-states {
    366			entry-method = "psci";
    367
    368			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
    369				compatible = "arm,idle-state";
    370				idle-state-name = "little-power-down";
    371				arm,psci-suspend-param = <0x40000003>;
    372				entry-latency-us = <549>;
    373				exit-latency-us = <901>;
    374				min-residency-us = <1774>;
    375				local-timer-stop;
    376			};
    377
    378			LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
    379				compatible = "arm,idle-state";
    380				idle-state-name = "little-rail-power-down";
    381				arm,psci-suspend-param = <0x40000004>;
    382				entry-latency-us = <702>;
    383				exit-latency-us = <915>;
    384				min-residency-us = <4001>;
    385				local-timer-stop;
    386			};
    387
    388			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
    389				compatible = "arm,idle-state";
    390				idle-state-name = "big-power-down";
    391				arm,psci-suspend-param = <0x40000003>;
    392				entry-latency-us = <523>;
    393				exit-latency-us = <1244>;
    394				min-residency-us = <2207>;
    395				local-timer-stop;
    396			};
    397
    398			BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
    399				compatible = "arm,idle-state";
    400				idle-state-name = "big-rail-power-down";
    401				arm,psci-suspend-param = <0x40000004>;
    402				entry-latency-us = <526>;
    403				exit-latency-us = <1854>;
    404				min-residency-us = <5555>;
    405				local-timer-stop;
    406			};
    407
    408			CLUSTER_SLEEP_0: cluster-sleep-0 {
    409				compatible = "arm,idle-state";
    410				idle-state-name = "cluster-power-down";
    411				arm,psci-suspend-param = <0x40003444>;
    412				entry-latency-us = <3263>;
    413				exit-latency-us = <6562>;
    414				min-residency-us = <9926>;
    415				local-timer-stop;
    416			};
    417		};
    418	};
    419
    420	cpu0_opp_table: cpu0-opp-table {
    421		compatible = "operating-points-v2";
    422		opp-shared;
    423
    424		cpu0_opp_300mhz: opp-300000000 {
    425			opp-hz = /bits/ 64 <300000000>;
    426			opp-peak-kBps = <800000 9600000>;
    427		};
    428
    429		cpu0_opp_691mhz: opp-691200000 {
    430			opp-hz = /bits/ 64 <691200000>;
    431			opp-peak-kBps = <800000 17817600>;
    432		};
    433
    434		cpu0_opp_806mhz: opp-806400000 {
    435			opp-hz = /bits/ 64 <806400000>;
    436			opp-peak-kBps = <800000 20889600>;
    437		};
    438
    439		cpu0_opp_941mhz: opp-940800000 {
    440			opp-hz = /bits/ 64 <940800000>;
    441			opp-peak-kBps = <1804000 24576000>;
    442		};
    443
    444		cpu0_opp_1152mhz: opp-1152000000 {
    445			opp-hz = /bits/ 64 <1152000000>;
    446			opp-peak-kBps = <2188000 27033600>;
    447		};
    448
    449		cpu0_opp_1325mhz: opp-1324800000 {
    450			opp-hz = /bits/ 64 <1324800000>;
    451			opp-peak-kBps = <2188000 33792000>;
    452		};
    453
    454		cpu0_opp_1517mhz: opp-1516800000 {
    455			opp-hz = /bits/ 64 <1516800000>;
    456			opp-peak-kBps = <3072000 38092800>;
    457		};
    458
    459		cpu0_opp_1651mhz: opp-1651200000 {
    460			opp-hz = /bits/ 64 <1651200000>;
    461			opp-peak-kBps = <3072000 41779200>;
    462		};
    463
    464		cpu0_opp_1805mhz: opp-1804800000 {
    465			opp-hz = /bits/ 64 <1804800000>;
    466			opp-peak-kBps = <4068000 48537600>;
    467		};
    468
    469		cpu0_opp_1958mhz: opp-1958400000 {
    470			opp-hz = /bits/ 64 <1958400000>;
    471			opp-peak-kBps = <4068000 48537600>;
    472		};
    473
    474		cpu0_opp_2016mhz: opp-2016000000 {
    475			opp-hz = /bits/ 64 <2016000000>;
    476			opp-peak-kBps = <6220000 48537600>;
    477		};
    478	};
    479
    480	cpu4_opp_table: cpu4-opp-table {
    481		compatible = "operating-points-v2";
    482		opp-shared;
    483
    484		cpu4_opp_691mhz: opp-691200000 {
    485			opp-hz = /bits/ 64 <691200000>;
    486			opp-peak-kBps = <1804000 9600000>;
    487		};
    488
    489		cpu4_opp_941mhz: opp-940800000 {
    490			opp-hz = /bits/ 64 <940800000>;
    491			opp-peak-kBps = <2188000 17817600>;
    492		};
    493
    494		cpu4_opp_1229mhz: opp-1228800000 {
    495			opp-hz = /bits/ 64 <1228800000>;
    496			opp-peak-kBps = <4068000 24576000>;
    497		};
    498
    499		cpu4_opp_1344mhz: opp-1344000000 {
    500			opp-hz = /bits/ 64 <1344000000>;
    501			opp-peak-kBps = <4068000 24576000>;
    502		};
    503
    504		cpu4_opp_1517mhz: opp-1516800000 {
    505			opp-hz = /bits/ 64 <1516800000>;
    506			opp-peak-kBps = <4068000 24576000>;
    507		};
    508
    509		cpu4_opp_1651mhz: opp-1651200000 {
    510			opp-hz = /bits/ 64 <1651200000>;
    511			opp-peak-kBps = <6220000 38092800>;
    512		};
    513
    514		cpu4_opp_1901mhz: opp-1900800000 {
    515			opp-hz = /bits/ 64 <1900800000>;
    516			opp-peak-kBps = <6220000 44851200>;
    517		};
    518
    519		cpu4_opp_2054mhz: opp-2054400000 {
    520			opp-hz = /bits/ 64 <2054400000>;
    521			opp-peak-kBps = <6220000 44851200>;
    522		};
    523
    524		cpu4_opp_2112mhz: opp-2112000000 {
    525			opp-hz = /bits/ 64 <2112000000>;
    526			opp-peak-kBps = <6220000 44851200>;
    527		};
    528
    529		cpu4_opp_2131mhz: opp-2131200000 {
    530			opp-hz = /bits/ 64 <2131200000>;
    531			opp-peak-kBps = <6220000 44851200>;
    532		};
    533
    534		cpu4_opp_2208mhz: opp-2208000000 {
    535			opp-hz = /bits/ 64 <2208000000>;
    536			opp-peak-kBps = <6220000 44851200>;
    537		};
    538
    539		cpu4_opp_2400mhz: opp-2400000000 {
    540			opp-hz = /bits/ 64 <2400000000>;
    541			opp-peak-kBps = <8532000 48537600>;
    542		};
    543
    544		cpu4_opp_2611mhz: opp-2611200000 {
    545			opp-hz = /bits/ 64 <2611200000>;
    546			opp-peak-kBps = <8532000 48537600>;
    547		};
    548	};
    549
    550	cpu7_opp_table: cpu7-opp-table {
    551		compatible = "operating-points-v2";
    552		opp-shared;
    553
    554		cpu7_opp_806mhz: opp-806400000 {
    555			opp-hz = /bits/ 64 <806400000>;
    556			opp-peak-kBps = <1804000 9600000>;
    557		};
    558
    559		cpu7_opp_1056mhz: opp-1056000000 {
    560			opp-hz = /bits/ 64 <1056000000>;
    561			opp-peak-kBps = <2188000 17817600>;
    562		};
    563
    564		cpu7_opp_1325mhz: opp-1324800000 {
    565			opp-hz = /bits/ 64 <1324800000>;
    566			opp-peak-kBps = <4068000 24576000>;
    567		};
    568
    569		cpu7_opp_1517mhz: opp-1516800000 {
    570			opp-hz = /bits/ 64 <1516800000>;
    571			opp-peak-kBps = <4068000 24576000>;
    572		};
    573
    574		cpu7_opp_1766mhz: opp-1766400000 {
    575			opp-hz = /bits/ 64 <1766400000>;
    576			opp-peak-kBps = <6220000 38092800>;
    577		};
    578
    579		cpu7_opp_1862mhz: opp-1862400000 {
    580			opp-hz = /bits/ 64 <1862400000>;
    581			opp-peak-kBps = <6220000 38092800>;
    582		};
    583
    584		cpu7_opp_2035mhz: opp-2035200000 {
    585			opp-hz = /bits/ 64 <2035200000>;
    586			opp-peak-kBps = <6220000 38092800>;
    587		};
    588
    589		cpu7_opp_2112mhz: opp-2112000000 {
    590			opp-hz = /bits/ 64 <2112000000>;
    591			opp-peak-kBps = <6220000 44851200>;
    592		};
    593
    594		cpu7_opp_2208mhz: opp-2208000000 {
    595			opp-hz = /bits/ 64 <2208000000>;
    596			opp-peak-kBps = <6220000 44851200>;
    597		};
    598
    599		cpu7_opp_2381mhz: opp-2380800000 {
    600			opp-hz = /bits/ 64 <2380800000>;
    601			opp-peak-kBps = <6832000 44851200>;
    602		};
    603
    604		cpu7_opp_2400mhz: opp-2400000000 {
    605			opp-hz = /bits/ 64 <2400000000>;
    606			opp-peak-kBps = <8532000 48537600>;
    607		};
    608
    609		cpu7_opp_2515mhz: opp-2515200000 {
    610			opp-hz = /bits/ 64 <2515200000>;
    611			opp-peak-kBps = <8532000 48537600>;
    612		};
    613
    614		cpu7_opp_2707mhz: opp-2707200000 {
    615			opp-hz = /bits/ 64 <2707200000>;
    616			opp-peak-kBps = <8532000 48537600>;
    617		};
    618
    619		cpu7_opp_3014mhz: opp-3014400000 {
    620			opp-hz = /bits/ 64 <3014400000>;
    621			opp-peak-kBps = <8532000 48537600>;
    622		};
    623	};
    624
    625	memory@80000000 {
    626		device_type = "memory";
    627		/* We expect the bootloader to fill in the size */
    628		reg = <0 0x80000000 0 0>;
    629	};
    630
    631	firmware {
    632		scm {
    633			compatible = "qcom,scm-sc7280", "qcom,scm";
    634		};
    635	};
    636
    637	clk_virt: interconnect {
    638		compatible = "qcom,sc7280-clk-virt";
    639		#interconnect-cells = <2>;
    640		qcom,bcm-voters = <&apps_bcm_voter>;
    641	};
    642
    643	smem {
    644		compatible = "qcom,smem";
    645		memory-region = <&smem_mem>;
    646		hwlocks = <&tcsr_mutex 3>;
    647	};
    648
    649	smp2p-adsp {
    650		compatible = "qcom,smp2p";
    651		qcom,smem = <443>, <429>;
    652		interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
    653					     IPCC_MPROC_SIGNAL_SMP2P
    654					     IRQ_TYPE_EDGE_RISING>;
    655		mboxes = <&ipcc IPCC_CLIENT_LPASS
    656				IPCC_MPROC_SIGNAL_SMP2P>;
    657
    658		qcom,local-pid = <0>;
    659		qcom,remote-pid = <2>;
    660
    661		adsp_smp2p_out: master-kernel {
    662			qcom,entry-name = "master-kernel";
    663			#qcom,smem-state-cells = <1>;
    664		};
    665
    666		adsp_smp2p_in: slave-kernel {
    667			qcom,entry-name = "slave-kernel";
    668			interrupt-controller;
    669			#interrupt-cells = <2>;
    670		};
    671	};
    672
    673	smp2p-cdsp {
    674		compatible = "qcom,smp2p";
    675		qcom,smem = <94>, <432>;
    676		interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
    677					     IPCC_MPROC_SIGNAL_SMP2P
    678					     IRQ_TYPE_EDGE_RISING>;
    679		mboxes = <&ipcc IPCC_CLIENT_CDSP
    680				IPCC_MPROC_SIGNAL_SMP2P>;
    681
    682		qcom,local-pid = <0>;
    683		qcom,remote-pid = <5>;
    684
    685		cdsp_smp2p_out: master-kernel {
    686			qcom,entry-name = "master-kernel";
    687			#qcom,smem-state-cells = <1>;
    688		};
    689
    690		cdsp_smp2p_in: slave-kernel {
    691			qcom,entry-name = "slave-kernel";
    692			interrupt-controller;
    693			#interrupt-cells = <2>;
    694		};
    695	};
    696
    697	smp2p-mpss {
    698		compatible = "qcom,smp2p";
    699		qcom,smem = <435>, <428>;
    700		interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
    701					     IPCC_MPROC_SIGNAL_SMP2P
    702					     IRQ_TYPE_EDGE_RISING>;
    703		mboxes = <&ipcc IPCC_CLIENT_MPSS
    704				IPCC_MPROC_SIGNAL_SMP2P>;
    705
    706		qcom,local-pid = <0>;
    707		qcom,remote-pid = <1>;
    708
    709		modem_smp2p_out: master-kernel {
    710			qcom,entry-name = "master-kernel";
    711			#qcom,smem-state-cells = <1>;
    712		};
    713
    714		modem_smp2p_in: slave-kernel {
    715			qcom,entry-name = "slave-kernel";
    716			interrupt-controller;
    717			#interrupt-cells = <2>;
    718		};
    719
    720		ipa_smp2p_out: ipa-ap-to-modem {
    721			qcom,entry-name = "ipa";
    722			#qcom,smem-state-cells = <1>;
    723		};
    724
    725		ipa_smp2p_in: ipa-modem-to-ap {
    726			qcom,entry-name = "ipa";
    727			interrupt-controller;
    728			#interrupt-cells = <2>;
    729		};
    730	};
    731
    732	smp2p-wpss {
    733		compatible = "qcom,smp2p";
    734		qcom,smem = <617>, <616>;
    735		interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
    736					     IPCC_MPROC_SIGNAL_SMP2P
    737					     IRQ_TYPE_EDGE_RISING>;
    738		mboxes = <&ipcc IPCC_CLIENT_WPSS
    739				IPCC_MPROC_SIGNAL_SMP2P>;
    740
    741		qcom,local-pid = <0>;
    742		qcom,remote-pid = <13>;
    743
    744		wpss_smp2p_out: master-kernel {
    745			qcom,entry-name = "master-kernel";
    746			#qcom,smem-state-cells = <1>;
    747		};
    748
    749		wpss_smp2p_in: slave-kernel {
    750			qcom,entry-name = "slave-kernel";
    751			interrupt-controller;
    752			#interrupt-cells = <2>;
    753		};
    754	};
    755
    756	pmu {
    757		compatible = "arm,armv8-pmuv3";
    758		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
    759	};
    760
    761	psci {
    762		compatible = "arm,psci-1.0";
    763		method = "smc";
    764	};
    765
    766	qspi_opp_table: qspi-opp-table {
    767		compatible = "operating-points-v2";
    768
    769		opp-75000000 {
    770			opp-hz = /bits/ 64 <75000000>;
    771			required-opps = <&rpmhpd_opp_low_svs>;
    772		};
    773
    774		opp-150000000 {
    775			opp-hz = /bits/ 64 <150000000>;
    776			required-opps = <&rpmhpd_opp_svs>;
    777		};
    778
    779		opp-200000000 {
    780			opp-hz = /bits/ 64 <200000000>;
    781			required-opps = <&rpmhpd_opp_svs_l1>;
    782		};
    783
    784		opp-300000000 {
    785			opp-hz = /bits/ 64 <300000000>;
    786			required-opps = <&rpmhpd_opp_nom>;
    787		};
    788	};
    789
    790	qup_opp_table: qup-opp-table {
    791		compatible = "operating-points-v2";
    792
    793		opp-75000000 {
    794			opp-hz = /bits/ 64 <75000000>;
    795			required-opps = <&rpmhpd_opp_low_svs>;
    796		};
    797
    798		opp-100000000 {
    799			opp-hz = /bits/ 64 <100000000>;
    800			required-opps = <&rpmhpd_opp_svs>;
    801		};
    802
    803		opp-128000000 {
    804			opp-hz = /bits/ 64 <128000000>;
    805			required-opps = <&rpmhpd_opp_nom>;
    806		};
    807	};
    808
    809	soc: soc@0 {
    810		#address-cells = <2>;
    811		#size-cells = <2>;
    812		ranges = <0 0 0 0 0x10 0>;
    813		dma-ranges = <0 0 0 0 0x10 0>;
    814		compatible = "simple-bus";
    815
    816		gcc: clock-controller@100000 {
    817			compatible = "qcom,gcc-sc7280";
    818			reg = <0 0x00100000 0 0x1f0000>;
    819			clocks = <&rpmhcc RPMH_CXO_CLK>,
    820				 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
    821				 <0>, <&pcie1_lane 0>,
    822				 <0>, <0>, <0>, <0>;
    823			clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
    824				      "pcie_0_pipe_clk", "pcie_1_pipe_clk",
    825				      "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
    826				      "ufs_phy_tx_symbol_0_clk",
    827				      "usb3_phy_wrapper_gcc_usb30_pipe_clk";
    828			#clock-cells = <1>;
    829			#reset-cells = <1>;
    830			#power-domain-cells = <1>;
    831		};
    832
    833		ipcc: mailbox@408000 {
    834			compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
    835			reg = <0 0x00408000 0 0x1000>;
    836			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
    837			interrupt-controller;
    838			#interrupt-cells = <3>;
    839			#mbox-cells = <2>;
    840		};
    841
    842		qfprom: efuse@784000 {
    843			compatible = "qcom,sc7280-qfprom", "qcom,qfprom";
    844			reg = <0 0x00784000 0 0xa20>,
    845			      <0 0x00780000 0 0xa20>,
    846			      <0 0x00782000 0 0x120>,
    847			      <0 0x00786000 0 0x1fff>;
    848			clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
    849			clock-names = "core";
    850			power-domains = <&rpmhpd SC7280_MX>;
    851			#address-cells = <1>;
    852			#size-cells = <1>;
    853
    854			gpu_speed_bin: gpu_speed_bin@1e9 {
    855				reg = <0x1e9 0x2>;
    856				bits = <5 8>;
    857			};
    858		};
    859
    860		sdhc_1: sdhci@7c4000 {
    861			compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
    862			pinctrl-names = "default", "sleep";
    863			pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>;
    864			pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>;
    865			status = "disabled";
    866
    867			reg = <0 0x007c4000 0 0x1000>,
    868			      <0 0x007c5000 0 0x1000>;
    869			reg-names = "hc", "cqhci";
    870
    871			iommus = <&apps_smmu 0xc0 0x0>;
    872			interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
    873				     <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>;
    874			interrupt-names = "hc_irq", "pwr_irq";
    875
    876			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
    877				 <&gcc GCC_SDCC1_AHB_CLK>,
    878				 <&rpmhcc RPMH_CXO_CLK>;
    879			clock-names = "core", "iface", "xo";
    880			interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
    881					<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>;
    882			interconnect-names = "sdhc-ddr","cpu-sdhc";
    883			power-domains = <&rpmhpd SC7280_CX>;
    884			operating-points-v2 = <&sdhc1_opp_table>;
    885
    886			bus-width = <8>;
    887			supports-cqe;
    888
    889			qcom,dll-config = <0x0007642c>;
    890			qcom,ddr-config = <0x80040868>;
    891
    892			mmc-ddr-1_8v;
    893			mmc-hs200-1_8v;
    894			mmc-hs400-1_8v;
    895			mmc-hs400-enhanced-strobe;
    896
    897			resets = <&gcc GCC_SDCC1_BCR>;
    898
    899			sdhc1_opp_table: opp-table {
    900				compatible = "operating-points-v2";
    901
    902				opp-100000000 {
    903					opp-hz = /bits/ 64 <100000000>;
    904					required-opps = <&rpmhpd_opp_low_svs>;
    905					opp-peak-kBps = <1800000 400000>;
    906					opp-avg-kBps = <100000 0>;
    907				};
    908
    909				opp-384000000 {
    910					opp-hz = /bits/ 64 <384000000>;
    911					required-opps = <&rpmhpd_opp_nom>;
    912					opp-peak-kBps = <5400000 1600000>;
    913					opp-avg-kBps = <390000 0>;
    914				};
    915			};
    916
    917		};
    918
    919		gpi_dma0: dma-controller@900000 {
    920			#dma-cells = <3>;
    921			compatible = "qcom,sc7280-gpi-dma";
    922			reg = <0 0x00900000 0 0x60000>;
    923			interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
    924				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
    925				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
    926				     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
    927				     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
    928				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
    929				     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
    930				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
    931				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
    932				     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
    933				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
    934				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
    935			dma-channels = <12>;
    936			dma-channel-mask = <0x7f>;
    937			iommus = <&apps_smmu 0x0136 0x0>;
    938			status = "disabled";
    939		};
    940
    941		qupv3_id_0: geniqup@9c0000 {
    942			compatible = "qcom,geni-se-qup";
    943			reg = <0 0x009c0000 0 0x2000>;
    944			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
    945				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
    946			clock-names = "m-ahb", "s-ahb";
    947			#address-cells = <2>;
    948			#size-cells = <2>;
    949			ranges;
    950			iommus = <&apps_smmu 0x123 0x0>;
    951			status = "disabled";
    952
    953			i2c0: i2c@980000 {
    954				compatible = "qcom,geni-i2c";
    955				reg = <0 0x00980000 0 0x4000>;
    956				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
    957				clock-names = "se";
    958				pinctrl-names = "default";
    959				pinctrl-0 = <&qup_i2c0_data_clk>;
    960				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
    961				#address-cells = <1>;
    962				#size-cells = <0>;
    963				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
    964						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
    965						<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    966				interconnect-names = "qup-core", "qup-config",
    967							"qup-memory";
    968				dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
    969				       <&gpi_dma0 1 0 QCOM_GPI_I2C>;
    970				dma-names = "tx", "rx";
    971				status = "disabled";
    972			};
    973
    974			spi0: spi@980000 {
    975				compatible = "qcom,geni-spi";
    976				reg = <0 0x00980000 0 0x4000>;
    977				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
    978				clock-names = "se";
    979				pinctrl-names = "default";
    980				pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
    981				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
    982				#address-cells = <1>;
    983				#size-cells = <0>;
    984				power-domains = <&rpmhpd SC7280_CX>;
    985				operating-points-v2 = <&qup_opp_table>;
    986				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
    987						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
    988				interconnect-names = "qup-core", "qup-config";
    989				dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
    990				       <&gpi_dma0 1 0 QCOM_GPI_SPI>;
    991				dma-names = "tx", "rx";
    992				status = "disabled";
    993			};
    994
    995			uart0: serial@980000 {
    996				compatible = "qcom,geni-uart";
    997				reg = <0 0x00980000 0 0x4000>;
    998				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
    999				clock-names = "se";
   1000				pinctrl-names = "default";
   1001				pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
   1002				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
   1003				power-domains = <&rpmhpd SC7280_CX>;
   1004				operating-points-v2 = <&qup_opp_table>;
   1005				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
   1006						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
   1007				interconnect-names = "qup-core", "qup-config";
   1008				status = "disabled";
   1009			};
   1010
   1011			i2c1: i2c@984000 {
   1012				compatible = "qcom,geni-i2c";
   1013				reg = <0 0x00984000 0 0x4000>;
   1014				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
   1015				clock-names = "se";
   1016				pinctrl-names = "default";
   1017				pinctrl-0 = <&qup_i2c1_data_clk>;
   1018				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
   1019				#address-cells = <1>;
   1020				#size-cells = <0>;
   1021				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
   1022						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
   1023						<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
   1024				interconnect-names = "qup-core", "qup-config",
   1025							"qup-memory";
   1026				dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
   1027				       <&gpi_dma0 1 1 QCOM_GPI_I2C>;
   1028				dma-names = "tx", "rx";
   1029				status = "disabled";
   1030			};
   1031
   1032			spi1: spi@984000 {
   1033				compatible = "qcom,geni-spi";
   1034				reg = <0 0x00984000 0 0x4000>;
   1035				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
   1036				clock-names = "se";
   1037				pinctrl-names = "default";
   1038				pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
   1039				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
   1040				#address-cells = <1>;
   1041				#size-cells = <0>;
   1042				power-domains = <&rpmhpd SC7280_CX>;
   1043				operating-points-v2 = <&qup_opp_table>;
   1044				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
   1045						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
   1046				interconnect-names = "qup-core", "qup-config";
   1047				dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
   1048				       <&gpi_dma0 1 1 QCOM_GPI_SPI>;
   1049				dma-names = "tx", "rx";
   1050				status = "disabled";
   1051			};
   1052
   1053			uart1: serial@984000 {
   1054				compatible = "qcom,geni-uart";
   1055				reg = <0 0x00984000 0 0x4000>;
   1056				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
   1057				clock-names = "se";
   1058				pinctrl-names = "default";
   1059				pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
   1060				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
   1061				power-domains = <&rpmhpd SC7280_CX>;
   1062				operating-points-v2 = <&qup_opp_table>;
   1063				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
   1064						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
   1065				interconnect-names = "qup-core", "qup-config";
   1066				status = "disabled";
   1067			};
   1068
   1069			i2c2: i2c@988000 {
   1070				compatible = "qcom,geni-i2c";
   1071				reg = <0 0x00988000 0 0x4000>;
   1072				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
   1073				clock-names = "se";
   1074				pinctrl-names = "default";
   1075				pinctrl-0 = <&qup_i2c2_data_clk>;
   1076				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
   1077				#address-cells = <1>;
   1078				#size-cells = <0>;
   1079				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
   1080						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
   1081						<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
   1082				interconnect-names = "qup-core", "qup-config",
   1083							"qup-memory";
   1084				dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
   1085				       <&gpi_dma0 1 2 QCOM_GPI_I2C>;
   1086				dma-names = "tx", "rx";
   1087				status = "disabled";
   1088			};
   1089
   1090			spi2: spi@988000 {
   1091				compatible = "qcom,geni-spi";
   1092				reg = <0 0x00988000 0 0x4000>;
   1093				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
   1094				clock-names = "se";
   1095				pinctrl-names = "default";
   1096				pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
   1097				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
   1098				#address-cells = <1>;
   1099				#size-cells = <0>;
   1100				power-domains = <&rpmhpd SC7280_CX>;
   1101				operating-points-v2 = <&qup_opp_table>;
   1102				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
   1103						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
   1104				interconnect-names = "qup-core", "qup-config";
   1105				dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
   1106				       <&gpi_dma0 1 2 QCOM_GPI_SPI>;
   1107				dma-names = "tx", "rx";
   1108				status = "disabled";
   1109			};
   1110
   1111			uart2: serial@988000 {
   1112				compatible = "qcom,geni-uart";
   1113				reg = <0 0x00988000 0 0x4000>;
   1114				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
   1115				clock-names = "se";
   1116				pinctrl-names = "default";
   1117				pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
   1118				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
   1119				power-domains = <&rpmhpd SC7280_CX>;
   1120				operating-points-v2 = <&qup_opp_table>;
   1121				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
   1122						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
   1123				interconnect-names = "qup-core", "qup-config";
   1124				status = "disabled";
   1125			};
   1126
   1127			i2c3: i2c@98c000 {
   1128				compatible = "qcom,geni-i2c";
   1129				reg = <0 0x0098c000 0 0x4000>;
   1130				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
   1131				clock-names = "se";
   1132				pinctrl-names = "default";
   1133				pinctrl-0 = <&qup_i2c3_data_clk>;
   1134				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
   1135				#address-cells = <1>;
   1136				#size-cells = <0>;
   1137				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
   1138						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
   1139						<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
   1140				interconnect-names = "qup-core", "qup-config",
   1141							"qup-memory";
   1142				dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
   1143				       <&gpi_dma0 1 3 QCOM_GPI_I2C>;
   1144				dma-names = "tx", "rx";
   1145				status = "disabled";
   1146			};
   1147
   1148			spi3: spi@98c000 {
   1149				compatible = "qcom,geni-spi";
   1150				reg = <0 0x0098c000 0 0x4000>;
   1151				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
   1152				clock-names = "se";
   1153				pinctrl-names = "default";
   1154				pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
   1155				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
   1156				#address-cells = <1>;
   1157				#size-cells = <0>;
   1158				power-domains = <&rpmhpd SC7280_CX>;
   1159				operating-points-v2 = <&qup_opp_table>;
   1160				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
   1161						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
   1162				interconnect-names = "qup-core", "qup-config";
   1163				dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
   1164				       <&gpi_dma0 1 3 QCOM_GPI_SPI>;
   1165				dma-names = "tx", "rx";
   1166				status = "disabled";
   1167			};
   1168
   1169			uart3: serial@98c000 {
   1170				compatible = "qcom,geni-uart";
   1171				reg = <0 0x0098c000 0 0x4000>;
   1172				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
   1173				clock-names = "se";
   1174				pinctrl-names = "default";
   1175				pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
   1176				interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
   1177				power-domains = <&rpmhpd SC7280_CX>;
   1178				operating-points-v2 = <&qup_opp_table>;
   1179				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
   1180						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
   1181				interconnect-names = "qup-core", "qup-config";
   1182				status = "disabled";
   1183			};
   1184
   1185			i2c4: i2c@990000 {
   1186				compatible = "qcom,geni-i2c";
   1187				reg = <0 0x00990000 0 0x4000>;
   1188				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
   1189				clock-names = "se";
   1190				pinctrl-names = "default";
   1191				pinctrl-0 = <&qup_i2c4_data_clk>;
   1192				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
   1193				#address-cells = <1>;
   1194				#size-cells = <0>;
   1195				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
   1196						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
   1197						<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
   1198				interconnect-names = "qup-core", "qup-config",
   1199							"qup-memory";
   1200				dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
   1201				       <&gpi_dma0 1 4 QCOM_GPI_I2C>;
   1202				dma-names = "tx", "rx";
   1203				status = "disabled";
   1204			};
   1205
   1206			spi4: spi@990000 {
   1207				compatible = "qcom,geni-spi";
   1208				reg = <0 0x00990000 0 0x4000>;
   1209				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
   1210				clock-names = "se";
   1211				pinctrl-names = "default";
   1212				pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
   1213				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
   1214				#address-cells = <1>;
   1215				#size-cells = <0>;
   1216				power-domains = <&rpmhpd SC7280_CX>;
   1217				operating-points-v2 = <&qup_opp_table>;
   1218				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
   1219						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
   1220				interconnect-names = "qup-core", "qup-config";
   1221				dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
   1222				       <&gpi_dma0 1 4 QCOM_GPI_SPI>;
   1223				dma-names = "tx", "rx";
   1224				status = "disabled";
   1225			};
   1226
   1227			uart4: serial@990000 {
   1228				compatible = "qcom,geni-uart";
   1229				reg = <0 0x00990000 0 0x4000>;
   1230				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
   1231				clock-names = "se";
   1232				pinctrl-names = "default";
   1233				pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
   1234				interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
   1235				power-domains = <&rpmhpd SC7280_CX>;
   1236				operating-points-v2 = <&qup_opp_table>;
   1237				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
   1238						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
   1239				interconnect-names = "qup-core", "qup-config";
   1240				status = "disabled";
   1241			};
   1242
   1243			i2c5: i2c@994000 {
   1244				compatible = "qcom,geni-i2c";
   1245				reg = <0 0x00994000 0 0x4000>;
   1246				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
   1247				clock-names = "se";
   1248				pinctrl-names = "default";
   1249				pinctrl-0 = <&qup_i2c5_data_clk>;
   1250				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
   1251				#address-cells = <1>;
   1252				#size-cells = <0>;
   1253				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
   1254						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
   1255						<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
   1256				interconnect-names = "qup-core", "qup-config",
   1257							"qup-memory";
   1258				dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
   1259				       <&gpi_dma0 1 5 QCOM_GPI_I2C>;
   1260				dma-names = "tx", "rx";
   1261				status = "disabled";
   1262			};
   1263
   1264			spi5: spi@994000 {
   1265				compatible = "qcom,geni-spi";
   1266				reg = <0 0x00994000 0 0x4000>;
   1267				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
   1268				clock-names = "se";
   1269				pinctrl-names = "default";
   1270				pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
   1271				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
   1272				#address-cells = <1>;
   1273				#size-cells = <0>;
   1274				power-domains = <&rpmhpd SC7280_CX>;
   1275				operating-points-v2 = <&qup_opp_table>;
   1276				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
   1277						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
   1278				interconnect-names = "qup-core", "qup-config";
   1279				dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
   1280				       <&gpi_dma0 1 5 QCOM_GPI_SPI>;
   1281				dma-names = "tx", "rx";
   1282				status = "disabled";
   1283			};
   1284
   1285			uart5: serial@994000 {
   1286				compatible = "qcom,geni-uart";
   1287				reg = <0 0x00994000 0 0x4000>;
   1288				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
   1289				clock-names = "se";
   1290				pinctrl-names = "default";
   1291				pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
   1292				interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
   1293				power-domains = <&rpmhpd SC7280_CX>;
   1294				operating-points-v2 = <&qup_opp_table>;
   1295				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
   1296						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
   1297				interconnect-names = "qup-core", "qup-config";
   1298				status = "disabled";
   1299			};
   1300
   1301			i2c6: i2c@998000 {
   1302				compatible = "qcom,geni-i2c";
   1303				reg = <0 0x00998000 0 0x4000>;
   1304				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
   1305				clock-names = "se";
   1306				pinctrl-names = "default";
   1307				pinctrl-0 = <&qup_i2c6_data_clk>;
   1308				interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
   1309				#address-cells = <1>;
   1310				#size-cells = <0>;
   1311				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
   1312						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
   1313						<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
   1314				interconnect-names = "qup-core", "qup-config",
   1315							"qup-memory";
   1316				dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
   1317				       <&gpi_dma0 1 6 QCOM_GPI_I2C>;
   1318				dma-names = "tx", "rx";
   1319				status = "disabled";
   1320			};
   1321
   1322			spi6: spi@998000 {
   1323				compatible = "qcom,geni-spi";
   1324				reg = <0 0x00998000 0 0x4000>;
   1325				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
   1326				clock-names = "se";
   1327				pinctrl-names = "default";
   1328				pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
   1329				interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
   1330				#address-cells = <1>;
   1331				#size-cells = <0>;
   1332				power-domains = <&rpmhpd SC7280_CX>;
   1333				operating-points-v2 = <&qup_opp_table>;
   1334				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
   1335						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
   1336				interconnect-names = "qup-core", "qup-config";
   1337				dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
   1338				       <&gpi_dma0 1 6 QCOM_GPI_SPI>;
   1339				dma-names = "tx", "rx";
   1340				status = "disabled";
   1341			};
   1342
   1343			uart6: serial@998000 {
   1344				compatible = "qcom,geni-uart";
   1345				reg = <0 0x00998000 0 0x4000>;
   1346				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
   1347				clock-names = "se";
   1348				pinctrl-names = "default";
   1349				pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
   1350				interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
   1351				power-domains = <&rpmhpd SC7280_CX>;
   1352				operating-points-v2 = <&qup_opp_table>;
   1353				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
   1354						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
   1355				interconnect-names = "qup-core", "qup-config";
   1356				status = "disabled";
   1357			};
   1358
   1359			i2c7: i2c@99c000 {
   1360				compatible = "qcom,geni-i2c";
   1361				reg = <0 0x0099c000 0 0x4000>;
   1362				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
   1363				clock-names = "se";
   1364				pinctrl-names = "default";
   1365				pinctrl-0 = <&qup_i2c7_data_clk>;
   1366				interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
   1367				#address-cells = <1>;
   1368				#size-cells = <0>;
   1369				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
   1370						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
   1371						<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
   1372				interconnect-names = "qup-core", "qup-config",
   1373							"qup-memory";
   1374				dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
   1375				       <&gpi_dma0 1 7 QCOM_GPI_I2C>;
   1376				dma-names = "tx", "rx";
   1377				status = "disabled";
   1378			};
   1379
   1380			spi7: spi@99c000 {
   1381				compatible = "qcom,geni-spi";
   1382				reg = <0 0x0099c000 0 0x4000>;
   1383				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
   1384				clock-names = "se";
   1385				pinctrl-names = "default";
   1386				pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
   1387				interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
   1388				#address-cells = <1>;
   1389				#size-cells = <0>;
   1390				power-domains = <&rpmhpd SC7280_CX>;
   1391				operating-points-v2 = <&qup_opp_table>;
   1392				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
   1393						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
   1394				interconnect-names = "qup-core", "qup-config";
   1395				dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
   1396				       <&gpi_dma0 1 7 QCOM_GPI_SPI>;
   1397				dma-names = "tx", "rx";
   1398				status = "disabled";
   1399			};
   1400
   1401			uart7: serial@99c000 {
   1402				compatible = "qcom,geni-uart";
   1403				reg = <0 0x0099c000 0 0x4000>;
   1404				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
   1405				clock-names = "se";
   1406				pinctrl-names = "default";
   1407				pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
   1408				interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
   1409				power-domains = <&rpmhpd SC7280_CX>;
   1410				operating-points-v2 = <&qup_opp_table>;
   1411				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
   1412						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
   1413				interconnect-names = "qup-core", "qup-config";
   1414				status = "disabled";
   1415			};
   1416		};
   1417
   1418		gpi_dma1: dma-controller@a00000 {
   1419			#dma-cells = <3>;
   1420			compatible = "qcom,sc7280-gpi-dma";
   1421			reg = <0 0x00a00000 0 0x60000>;
   1422			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
   1423				     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
   1424				     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
   1425				     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
   1426				     <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
   1427				     <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
   1428				     <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
   1429				     <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
   1430				     <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
   1431				     <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
   1432				     <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
   1433				     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
   1434			dma-channels = <12>;
   1435			dma-channel-mask = <0x1e>;
   1436			iommus = <&apps_smmu 0x56 0x0>;
   1437			status = "disabled";
   1438		};
   1439
   1440		qupv3_id_1: geniqup@ac0000 {
   1441			compatible = "qcom,geni-se-qup";
   1442			reg = <0 0x00ac0000 0 0x2000>;
   1443			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
   1444				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
   1445			clock-names = "m-ahb", "s-ahb";
   1446			#address-cells = <2>;
   1447			#size-cells = <2>;
   1448			ranges;
   1449			iommus = <&apps_smmu 0x43 0x0>;
   1450			status = "disabled";
   1451
   1452			i2c8: i2c@a80000 {
   1453				compatible = "qcom,geni-i2c";
   1454				reg = <0 0x00a80000 0 0x4000>;
   1455				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
   1456				clock-names = "se";
   1457				pinctrl-names = "default";
   1458				pinctrl-0 = <&qup_i2c8_data_clk>;
   1459				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
   1460				#address-cells = <1>;
   1461				#size-cells = <0>;
   1462				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
   1463						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
   1464						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
   1465				interconnect-names = "qup-core", "qup-config",
   1466							"qup-memory";
   1467				dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
   1468				       <&gpi_dma1 1 0 QCOM_GPI_I2C>;
   1469				dma-names = "tx", "rx";
   1470				status = "disabled";
   1471			};
   1472
   1473			spi8: spi@a80000 {
   1474				compatible = "qcom,geni-spi";
   1475				reg = <0 0x00a80000 0 0x4000>;
   1476				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
   1477				clock-names = "se";
   1478				pinctrl-names = "default";
   1479				pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
   1480				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
   1481				#address-cells = <1>;
   1482				#size-cells = <0>;
   1483				power-domains = <&rpmhpd SC7280_CX>;
   1484				operating-points-v2 = <&qup_opp_table>;
   1485				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
   1486						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
   1487				interconnect-names = "qup-core", "qup-config";
   1488				dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
   1489				       <&gpi_dma1 1 0 QCOM_GPI_SPI>;
   1490				dma-names = "tx", "rx";
   1491				status = "disabled";
   1492			};
   1493
   1494			uart8: serial@a80000 {
   1495				compatible = "qcom,geni-uart";
   1496				reg = <0 0x00a80000 0 0x4000>;
   1497				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
   1498				clock-names = "se";
   1499				pinctrl-names = "default";
   1500				pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
   1501				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
   1502				power-domains = <&rpmhpd SC7280_CX>;
   1503				operating-points-v2 = <&qup_opp_table>;
   1504				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
   1505						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
   1506				interconnect-names = "qup-core", "qup-config";
   1507				status = "disabled";
   1508			};
   1509
   1510			i2c9: i2c@a84000 {
   1511				compatible = "qcom,geni-i2c";
   1512				reg = <0 0x00a84000 0 0x4000>;
   1513				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
   1514				clock-names = "se";
   1515				pinctrl-names = "default";
   1516				pinctrl-0 = <&qup_i2c9_data_clk>;
   1517				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
   1518				#address-cells = <1>;
   1519				#size-cells = <0>;
   1520				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
   1521						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
   1522						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
   1523				interconnect-names = "qup-core", "qup-config",
   1524							"qup-memory";
   1525				dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
   1526				       <&gpi_dma1 1 1 QCOM_GPI_I2C>;
   1527				dma-names = "tx", "rx";
   1528				status = "disabled";
   1529			};
   1530
   1531			spi9: spi@a84000 {
   1532				compatible = "qcom,geni-spi";
   1533				reg = <0 0x00a84000 0 0x4000>;
   1534				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
   1535				clock-names = "se";
   1536				pinctrl-names = "default";
   1537				pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
   1538				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
   1539				#address-cells = <1>;
   1540				#size-cells = <0>;
   1541				power-domains = <&rpmhpd SC7280_CX>;
   1542				operating-points-v2 = <&qup_opp_table>;
   1543				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
   1544						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
   1545				interconnect-names = "qup-core", "qup-config";
   1546				dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
   1547				       <&gpi_dma1 1 1 QCOM_GPI_SPI>;
   1548				dma-names = "tx", "rx";
   1549				status = "disabled";
   1550			};
   1551
   1552			uart9: serial@a84000 {
   1553				compatible = "qcom,geni-uart";
   1554				reg = <0 0x00a84000 0 0x4000>;
   1555				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
   1556				clock-names = "se";
   1557				pinctrl-names = "default";
   1558				pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
   1559				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
   1560				power-domains = <&rpmhpd SC7280_CX>;
   1561				operating-points-v2 = <&qup_opp_table>;
   1562				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
   1563						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
   1564				interconnect-names = "qup-core", "qup-config";
   1565				status = "disabled";
   1566			};
   1567
   1568			i2c10: i2c@a88000 {
   1569				compatible = "qcom,geni-i2c";
   1570				reg = <0 0x00a88000 0 0x4000>;
   1571				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
   1572				clock-names = "se";
   1573				pinctrl-names = "default";
   1574				pinctrl-0 = <&qup_i2c10_data_clk>;
   1575				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
   1576				#address-cells = <1>;
   1577				#size-cells = <0>;
   1578				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
   1579						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
   1580						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
   1581				interconnect-names = "qup-core", "qup-config",
   1582							"qup-memory";
   1583				dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
   1584				       <&gpi_dma1 1 2 QCOM_GPI_I2C>;
   1585				dma-names = "tx", "rx";
   1586				status = "disabled";
   1587			};
   1588
   1589			spi10: spi@a88000 {
   1590				compatible = "qcom,geni-spi";
   1591				reg = <0 0x00a88000 0 0x4000>;
   1592				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
   1593				clock-names = "se";
   1594				pinctrl-names = "default";
   1595				pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
   1596				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
   1597				#address-cells = <1>;
   1598				#size-cells = <0>;
   1599				power-domains = <&rpmhpd SC7280_CX>;
   1600				operating-points-v2 = <&qup_opp_table>;
   1601				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
   1602						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
   1603				interconnect-names = "qup-core", "qup-config";
   1604				dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
   1605				       <&gpi_dma1 1 2 QCOM_GPI_SPI>;
   1606				dma-names = "tx", "rx";
   1607				status = "disabled";
   1608			};
   1609
   1610			uart10: serial@a88000 {
   1611				compatible = "qcom,geni-uart";
   1612				reg = <0 0x00a88000 0 0x4000>;
   1613				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
   1614				clock-names = "se";
   1615				pinctrl-names = "default";
   1616				pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
   1617				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
   1618				power-domains = <&rpmhpd SC7280_CX>;
   1619				operating-points-v2 = <&qup_opp_table>;
   1620				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
   1621						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
   1622				interconnect-names = "qup-core", "qup-config";
   1623				status = "disabled";
   1624			};
   1625
   1626			i2c11: i2c@a8c000 {
   1627				compatible = "qcom,geni-i2c";
   1628				reg = <0 0x00a8c000 0 0x4000>;
   1629				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
   1630				clock-names = "se";
   1631				pinctrl-names = "default";
   1632				pinctrl-0 = <&qup_i2c11_data_clk>;
   1633				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
   1634				#address-cells = <1>;
   1635				#size-cells = <0>;
   1636				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
   1637						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
   1638						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
   1639				interconnect-names = "qup-core", "qup-config",
   1640							"qup-memory";
   1641				dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
   1642				       <&gpi_dma1 1 3 QCOM_GPI_I2C>;
   1643				dma-names = "tx", "rx";
   1644				status = "disabled";
   1645			};
   1646
   1647			spi11: spi@a8c000 {
   1648				compatible = "qcom,geni-spi";
   1649				reg = <0 0x00a8c000 0 0x4000>;
   1650				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
   1651				clock-names = "se";
   1652				pinctrl-names = "default";
   1653				pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
   1654				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
   1655				#address-cells = <1>;
   1656				#size-cells = <0>;
   1657				power-domains = <&rpmhpd SC7280_CX>;
   1658				operating-points-v2 = <&qup_opp_table>;
   1659				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
   1660						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
   1661				interconnect-names = "qup-core", "qup-config";
   1662				dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
   1663				       <&gpi_dma1 1 3 QCOM_GPI_SPI>;
   1664				dma-names = "tx", "rx";
   1665				status = "disabled";
   1666			};
   1667
   1668			uart11: serial@a8c000 {
   1669				compatible = "qcom,geni-uart";
   1670				reg = <0 0x00a8c000 0 0x4000>;
   1671				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
   1672				clock-names = "se";
   1673				pinctrl-names = "default";
   1674				pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
   1675				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
   1676				power-domains = <&rpmhpd SC7280_CX>;
   1677				operating-points-v2 = <&qup_opp_table>;
   1678				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
   1679						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
   1680				interconnect-names = "qup-core", "qup-config";
   1681				status = "disabled";
   1682			};
   1683
   1684			i2c12: i2c@a90000 {
   1685				compatible = "qcom,geni-i2c";
   1686				reg = <0 0x00a90000 0 0x4000>;
   1687				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
   1688				clock-names = "se";
   1689				pinctrl-names = "default";
   1690				pinctrl-0 = <&qup_i2c12_data_clk>;
   1691				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
   1692				#address-cells = <1>;
   1693				#size-cells = <0>;
   1694				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
   1695						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
   1696						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
   1697				interconnect-names = "qup-core", "qup-config",
   1698							"qup-memory";
   1699				dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
   1700				       <&gpi_dma1 1 4 QCOM_GPI_I2C>;
   1701				dma-names = "tx", "rx";
   1702				status = "disabled";
   1703			};
   1704
   1705			spi12: spi@a90000 {
   1706				compatible = "qcom,geni-spi";
   1707				reg = <0 0x00a90000 0 0x4000>;
   1708				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
   1709				clock-names = "se";
   1710				pinctrl-names = "default";
   1711				pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
   1712				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
   1713				#address-cells = <1>;
   1714				#size-cells = <0>;
   1715				power-domains = <&rpmhpd SC7280_CX>;
   1716				operating-points-v2 = <&qup_opp_table>;
   1717				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
   1718						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
   1719				interconnect-names = "qup-core", "qup-config";
   1720				dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
   1721				       <&gpi_dma1 1 4 QCOM_GPI_SPI>;
   1722				dma-names = "tx", "rx";
   1723				status = "disabled";
   1724			};
   1725
   1726			uart12: serial@a90000 {
   1727				compatible = "qcom,geni-uart";
   1728				reg = <0 0x00a90000 0 0x4000>;
   1729				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
   1730				clock-names = "se";
   1731				pinctrl-names = "default";
   1732				pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
   1733				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
   1734				power-domains = <&rpmhpd SC7280_CX>;
   1735				operating-points-v2 = <&qup_opp_table>;
   1736				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
   1737						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
   1738				interconnect-names = "qup-core", "qup-config";
   1739				status = "disabled";
   1740			};
   1741
   1742			i2c13: i2c@a94000 {
   1743				compatible = "qcom,geni-i2c";
   1744				reg = <0 0x00a94000 0 0x4000>;
   1745				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
   1746				clock-names = "se";
   1747				pinctrl-names = "default";
   1748				pinctrl-0 = <&qup_i2c13_data_clk>;
   1749				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
   1750				#address-cells = <1>;
   1751				#size-cells = <0>;
   1752				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
   1753						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
   1754						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
   1755				interconnect-names = "qup-core", "qup-config",
   1756							"qup-memory";
   1757				dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
   1758				       <&gpi_dma1 1 5 QCOM_GPI_I2C>;
   1759				dma-names = "tx", "rx";
   1760				status = "disabled";
   1761			};
   1762
   1763			spi13: spi@a94000 {
   1764				compatible = "qcom,geni-spi";
   1765				reg = <0 0x00a94000 0 0x4000>;
   1766				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
   1767				clock-names = "se";
   1768				pinctrl-names = "default";
   1769				pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
   1770				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
   1771				#address-cells = <1>;
   1772				#size-cells = <0>;
   1773				power-domains = <&rpmhpd SC7280_CX>;
   1774				operating-points-v2 = <&qup_opp_table>;
   1775				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
   1776						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
   1777				interconnect-names = "qup-core", "qup-config";
   1778				dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
   1779				       <&gpi_dma1 1 5 QCOM_GPI_SPI>;
   1780				dma-names = "tx", "rx";
   1781				status = "disabled";
   1782			};
   1783
   1784			uart13: serial@a94000 {
   1785				compatible = "qcom,geni-uart";
   1786				reg = <0 0x00a94000 0 0x4000>;
   1787				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
   1788				clock-names = "se";
   1789				pinctrl-names = "default";
   1790				pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
   1791				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
   1792				power-domains = <&rpmhpd SC7280_CX>;
   1793				operating-points-v2 = <&qup_opp_table>;
   1794				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
   1795						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
   1796				interconnect-names = "qup-core", "qup-config";
   1797				status = "disabled";
   1798			};
   1799
   1800			i2c14: i2c@a98000 {
   1801				compatible = "qcom,geni-i2c";
   1802				reg = <0 0x00a98000 0 0x4000>;
   1803				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
   1804				clock-names = "se";
   1805				pinctrl-names = "default";
   1806				pinctrl-0 = <&qup_i2c14_data_clk>;
   1807				interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
   1808				#address-cells = <1>;
   1809				#size-cells = <0>;
   1810				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
   1811						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
   1812						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
   1813				interconnect-names = "qup-core", "qup-config",
   1814							"qup-memory";
   1815				dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
   1816				       <&gpi_dma1 1 6 QCOM_GPI_I2C>;
   1817				dma-names = "tx", "rx";
   1818				status = "disabled";
   1819			};
   1820
   1821			spi14: spi@a98000 {
   1822				compatible = "qcom,geni-spi";
   1823				reg = <0 0x00a98000 0 0x4000>;
   1824				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
   1825				clock-names = "se";
   1826				pinctrl-names = "default";
   1827				pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
   1828				interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
   1829				#address-cells = <1>;
   1830				#size-cells = <0>;
   1831				power-domains = <&rpmhpd SC7280_CX>;
   1832				operating-points-v2 = <&qup_opp_table>;
   1833				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
   1834						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
   1835				interconnect-names = "qup-core", "qup-config";
   1836				dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
   1837				       <&gpi_dma1 1 6 QCOM_GPI_SPI>;
   1838				dma-names = "tx", "rx";
   1839				status = "disabled";
   1840			};
   1841
   1842			uart14: serial@a98000 {
   1843				compatible = "qcom,geni-uart";
   1844				reg = <0 0x00a98000 0 0x4000>;
   1845				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
   1846				clock-names = "se";
   1847				pinctrl-names = "default";
   1848				pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
   1849				interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
   1850				power-domains = <&rpmhpd SC7280_CX>;
   1851				operating-points-v2 = <&qup_opp_table>;
   1852				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
   1853						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
   1854				interconnect-names = "qup-core", "qup-config";
   1855				status = "disabled";
   1856			};
   1857
   1858			i2c15: i2c@a9c000 {
   1859				compatible = "qcom,geni-i2c";
   1860				reg = <0 0x00a9c000 0 0x4000>;
   1861				clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
   1862				clock-names = "se";
   1863				pinctrl-names = "default";
   1864				pinctrl-0 = <&qup_i2c15_data_clk>;
   1865				interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
   1866				#address-cells = <1>;
   1867				#size-cells = <0>;
   1868				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
   1869						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
   1870						<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
   1871				interconnect-names = "qup-core", "qup-config",
   1872							"qup-memory";
   1873				dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
   1874				       <&gpi_dma1 1 7 QCOM_GPI_I2C>;
   1875				dma-names = "tx", "rx";
   1876				status = "disabled";
   1877			};
   1878
   1879			spi15: spi@a9c000 {
   1880				compatible = "qcom,geni-spi";
   1881				reg = <0 0x00a9c000 0 0x4000>;
   1882				clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
   1883				clock-names = "se";
   1884				pinctrl-names = "default";
   1885				pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
   1886				interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
   1887				#address-cells = <1>;
   1888				#size-cells = <0>;
   1889				power-domains = <&rpmhpd SC7280_CX>;
   1890				operating-points-v2 = <&qup_opp_table>;
   1891				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
   1892						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
   1893				interconnect-names = "qup-core", "qup-config";
   1894				dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
   1895				       <&gpi_dma1 1 7 QCOM_GPI_SPI>;
   1896				dma-names = "tx", "rx";
   1897				status = "disabled";
   1898			};
   1899
   1900			uart15: serial@a9c000 {
   1901				compatible = "qcom,geni-uart";
   1902				reg = <0 0x00a9c000 0 0x4000>;
   1903				clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
   1904				clock-names = "se";
   1905				pinctrl-names = "default";
   1906				pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
   1907				interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
   1908				power-domains = <&rpmhpd SC7280_CX>;
   1909				operating-points-v2 = <&qup_opp_table>;
   1910				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
   1911						<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
   1912				interconnect-names = "qup-core", "qup-config";
   1913				status = "disabled";
   1914			};
   1915		};
   1916
   1917		cnoc2: interconnect@1500000 {
   1918			reg = <0 0x01500000 0 0x1000>;
   1919			compatible = "qcom,sc7280-cnoc2";
   1920			#interconnect-cells = <2>;
   1921			qcom,bcm-voters = <&apps_bcm_voter>;
   1922		};
   1923
   1924		cnoc3: interconnect@1502000 {
   1925			reg = <0 0x01502000 0 0x1000>;
   1926			compatible = "qcom,sc7280-cnoc3";
   1927			#interconnect-cells = <2>;
   1928			qcom,bcm-voters = <&apps_bcm_voter>;
   1929		};
   1930
   1931		mc_virt: interconnect@1580000 {
   1932			reg = <0 0x01580000 0 0x4>;
   1933			compatible = "qcom,sc7280-mc-virt";
   1934			#interconnect-cells = <2>;
   1935			qcom,bcm-voters = <&apps_bcm_voter>;
   1936		};
   1937
   1938		system_noc: interconnect@1680000 {
   1939			reg = <0 0x01680000 0 0x15480>;
   1940			compatible = "qcom,sc7280-system-noc";
   1941			#interconnect-cells = <2>;
   1942			qcom,bcm-voters = <&apps_bcm_voter>;
   1943		};
   1944
   1945		aggre1_noc: interconnect@16e0000 {
   1946			compatible = "qcom,sc7280-aggre1-noc";
   1947			reg = <0 0x016e0000 0 0x1c080>;
   1948			#interconnect-cells = <2>;
   1949			qcom,bcm-voters = <&apps_bcm_voter>;
   1950		};
   1951
   1952		aggre2_noc: interconnect@1700000 {
   1953			reg = <0 0x01700000 0 0x2b080>;
   1954			compatible = "qcom,sc7280-aggre2-noc";
   1955			#interconnect-cells = <2>;
   1956			qcom,bcm-voters = <&apps_bcm_voter>;
   1957		};
   1958
   1959		mmss_noc: interconnect@1740000 {
   1960			reg = <0 0x01740000 0 0x1e080>;
   1961			compatible = "qcom,sc7280-mmss-noc";
   1962			#interconnect-cells = <2>;
   1963			qcom,bcm-voters = <&apps_bcm_voter>;
   1964		};
   1965
   1966		wifi: wifi@17a10040 {
   1967			compatible = "qcom,wcn6750-wifi";
   1968			reg = <0 0x17a10040 0 0x0>;
   1969			iommus = <&apps_smmu 0x1c00 0x1>;
   1970			interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
   1971				     <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
   1972				     <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
   1973				     <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
   1974				     <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
   1975				     <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
   1976				     <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
   1977				     <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
   1978				     <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
   1979				     <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
   1980				     <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
   1981				     <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
   1982				     <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
   1983				     <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
   1984				     <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
   1985				     <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
   1986				     <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
   1987				     <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
   1988				     <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
   1989				     <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
   1990				     <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
   1991				     <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
   1992				     <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
   1993				     <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
   1994				     <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
   1995				     <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
   1996				     <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
   1997				     <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
   1998				     <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
   1999				     <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
   2000				     <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
   2001				     <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
   2002			qcom,rproc = <&remoteproc_wpss>;
   2003			memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>;
   2004			status = "disabled";
   2005		};
   2006
   2007		pcie1: pci@1c08000 {
   2008			compatible = "qcom,pcie-sc7280";
   2009			reg = <0 0x01c08000 0 0x3000>,
   2010			      <0 0x40000000 0 0xf1d>,
   2011			      <0 0x40000f20 0 0xa8>,
   2012			      <0 0x40001000 0 0x1000>,
   2013			      <0 0x40100000 0 0x100000>;
   2014
   2015			reg-names = "parf", "dbi", "elbi", "atu", "config";
   2016			device_type = "pci";
   2017			linux,pci-domain = <1>;
   2018			bus-range = <0x00 0xff>;
   2019			num-lanes = <2>;
   2020
   2021			#address-cells = <3>;
   2022			#size-cells = <2>;
   2023
   2024			ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
   2025				 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
   2026
   2027			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
   2028			interrupt-names = "msi";
   2029			#interrupt-cells = <1>;
   2030			interrupt-map-mask = <0 0 0 0x7>;
   2031			interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
   2032					<0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
   2033					<0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
   2034					<0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
   2035
   2036			clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
   2037				 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
   2038				 <&pcie1_lane 0>,
   2039				 <&rpmhcc RPMH_CXO_CLK>,
   2040				 <&gcc GCC_PCIE_1_AUX_CLK>,
   2041				 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
   2042				 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
   2043				 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
   2044				 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
   2045				 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
   2046				 <&gcc GCC_DDRSS_PCIE_SF_CLK>;
   2047
   2048			clock-names = "pipe",
   2049				      "pipe_mux",
   2050				      "phy_pipe",
   2051				      "ref",
   2052				      "aux",
   2053				      "cfg",
   2054				      "bus_master",
   2055				      "bus_slave",
   2056				      "slave_q2a",
   2057				      "tbu",
   2058				      "ddrss_sf_tbu";
   2059
   2060			assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
   2061			assigned-clock-rates = <19200000>;
   2062
   2063			resets = <&gcc GCC_PCIE_1_BCR>;
   2064			reset-names = "pci";
   2065
   2066			power-domains = <&gcc GCC_PCIE_1_GDSC>;
   2067
   2068			phys = <&pcie1_lane>;
   2069			phy-names = "pciephy";
   2070
   2071			pinctrl-names = "default";
   2072			pinctrl-0 = <&pcie1_clkreq_n>;
   2073
   2074			iommus = <&apps_smmu 0x1c80 0x1>;
   2075
   2076			iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
   2077				    <0x100 &apps_smmu 0x1c81 0x1>;
   2078
   2079			status = "disabled";
   2080		};
   2081
   2082		pcie1_phy: phy@1c0e000 {
   2083			compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
   2084			reg = <0 0x01c0e000 0 0x1c0>;
   2085			#address-cells = <2>;
   2086			#size-cells = <2>;
   2087			ranges;
   2088			clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
   2089				 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
   2090				 <&gcc GCC_PCIE_CLKREF_EN>,
   2091				 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
   2092			clock-names = "aux", "cfg_ahb", "ref", "refgen";
   2093
   2094			resets = <&gcc GCC_PCIE_1_PHY_BCR>;
   2095			reset-names = "phy";
   2096
   2097			assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
   2098			assigned-clock-rates = <100000000>;
   2099
   2100			status = "disabled";
   2101
   2102			pcie1_lane: phy@1c0e200 {
   2103				reg = <0 0x01c0e200 0 0x170>,
   2104				      <0 0x01c0e400 0 0x200>,
   2105				      <0 0x01c0ea00 0 0x1f0>,
   2106				      <0 0x01c0e600 0 0x170>,
   2107				      <0 0x01c0e800 0 0x200>,
   2108				      <0 0x01c0ee00 0 0xf4>;
   2109				clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
   2110				clock-names = "pipe0";
   2111
   2112				#phy-cells = <0>;
   2113				#clock-cells = <1>;
   2114				clock-output-names = "pcie_1_pipe_clk";
   2115			};
   2116		};
   2117
   2118		ipa: ipa@1e40000 {
   2119			compatible = "qcom,sc7280-ipa";
   2120
   2121			iommus = <&apps_smmu 0x480 0x0>,
   2122				 <&apps_smmu 0x482 0x0>;
   2123			reg = <0 0x1e40000 0 0x8000>,
   2124			      <0 0x1e50000 0 0x4ad0>,
   2125			      <0 0x1e04000 0 0x23000>;
   2126			reg-names = "ipa-reg",
   2127				    "ipa-shared",
   2128				    "gsi";
   2129
   2130			interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
   2131					      <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
   2132					      <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
   2133					      <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
   2134			interrupt-names = "ipa",
   2135					  "gsi",
   2136					  "ipa-clock-query",
   2137					  "ipa-setup-ready";
   2138
   2139			clocks = <&rpmhcc RPMH_IPA_CLK>;
   2140			clock-names = "core";
   2141
   2142			interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
   2143					<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>;
   2144			interconnect-names = "memory",
   2145					     "config";
   2146
   2147			qcom,qmp = <&aoss_qmp>;
   2148
   2149			qcom,smem-states = <&ipa_smp2p_out 0>,
   2150					   <&ipa_smp2p_out 1>;
   2151			qcom,smem-state-names = "ipa-clock-enabled-valid",
   2152						"ipa-clock-enabled";
   2153
   2154			status = "disabled";
   2155		};
   2156
   2157		tcsr_mutex: hwlock@1f40000 {
   2158			compatible = "qcom,tcsr-mutex", "syscon";
   2159			reg = <0 0x01f40000 0 0x40000>;
   2160			#hwlock-cells = <1>;
   2161		};
   2162
   2163		tcsr: syscon@1fc0000 {
   2164			compatible = "qcom,sc7280-tcsr", "syscon";
   2165			reg = <0 0x01fc0000 0 0x30000>;
   2166		};
   2167
   2168		lpasscc: lpasscc@3000000 {
   2169			compatible = "qcom,sc7280-lpasscc";
   2170			reg = <0 0x03000000 0 0x40>,
   2171			      <0 0x03c04000 0 0x4>,
   2172			      <0 0x03389000 0 0x24>;
   2173			reg-names = "qdsp6ss", "top_cc", "cc";
   2174			clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
   2175			clock-names = "iface";
   2176			#clock-cells = <1>;
   2177		};
   2178
   2179		lpass_audiocc: clock-controller@3300000 {
   2180			compatible = "qcom,sc7280-lpassaudiocc";
   2181			reg = <0 0x03300000 0 0x30000>;
   2182			clocks = <&rpmhcc RPMH_CXO_CLK>,
   2183			       <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
   2184			clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
   2185			power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
   2186			#clock-cells = <1>;
   2187			#power-domain-cells = <1>;
   2188		};
   2189
   2190		lpass_aon: clock-controller@3380000 {
   2191			compatible = "qcom,sc7280-lpassaoncc";
   2192			reg = <0 0x03380000 0 0x30000>;
   2193			clocks = <&rpmhcc RPMH_CXO_CLK>,
   2194			       <&rpmhcc RPMH_CXO_CLK_A>,
   2195			       <&lpasscore LPASS_CORE_CC_CORE_CLK>;
   2196			clock-names = "bi_tcxo", "bi_tcxo_ao", "iface";
   2197			#clock-cells = <1>;
   2198			#power-domain-cells = <1>;
   2199		};
   2200
   2201		lpasscore: clock-controller@3900000 {
   2202			compatible = "qcom,sc7280-lpasscorecc";
   2203			reg = <0 0x03900000 0 0x50000>;
   2204			clocks =  <&rpmhcc RPMH_CXO_CLK>;
   2205			clock-names = "bi_tcxo";
   2206			power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
   2207			#clock-cells = <1>;
   2208			#power-domain-cells = <1>;
   2209		};
   2210
   2211		lpass_hm: clock-controller@3c00000 {
   2212			compatible = "qcom,sc7280-lpasshm";
   2213			reg = <0 0x3c00000 0 0x28>;
   2214			clocks = <&rpmhcc RPMH_CXO_CLK>;
   2215			clock-names = "bi_tcxo";
   2216			#clock-cells = <1>;
   2217			#power-domain-cells = <1>;
   2218		};
   2219
   2220		lpass_ag_noc: interconnect@3c40000 {
   2221			reg = <0 0x03c40000 0 0xf080>;
   2222			compatible = "qcom,sc7280-lpass-ag-noc";
   2223			#interconnect-cells = <2>;
   2224			qcom,bcm-voters = <&apps_bcm_voter>;
   2225		};
   2226
   2227		gpu: gpu@3d00000 {
   2228			compatible = "qcom,adreno-635.0", "qcom,adreno";
   2229			reg = <0 0x03d00000 0 0x40000>,
   2230			      <0 0x03d9e000 0 0x1000>,
   2231			      <0 0x03d61000 0 0x800>;
   2232			reg-names = "kgsl_3d0_reg_memory",
   2233				    "cx_mem",
   2234				    "cx_dbgc";
   2235			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
   2236			iommus = <&adreno_smmu 0 0x401>;
   2237			operating-points-v2 = <&gpu_opp_table>;
   2238			qcom,gmu = <&gmu>;
   2239			interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
   2240			interconnect-names = "gfx-mem";
   2241			#cooling-cells = <2>;
   2242
   2243			nvmem-cells = <&gpu_speed_bin>;
   2244			nvmem-cell-names = "speed_bin";
   2245
   2246			gpu_opp_table: opp-table {
   2247				compatible = "operating-points-v2";
   2248
   2249				opp-315000000 {
   2250					opp-hz = /bits/ 64 <315000000>;
   2251					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
   2252					opp-peak-kBps = <1804000>;
   2253					opp-supported-hw = <0x03>;
   2254				};
   2255
   2256				opp-450000000 {
   2257					opp-hz = /bits/ 64 <450000000>;
   2258					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
   2259					opp-peak-kBps = <4068000>;
   2260					opp-supported-hw = <0x03>;
   2261				};
   2262
   2263				opp-550000000 {
   2264					opp-hz = /bits/ 64 <550000000>;
   2265					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
   2266					opp-peak-kBps = <6832000>;
   2267					opp-supported-hw = <0x03>;
   2268				};
   2269
   2270				opp-608000000 {
   2271					opp-hz = /bits/ 64 <608000000>;
   2272					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
   2273					opp-peak-kBps = <8368000>;
   2274					opp-supported-hw = <0x02>;
   2275				};
   2276
   2277				opp-700000000 {
   2278					opp-hz = /bits/ 64 <700000000>;
   2279					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
   2280					opp-peak-kBps = <8532000>;
   2281					opp-supported-hw = <0x02>;
   2282				};
   2283
   2284				opp-812000000 {
   2285					opp-hz = /bits/ 64 <812000000>;
   2286					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
   2287					opp-peak-kBps = <8532000>;
   2288					opp-supported-hw = <0x02>;
   2289				};
   2290
   2291				opp-840000000 {
   2292					opp-hz = /bits/ 64 <840000000>;
   2293					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
   2294					opp-peak-kBps = <8532000>;
   2295					opp-supported-hw = <0x02>;
   2296				};
   2297
   2298				opp-900000000 {
   2299					opp-hz = /bits/ 64 <900000000>;
   2300					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
   2301					opp-peak-kBps = <8532000>;
   2302					opp-supported-hw = <0x02>;
   2303				};
   2304			};
   2305		};
   2306
   2307		gmu: gmu@3d6a000 {
   2308			compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
   2309			reg = <0 0x03d6a000 0 0x34000>,
   2310				<0 0x3de0000 0 0x10000>,
   2311				<0 0x0b290000 0 0x10000>;
   2312			reg-names = "gmu", "rscc", "gmu_pdc";
   2313			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
   2314					<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
   2315			interrupt-names = "hfi", "gmu";
   2316			clocks = <&gpucc 5>,
   2317					<&gpucc 8>,
   2318					<&gcc GCC_DDRSS_GPU_AXI_CLK>,
   2319					<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
   2320					<&gpucc 2>,
   2321					<&gpucc 15>,
   2322					<&gpucc 11>;
   2323			clock-names = "gmu",
   2324				      "cxo",
   2325				      "axi",
   2326				      "memnoc",
   2327				      "ahb",
   2328				      "hub",
   2329				      "smmu_vote";
   2330			power-domains = <&gpucc 0>,
   2331					<&gpucc 1>;
   2332			power-domain-names = "cx",
   2333					     "gx";
   2334			iommus = <&adreno_smmu 5 0x400>;
   2335			operating-points-v2 = <&gmu_opp_table>;
   2336
   2337			gmu_opp_table: opp-table {
   2338				compatible = "operating-points-v2";
   2339
   2340				opp-200000000 {
   2341					opp-hz = /bits/ 64 <200000000>;
   2342					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
   2343				};
   2344			};
   2345		};
   2346
   2347		gpucc: clock-controller@3d90000 {
   2348			compatible = "qcom,sc7280-gpucc";
   2349			reg = <0 0x03d90000 0 0x9000>;
   2350			clocks = <&rpmhcc RPMH_CXO_CLK>,
   2351				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
   2352				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
   2353			clock-names = "bi_tcxo",
   2354				      "gcc_gpu_gpll0_clk_src",
   2355				      "gcc_gpu_gpll0_div_clk_src";
   2356			#clock-cells = <1>;
   2357			#reset-cells = <1>;
   2358			#power-domain-cells = <1>;
   2359		};
   2360
   2361		adreno_smmu: iommu@3da0000 {
   2362			compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
   2363			reg = <0 0x03da0000 0 0x20000>;
   2364			#iommu-cells = <2>;
   2365			#global-interrupts = <2>;
   2366			interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
   2367					<GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>,
   2368					<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
   2369					<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
   2370					<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
   2371					<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
   2372					<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
   2373					<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
   2374					<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
   2375					<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
   2376					<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
   2377					<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
   2378
   2379			clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
   2380					<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
   2381					<&gpucc 2>,
   2382					<&gpucc 11>,
   2383					<&gpucc 5>,
   2384					<&gpucc 15>,
   2385					<&gpucc 13>;
   2386			clock-names = "gcc_gpu_memnoc_gfx_clk",
   2387					"gcc_gpu_snoc_dvm_gfx_clk",
   2388					"gpu_cc_ahb_clk",
   2389					"gpu_cc_hlos1_vote_gpu_smmu_clk",
   2390					"gpu_cc_cx_gmu_clk",
   2391					"gpu_cc_hub_cx_int_clk",
   2392					"gpu_cc_hub_aon_clk";
   2393
   2394			power-domains = <&gpucc 0>;
   2395		};
   2396
   2397		remoteproc_mpss: remoteproc@4080000 {
   2398			compatible = "qcom,sc7280-mpss-pas";
   2399			reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>;
   2400			reg-names = "qdsp6", "rmb";
   2401
   2402			interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
   2403					      <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
   2404					      <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
   2405					      <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
   2406					      <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
   2407					      <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
   2408			interrupt-names = "wdog", "fatal", "ready", "handover",
   2409					  "stop-ack", "shutdown-ack";
   2410
   2411			clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
   2412				 <&gcc GCC_MSS_OFFLINE_AXI_CLK>,
   2413				 <&gcc GCC_MSS_SNOC_AXI_CLK>,
   2414				 <&rpmhcc RPMH_PKA_CLK>,
   2415				 <&rpmhcc RPMH_CXO_CLK>;
   2416			clock-names = "iface", "offline", "snoc_axi", "pka", "xo";
   2417
   2418			power-domains = <&rpmhpd SC7280_CX>,
   2419					<&rpmhpd SC7280_MSS>;
   2420			power-domain-names = "cx", "mss";
   2421
   2422			memory-region = <&mpss_mem>;
   2423
   2424			qcom,qmp = <&aoss_qmp>;
   2425
   2426			qcom,smem-states = <&modem_smp2p_out 0>;
   2427			qcom,smem-state-names = "stop";
   2428
   2429			resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
   2430				 <&pdc_reset PDC_MODEM_SYNC_RESET>;
   2431			reset-names = "mss_restart", "pdc_reset";
   2432
   2433			qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>;
   2434			qcom,ext-regs = <&tcsr 0x10000 0x10004 &tcsr_mutex 0x26004 0x26008>;
   2435			qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>;
   2436
   2437			status = "disabled";
   2438
   2439			glink-edge {
   2440				interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
   2441							     IPCC_MPROC_SIGNAL_GLINK_QMP
   2442							     IRQ_TYPE_EDGE_RISING>;
   2443				mboxes = <&ipcc IPCC_CLIENT_MPSS
   2444						IPCC_MPROC_SIGNAL_GLINK_QMP>;
   2445				label = "modem";
   2446				qcom,remote-pid = <1>;
   2447			};
   2448		};
   2449
   2450		stm@6002000 {
   2451			compatible = "arm,coresight-stm", "arm,primecell";
   2452			reg = <0 0x06002000 0 0x1000>,
   2453			      <0 0x16280000 0 0x180000>;
   2454			reg-names = "stm-base", "stm-stimulus-base";
   2455
   2456			clocks = <&aoss_qmp>;
   2457			clock-names = "apb_pclk";
   2458
   2459			out-ports {
   2460				port {
   2461					stm_out: endpoint {
   2462						remote-endpoint = <&funnel0_in7>;
   2463					};
   2464				};
   2465			};
   2466		};
   2467
   2468		funnel@6041000 {
   2469			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
   2470			reg = <0 0x06041000 0 0x1000>;
   2471
   2472			clocks = <&aoss_qmp>;
   2473			clock-names = "apb_pclk";
   2474
   2475			out-ports {
   2476				port {
   2477					funnel0_out: endpoint {
   2478						remote-endpoint = <&merge_funnel_in0>;
   2479					};
   2480				};
   2481			};
   2482
   2483			in-ports {
   2484				#address-cells = <1>;
   2485				#size-cells = <0>;
   2486
   2487				port@7 {
   2488					reg = <7>;
   2489					funnel0_in7: endpoint {
   2490						remote-endpoint = <&stm_out>;
   2491					};
   2492				};
   2493			};
   2494		};
   2495
   2496		funnel@6042000 {
   2497			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
   2498			reg = <0 0x06042000 0 0x1000>;
   2499
   2500			clocks = <&aoss_qmp>;
   2501			clock-names = "apb_pclk";
   2502
   2503			out-ports {
   2504				port {
   2505					funnel1_out: endpoint {
   2506						remote-endpoint = <&merge_funnel_in1>;
   2507					};
   2508				};
   2509			};
   2510
   2511			in-ports {
   2512				#address-cells = <1>;
   2513				#size-cells = <0>;
   2514
   2515				port@4 {
   2516					reg = <4>;
   2517					funnel1_in4: endpoint {
   2518						remote-endpoint = <&apss_merge_funnel_out>;
   2519					};
   2520				};
   2521			};
   2522		};
   2523
   2524		funnel@6045000 {
   2525			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
   2526			reg = <0 0x06045000 0 0x1000>;
   2527
   2528			clocks = <&aoss_qmp>;
   2529			clock-names = "apb_pclk";
   2530
   2531			out-ports {
   2532				port {
   2533					merge_funnel_out: endpoint {
   2534						remote-endpoint = <&swao_funnel_in>;
   2535					};
   2536				};
   2537			};
   2538
   2539			in-ports {
   2540				#address-cells = <1>;
   2541				#size-cells = <0>;
   2542
   2543				port@0 {
   2544					reg = <0>;
   2545					merge_funnel_in0: endpoint {
   2546						remote-endpoint = <&funnel0_out>;
   2547					};
   2548				};
   2549
   2550				port@1 {
   2551					reg = <1>;
   2552					merge_funnel_in1: endpoint {
   2553						remote-endpoint = <&funnel1_out>;
   2554					};
   2555				};
   2556			};
   2557		};
   2558
   2559		replicator@6046000 {
   2560			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
   2561			reg = <0 0x06046000 0 0x1000>;
   2562
   2563			clocks = <&aoss_qmp>;
   2564			clock-names = "apb_pclk";
   2565
   2566			out-ports {
   2567				port {
   2568					replicator_out: endpoint {
   2569						remote-endpoint = <&etr_in>;
   2570					};
   2571				};
   2572			};
   2573
   2574			in-ports {
   2575				port {
   2576					replicator_in: endpoint {
   2577						remote-endpoint = <&swao_replicator_out>;
   2578					};
   2579				};
   2580			};
   2581		};
   2582
   2583		etr@6048000 {
   2584			compatible = "arm,coresight-tmc", "arm,primecell";
   2585			reg = <0 0x06048000 0 0x1000>;
   2586			iommus = <&apps_smmu 0x04c0 0>;
   2587
   2588			clocks = <&aoss_qmp>;
   2589			clock-names = "apb_pclk";
   2590			arm,scatter-gather;
   2591
   2592			in-ports {
   2593				port {
   2594					etr_in: endpoint {
   2595						remote-endpoint = <&replicator_out>;
   2596					};
   2597				};
   2598			};
   2599		};
   2600
   2601		funnel@6b04000 {
   2602			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
   2603			reg = <0 0x06b04000 0 0x1000>;
   2604
   2605			clocks = <&aoss_qmp>;
   2606			clock-names = "apb_pclk";
   2607
   2608			out-ports {
   2609				port {
   2610					swao_funnel_out: endpoint {
   2611						remote-endpoint = <&etf_in>;
   2612					};
   2613				};
   2614			};
   2615
   2616			in-ports {
   2617				#address-cells = <1>;
   2618				#size-cells = <0>;
   2619
   2620				port@7 {
   2621					reg = <7>;
   2622					swao_funnel_in: endpoint {
   2623						remote-endpoint = <&merge_funnel_out>;
   2624					};
   2625				};
   2626			};
   2627		};
   2628
   2629		etf@6b05000 {
   2630			compatible = "arm,coresight-tmc", "arm,primecell";
   2631			reg = <0 0x06b05000 0 0x1000>;
   2632
   2633			clocks = <&aoss_qmp>;
   2634			clock-names = "apb_pclk";
   2635
   2636			out-ports {
   2637				port {
   2638					etf_out: endpoint {
   2639						remote-endpoint = <&swao_replicator_in>;
   2640					};
   2641				};
   2642			};
   2643
   2644			in-ports {
   2645				port {
   2646					etf_in: endpoint {
   2647						remote-endpoint = <&swao_funnel_out>;
   2648					};
   2649				};
   2650			};
   2651		};
   2652
   2653		replicator@6b06000 {
   2654			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
   2655			reg = <0 0x06b06000 0 0x1000>;
   2656
   2657			clocks = <&aoss_qmp>;
   2658			clock-names = "apb_pclk";
   2659			qcom,replicator-loses-context;
   2660
   2661			out-ports {
   2662				port {
   2663					swao_replicator_out: endpoint {
   2664						remote-endpoint = <&replicator_in>;
   2665					};
   2666				};
   2667			};
   2668
   2669			in-ports {
   2670				port {
   2671					swao_replicator_in: endpoint {
   2672						remote-endpoint = <&etf_out>;
   2673					};
   2674				};
   2675			};
   2676		};
   2677
   2678		etm@7040000 {
   2679			compatible = "arm,coresight-etm4x", "arm,primecell";
   2680			reg = <0 0x07040000 0 0x1000>;
   2681
   2682			cpu = <&CPU0>;
   2683
   2684			clocks = <&aoss_qmp>;
   2685			clock-names = "apb_pclk";
   2686			arm,coresight-loses-context-with-cpu;
   2687			qcom,skip-power-up;
   2688
   2689			out-ports {
   2690				port {
   2691					etm0_out: endpoint {
   2692						remote-endpoint = <&apss_funnel_in0>;
   2693					};
   2694				};
   2695			};
   2696		};
   2697
   2698		etm@7140000 {
   2699			compatible = "arm,coresight-etm4x", "arm,primecell";
   2700			reg = <0 0x07140000 0 0x1000>;
   2701
   2702			cpu = <&CPU1>;
   2703
   2704			clocks = <&aoss_qmp>;
   2705			clock-names = "apb_pclk";
   2706			arm,coresight-loses-context-with-cpu;
   2707			qcom,skip-power-up;
   2708
   2709			out-ports {
   2710				port {
   2711					etm1_out: endpoint {
   2712						remote-endpoint = <&apss_funnel_in1>;
   2713					};
   2714				};
   2715			};
   2716		};
   2717
   2718		etm@7240000 {
   2719			compatible = "arm,coresight-etm4x", "arm,primecell";
   2720			reg = <0 0x07240000 0 0x1000>;
   2721
   2722			cpu = <&CPU2>;
   2723
   2724			clocks = <&aoss_qmp>;
   2725			clock-names = "apb_pclk";
   2726			arm,coresight-loses-context-with-cpu;
   2727			qcom,skip-power-up;
   2728
   2729			out-ports {
   2730				port {
   2731					etm2_out: endpoint {
   2732						remote-endpoint = <&apss_funnel_in2>;
   2733					};
   2734				};
   2735			};
   2736		};
   2737
   2738		etm@7340000 {
   2739			compatible = "arm,coresight-etm4x", "arm,primecell";
   2740			reg = <0 0x07340000 0 0x1000>;
   2741
   2742			cpu = <&CPU3>;
   2743
   2744			clocks = <&aoss_qmp>;
   2745			clock-names = "apb_pclk";
   2746			arm,coresight-loses-context-with-cpu;
   2747			qcom,skip-power-up;
   2748
   2749			out-ports {
   2750				port {
   2751					etm3_out: endpoint {
   2752						remote-endpoint = <&apss_funnel_in3>;
   2753					};
   2754				};
   2755			};
   2756		};
   2757
   2758		etm@7440000 {
   2759			compatible = "arm,coresight-etm4x", "arm,primecell";
   2760			reg = <0 0x07440000 0 0x1000>;
   2761
   2762			cpu = <&CPU4>;
   2763
   2764			clocks = <&aoss_qmp>;
   2765			clock-names = "apb_pclk";
   2766			arm,coresight-loses-context-with-cpu;
   2767			qcom,skip-power-up;
   2768
   2769			out-ports {
   2770				port {
   2771					etm4_out: endpoint {
   2772						remote-endpoint = <&apss_funnel_in4>;
   2773					};
   2774				};
   2775			};
   2776		};
   2777
   2778		etm@7540000 {
   2779			compatible = "arm,coresight-etm4x", "arm,primecell";
   2780			reg = <0 0x07540000 0 0x1000>;
   2781
   2782			cpu = <&CPU5>;
   2783
   2784			clocks = <&aoss_qmp>;
   2785			clock-names = "apb_pclk";
   2786			arm,coresight-loses-context-with-cpu;
   2787			qcom,skip-power-up;
   2788
   2789			out-ports {
   2790				port {
   2791					etm5_out: endpoint {
   2792						remote-endpoint = <&apss_funnel_in5>;
   2793					};
   2794				};
   2795			};
   2796		};
   2797
   2798		etm@7640000 {
   2799			compatible = "arm,coresight-etm4x", "arm,primecell";
   2800			reg = <0 0x07640000 0 0x1000>;
   2801
   2802			cpu = <&CPU6>;
   2803
   2804			clocks = <&aoss_qmp>;
   2805			clock-names = "apb_pclk";
   2806			arm,coresight-loses-context-with-cpu;
   2807			qcom,skip-power-up;
   2808
   2809			out-ports {
   2810				port {
   2811					etm6_out: endpoint {
   2812						remote-endpoint = <&apss_funnel_in6>;
   2813					};
   2814				};
   2815			};
   2816		};
   2817
   2818		etm@7740000 {
   2819			compatible = "arm,coresight-etm4x", "arm,primecell";
   2820			reg = <0 0x07740000 0 0x1000>;
   2821
   2822			cpu = <&CPU7>;
   2823
   2824			clocks = <&aoss_qmp>;
   2825			clock-names = "apb_pclk";
   2826			arm,coresight-loses-context-with-cpu;
   2827			qcom,skip-power-up;
   2828
   2829			out-ports {
   2830				port {
   2831					etm7_out: endpoint {
   2832						remote-endpoint = <&apss_funnel_in7>;
   2833					};
   2834				};
   2835			};
   2836		};
   2837
   2838		funnel@7800000 { /* APSS Funnel */
   2839			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
   2840			reg = <0 0x07800000 0 0x1000>;
   2841
   2842			clocks = <&aoss_qmp>;
   2843			clock-names = "apb_pclk";
   2844
   2845			out-ports {
   2846				port {
   2847					apss_funnel_out: endpoint {
   2848						remote-endpoint = <&apss_merge_funnel_in>;
   2849					};
   2850				};
   2851			};
   2852
   2853			in-ports {
   2854				#address-cells = <1>;
   2855				#size-cells = <0>;
   2856
   2857				port@0 {
   2858					reg = <0>;
   2859					apss_funnel_in0: endpoint {
   2860						remote-endpoint = <&etm0_out>;
   2861					};
   2862				};
   2863
   2864				port@1 {
   2865					reg = <1>;
   2866					apss_funnel_in1: endpoint {
   2867						remote-endpoint = <&etm1_out>;
   2868					};
   2869				};
   2870
   2871				port@2 {
   2872					reg = <2>;
   2873					apss_funnel_in2: endpoint {
   2874						remote-endpoint = <&etm2_out>;
   2875					};
   2876				};
   2877
   2878				port@3 {
   2879					reg = <3>;
   2880					apss_funnel_in3: endpoint {
   2881						remote-endpoint = <&etm3_out>;
   2882					};
   2883				};
   2884
   2885				port@4 {
   2886					reg = <4>;
   2887					apss_funnel_in4: endpoint {
   2888						remote-endpoint = <&etm4_out>;
   2889					};
   2890				};
   2891
   2892				port@5 {
   2893					reg = <5>;
   2894					apss_funnel_in5: endpoint {
   2895						remote-endpoint = <&etm5_out>;
   2896					};
   2897				};
   2898
   2899				port@6 {
   2900					reg = <6>;
   2901					apss_funnel_in6: endpoint {
   2902						remote-endpoint = <&etm6_out>;
   2903					};
   2904				};
   2905
   2906				port@7 {
   2907					reg = <7>;
   2908					apss_funnel_in7: endpoint {
   2909						remote-endpoint = <&etm7_out>;
   2910					};
   2911				};
   2912			};
   2913		};
   2914
   2915		funnel@7810000 {
   2916			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
   2917			reg = <0 0x07810000 0 0x1000>;
   2918
   2919			clocks = <&aoss_qmp>;
   2920			clock-names = "apb_pclk";
   2921
   2922			out-ports {
   2923				port {
   2924					apss_merge_funnel_out: endpoint {
   2925						remote-endpoint = <&funnel1_in4>;
   2926					};
   2927				};
   2928			};
   2929
   2930			in-ports {
   2931				port {
   2932					apss_merge_funnel_in: endpoint {
   2933						remote-endpoint = <&apss_funnel_out>;
   2934					};
   2935				};
   2936			};
   2937		};
   2938
   2939		sdhc_2: sdhci@8804000 {
   2940			compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
   2941			pinctrl-names = "default", "sleep";
   2942			pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>;
   2943			pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>;
   2944			status = "disabled";
   2945
   2946			reg = <0 0x08804000 0 0x1000>;
   2947
   2948			iommus = <&apps_smmu 0x100 0x0>;
   2949			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
   2950				     <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
   2951			interrupt-names = "hc_irq", "pwr_irq";
   2952
   2953			clocks = <&gcc GCC_SDCC2_APPS_CLK>,
   2954				 <&gcc GCC_SDCC2_AHB_CLK>,
   2955				 <&rpmhcc RPMH_CXO_CLK>;
   2956			clock-names = "core", "iface", "xo";
   2957			interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
   2958					<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>;
   2959			interconnect-names = "sdhc-ddr","cpu-sdhc";
   2960			power-domains = <&rpmhpd SC7280_CX>;
   2961			operating-points-v2 = <&sdhc2_opp_table>;
   2962
   2963			bus-width = <4>;
   2964
   2965			qcom,dll-config = <0x0007642c>;
   2966
   2967			resets = <&gcc GCC_SDCC2_BCR>;
   2968
   2969			sdhc2_opp_table: opp-table {
   2970				compatible = "operating-points-v2";
   2971
   2972				opp-100000000 {
   2973					opp-hz = /bits/ 64 <100000000>;
   2974					required-opps = <&rpmhpd_opp_low_svs>;
   2975					opp-peak-kBps = <1800000 400000>;
   2976					opp-avg-kBps = <100000 0>;
   2977				};
   2978
   2979				opp-202000000 {
   2980					opp-hz = /bits/ 64 <202000000>;
   2981					required-opps = <&rpmhpd_opp_nom>;
   2982					opp-peak-kBps = <5400000 1600000>;
   2983					opp-avg-kBps = <200000 0>;
   2984				};
   2985			};
   2986
   2987		};
   2988
   2989		usb_1_hsphy: phy@88e3000 {
   2990			compatible = "qcom,sc7280-usb-hs-phy",
   2991				     "qcom,usb-snps-hs-7nm-phy";
   2992			reg = <0 0x088e3000 0 0x400>;
   2993			status = "disabled";
   2994			#phy-cells = <0>;
   2995
   2996			clocks = <&rpmhcc RPMH_CXO_CLK>;
   2997			clock-names = "ref";
   2998
   2999			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
   3000		};
   3001
   3002		usb_2_hsphy: phy@88e4000 {
   3003			compatible = "qcom,sc7280-usb-hs-phy",
   3004				     "qcom,usb-snps-hs-7nm-phy";
   3005			reg = <0 0x088e4000 0 0x400>;
   3006			status = "disabled";
   3007			#phy-cells = <0>;
   3008
   3009			clocks = <&rpmhcc RPMH_CXO_CLK>;
   3010			clock-names = "ref";
   3011
   3012			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
   3013		};
   3014
   3015		usb_1_qmpphy: phy-wrapper@88e9000 {
   3016			compatible = "qcom,sc7280-qmp-usb3-dp-phy",
   3017				     "qcom,sm8250-qmp-usb3-dp-phy";
   3018			reg = <0 0x088e9000 0 0x200>,
   3019			      <0 0x088e8000 0 0x40>,
   3020			      <0 0x088ea000 0 0x200>;
   3021			status = "disabled";
   3022			#address-cells = <2>;
   3023			#size-cells = <2>;
   3024			ranges;
   3025
   3026			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
   3027				 <&rpmhcc RPMH_CXO_CLK>,
   3028				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
   3029			clock-names = "aux", "ref_clk_src", "com_aux";
   3030
   3031			resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
   3032				 <&gcc GCC_USB3_PHY_PRIM_BCR>;
   3033			reset-names = "phy", "common";
   3034
   3035			usb_1_ssphy: usb3-phy@88e9200 {
   3036				reg = <0 0x088e9200 0 0x200>,
   3037				      <0 0x088e9400 0 0x200>,
   3038				      <0 0x088e9c00 0 0x400>,
   3039				      <0 0x088e9600 0 0x200>,
   3040				      <0 0x088e9800 0 0x200>,
   3041				      <0 0x088e9a00 0 0x100>;
   3042				#clock-cells = <0>;
   3043				#phy-cells = <0>;
   3044				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
   3045				clock-names = "pipe0";
   3046				clock-output-names = "usb3_phy_pipe_clk_src";
   3047			};
   3048
   3049			dp_phy: dp-phy@88ea200 {
   3050				reg = <0 0x088ea200 0 0x200>,
   3051				      <0 0x088ea400 0 0x200>,
   3052				      <0 0x088eaa00 0 0x200>,
   3053				      <0 0x088ea600 0 0x200>,
   3054				      <0 0x088ea800 0 0x200>;
   3055				#phy-cells = <0>;
   3056				#clock-cells = <1>;
   3057			};
   3058		};
   3059
   3060		usb_2: usb@8cf8800 {
   3061			compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
   3062			reg = <0 0x08cf8800 0 0x400>;
   3063			status = "disabled";
   3064			#address-cells = <2>;
   3065			#size-cells = <2>;
   3066			ranges;
   3067			dma-ranges;
   3068
   3069			clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
   3070				 <&gcc GCC_USB30_SEC_MASTER_CLK>,
   3071				 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
   3072				 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
   3073				 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
   3074			clock-names = "cfg_noc",
   3075				      "core",
   3076				      "iface",
   3077				      "sleep",
   3078				      "mock_utmi";
   3079
   3080			assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
   3081					  <&gcc GCC_USB30_SEC_MASTER_CLK>;
   3082			assigned-clock-rates = <19200000>, <200000000>;
   3083
   3084			interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
   3085				     <&pdc 13 IRQ_TYPE_EDGE_RISING>,
   3086				     <&pdc 12 IRQ_TYPE_EDGE_RISING>;
   3087			interrupt-names = "hs_phy_irq",
   3088					  "dm_hs_phy_irq", "dp_hs_phy_irq";
   3089
   3090			power-domains = <&gcc GCC_USB30_SEC_GDSC>;
   3091
   3092			resets = <&gcc GCC_USB30_SEC_BCR>;
   3093
   3094			interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
   3095					<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>;
   3096			interconnect-names = "usb-ddr", "apps-usb";
   3097
   3098			usb_2_dwc3: usb@8c00000 {
   3099				compatible = "snps,dwc3";
   3100				reg = <0 0x08c00000 0 0xe000>;
   3101				interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
   3102				iommus = <&apps_smmu 0xa0 0x0>;
   3103				snps,dis_u2_susphy_quirk;
   3104				snps,dis_enblslpm_quirk;
   3105				phys = <&usb_2_hsphy>;
   3106				phy-names = "usb2-phy";
   3107				maximum-speed = "high-speed";
   3108				usb-role-switch;
   3109				port {
   3110					usb2_role_switch: endpoint {
   3111						remote-endpoint = <&eud_ep>;
   3112					};
   3113				};
   3114			};
   3115		};
   3116
   3117		qspi: spi@88dc000 {
   3118			compatible = "qcom,sc7280-qspi", "qcom,qspi-v1";
   3119			reg = <0 0x088dc000 0 0x1000>;
   3120			#address-cells = <1>;
   3121			#size-cells = <0>;
   3122			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
   3123			clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
   3124				 <&gcc GCC_QSPI_CORE_CLK>;
   3125			clock-names = "iface", "core";
   3126			interconnects = <&gem_noc MASTER_APPSS_PROC 0
   3127					&cnoc2 SLAVE_QSPI_0 0>;
   3128			interconnect-names = "qspi-config";
   3129			power-domains = <&rpmhpd SC7280_CX>;
   3130			operating-points-v2 = <&qspi_opp_table>;
   3131			status = "disabled";
   3132		};
   3133
   3134		remoteproc_wpss: remoteproc@8a00000 {
   3135			compatible = "qcom,sc7280-wpss-pil";
   3136			reg = <0 0x08a00000 0 0x10000>;
   3137
   3138			interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
   3139					      <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
   3140					      <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
   3141					      <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
   3142					      <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
   3143					      <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
   3144			interrupt-names = "wdog", "fatal", "ready", "handover",
   3145					  "stop-ack", "shutdown-ack";
   3146
   3147			clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,
   3148				 <&gcc GCC_WPSS_AHB_CLK>,
   3149				 <&gcc GCC_WPSS_RSCP_CLK>,
   3150				 <&rpmhcc RPMH_CXO_CLK>;
   3151			clock-names = "ahb_bdg", "ahb",
   3152				      "rscp", "xo";
   3153
   3154			power-domains = <&rpmhpd SC7280_CX>,
   3155					<&rpmhpd SC7280_MX>;
   3156			power-domain-names = "cx", "mx";
   3157
   3158			memory-region = <&wpss_mem>;
   3159
   3160			qcom,qmp = <&aoss_qmp>;
   3161
   3162			qcom,smem-states = <&wpss_smp2p_out 0>;
   3163			qcom,smem-state-names = "stop";
   3164
   3165			resets = <&aoss_reset AOSS_CC_WCSS_RESTART>,
   3166				 <&pdc_reset PDC_WPSS_SYNC_RESET>;
   3167			reset-names = "restart", "pdc_sync";
   3168
   3169			qcom,halt-regs = <&tcsr_mutex 0x37000>;
   3170
   3171			status = "disabled";
   3172
   3173			glink-edge {
   3174				interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
   3175							     IPCC_MPROC_SIGNAL_GLINK_QMP
   3176							     IRQ_TYPE_EDGE_RISING>;
   3177				mboxes = <&ipcc IPCC_CLIENT_WPSS
   3178						IPCC_MPROC_SIGNAL_GLINK_QMP>;
   3179
   3180				label = "wpss";
   3181				qcom,remote-pid = <13>;
   3182			};
   3183		};
   3184
   3185		dc_noc: interconnect@90e0000 {
   3186			reg = <0 0x090e0000 0 0x5080>;
   3187			compatible = "qcom,sc7280-dc-noc";
   3188			#interconnect-cells = <2>;
   3189			qcom,bcm-voters = <&apps_bcm_voter>;
   3190		};
   3191
   3192		gem_noc: interconnect@9100000 {
   3193			reg = <0 0x9100000 0 0xe2200>;
   3194			compatible = "qcom,sc7280-gem-noc";
   3195			#interconnect-cells = <2>;
   3196			qcom,bcm-voters = <&apps_bcm_voter>;
   3197		};
   3198
   3199		system-cache-controller@9200000 {
   3200			compatible = "qcom,sc7280-llcc";
   3201			reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>;
   3202			reg-names = "llcc_base", "llcc_broadcast_base";
   3203			interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
   3204		};
   3205
   3206		eud: eud@88e0000 {
   3207			compatible = "qcom,sc7280-eud","qcom,eud";
   3208			reg = <0 0x88e0000 0 0x2000>,
   3209			      <0 0x88e2000 0 0x1000>;
   3210			interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>;
   3211			ports {
   3212				port@0 {
   3213					eud_ep: endpoint {
   3214						remote-endpoint = <&usb2_role_switch>;
   3215					};
   3216				};
   3217				port@1 {
   3218					eud_con: endpoint {
   3219						remote-endpoint = <&con_eud>;
   3220					};
   3221				};
   3222			};
   3223		};
   3224
   3225		eud_typec: connector {
   3226			compatible = "usb-c-connector";
   3227			ports {
   3228				port@0 {
   3229					con_eud: endpoint {
   3230						remote-endpoint = <&eud_con>;
   3231					};
   3232				};
   3233			};
   3234		};
   3235
   3236		nsp_noc: interconnect@a0c0000 {
   3237			reg = <0 0x0a0c0000 0 0x10000>;
   3238			compatible = "qcom,sc7280-nsp-noc";
   3239			#interconnect-cells = <2>;
   3240			qcom,bcm-voters = <&apps_bcm_voter>;
   3241		};
   3242
   3243		usb_1: usb@a6f8800 {
   3244			compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
   3245			reg = <0 0x0a6f8800 0 0x400>;
   3246			status = "disabled";
   3247			#address-cells = <2>;
   3248			#size-cells = <2>;
   3249			ranges;
   3250			dma-ranges;
   3251
   3252			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
   3253				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
   3254				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
   3255				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
   3256				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
   3257			clock-names = "cfg_noc",
   3258				      "core",
   3259				      "iface",
   3260				      "sleep",
   3261				      "mock_utmi";
   3262
   3263			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
   3264					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
   3265			assigned-clock-rates = <19200000>, <200000000>;
   3266
   3267			interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
   3268					      <&pdc 17 IRQ_TYPE_EDGE_BOTH>,
   3269					      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
   3270					      <&pdc 14 IRQ_TYPE_LEVEL_HIGH>;
   3271			interrupt-names = "hs_phy_irq",
   3272					  "ss_phy_irq",
   3273					  "dm_hs_phy_irq",
   3274					  "dp_hs_phy_irq";
   3275
   3276			power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
   3277
   3278			resets = <&gcc GCC_USB30_PRIM_BCR>;
   3279
   3280			interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
   3281					<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>;
   3282			interconnect-names = "usb-ddr", "apps-usb";
   3283
   3284			usb_1_dwc3: usb@a600000 {
   3285				compatible = "snps,dwc3";
   3286				reg = <0 0x0a600000 0 0xe000>;
   3287				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
   3288				iommus = <&apps_smmu 0xe0 0x0>;
   3289				snps,dis_u2_susphy_quirk;
   3290				snps,dis_enblslpm_quirk;
   3291				phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
   3292				phy-names = "usb2-phy", "usb3-phy";
   3293				maximum-speed = "super-speed";
   3294				wakeup-source;
   3295			};
   3296		};
   3297
   3298		venus: video-codec@aa00000 {
   3299			compatible = "qcom,sc7280-venus";
   3300			reg = <0 0x0aa00000 0 0xd0600>;
   3301			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
   3302
   3303			clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>,
   3304				 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>,
   3305				 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
   3306				 <&videocc VIDEO_CC_MVS0_CORE_CLK>,
   3307				 <&videocc VIDEO_CC_MVS0_AXI_CLK>;
   3308			clock-names = "core", "bus", "iface",
   3309				      "vcodec_core", "vcodec_bus";
   3310
   3311			power-domains = <&videocc MVSC_GDSC>,
   3312					<&videocc MVS0_GDSC>,
   3313					<&rpmhpd SC7280_CX>;
   3314			power-domain-names = "venus", "vcodec0", "cx";
   3315			operating-points-v2 = <&venus_opp_table>;
   3316
   3317			interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>,
   3318					<&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>;
   3319			interconnect-names = "cpu-cfg", "video-mem";
   3320
   3321			iommus = <&apps_smmu 0x2180 0x20>,
   3322				 <&apps_smmu 0x2184 0x20>;
   3323			memory-region = <&video_mem>;
   3324
   3325			video-decoder {
   3326				compatible = "venus-decoder";
   3327			};
   3328
   3329			video-encoder {
   3330				compatible = "venus-encoder";
   3331			};
   3332
   3333			video-firmware {
   3334				iommus = <&apps_smmu 0x21a2 0x0>;
   3335			};
   3336
   3337			venus_opp_table: venus-opp-table {
   3338				compatible = "operating-points-v2";
   3339
   3340				opp-133330000 {
   3341					opp-hz = /bits/ 64 <133330000>;
   3342					required-opps = <&rpmhpd_opp_low_svs>;
   3343				};
   3344
   3345				opp-240000000 {
   3346					opp-hz = /bits/ 64 <240000000>;
   3347					required-opps = <&rpmhpd_opp_svs>;
   3348				};
   3349
   3350				opp-335000000 {
   3351					opp-hz = /bits/ 64 <335000000>;
   3352					required-opps = <&rpmhpd_opp_svs_l1>;
   3353				};
   3354
   3355				opp-424000000 {
   3356					opp-hz = /bits/ 64 <424000000>;
   3357					required-opps = <&rpmhpd_opp_nom>;
   3358				};
   3359
   3360				opp-460000048 {
   3361					opp-hz = /bits/ 64 <460000048>;
   3362					required-opps = <&rpmhpd_opp_turbo>;
   3363				};
   3364			};
   3365
   3366		};
   3367
   3368		videocc: clock-controller@aaf0000 {
   3369			compatible = "qcom,sc7280-videocc";
   3370			reg = <0 0xaaf0000 0 0x10000>;
   3371			clocks = <&rpmhcc RPMH_CXO_CLK>,
   3372				<&rpmhcc RPMH_CXO_CLK_A>;
   3373			clock-names = "bi_tcxo", "bi_tcxo_ao";
   3374			#clock-cells = <1>;
   3375			#reset-cells = <1>;
   3376			#power-domain-cells = <1>;
   3377		};
   3378
   3379		camcc: clock-controller@ad00000 {
   3380			compatible = "qcom,sc7280-camcc";
   3381			reg = <0 0x0ad00000 0 0x10000>;
   3382			clocks = <&rpmhcc RPMH_CXO_CLK>,
   3383				<&rpmhcc RPMH_CXO_CLK_A>,
   3384				<&sleep_clk>;
   3385			clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
   3386			#clock-cells = <1>;
   3387			#reset-cells = <1>;
   3388			#power-domain-cells = <1>;
   3389		};
   3390
   3391		dispcc: clock-controller@af00000 {
   3392			compatible = "qcom,sc7280-dispcc";
   3393			reg = <0 0xaf00000 0 0x20000>;
   3394			clocks = <&rpmhcc RPMH_CXO_CLK>,
   3395				 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
   3396				 <&mdss_dsi_phy 0>,
   3397				 <&mdss_dsi_phy 1>,
   3398				 <&dp_phy 0>,
   3399				 <&dp_phy 1>,
   3400				 <&mdss_edp_phy 0>,
   3401				 <&mdss_edp_phy 1>;
   3402			clock-names = "bi_tcxo",
   3403				      "gcc_disp_gpll0_clk",
   3404				      "dsi0_phy_pll_out_byteclk",
   3405				      "dsi0_phy_pll_out_dsiclk",
   3406				      "dp_phy_pll_link_clk",
   3407				      "dp_phy_pll_vco_div_clk",
   3408				      "edp_phy_pll_link_clk",
   3409				      "edp_phy_pll_vco_div_clk";
   3410			#clock-cells = <1>;
   3411			#reset-cells = <1>;
   3412			#power-domain-cells = <1>;
   3413		};
   3414
   3415		mdss: display-subsystem@ae00000 {
   3416			compatible = "qcom,sc7280-mdss";
   3417			reg = <0 0x0ae00000 0 0x1000>;
   3418			reg-names = "mdss";
   3419
   3420			power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
   3421
   3422			clocks = <&gcc GCC_DISP_AHB_CLK>,
   3423				 <&dispcc DISP_CC_MDSS_AHB_CLK>,
   3424				<&dispcc DISP_CC_MDSS_MDP_CLK>;
   3425			clock-names = "iface",
   3426				      "ahb",
   3427				      "core";
   3428
   3429			assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
   3430			assigned-clock-rates = <300000000>;
   3431
   3432			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
   3433			interrupt-controller;
   3434			#interrupt-cells = <1>;
   3435
   3436			interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
   3437			interconnect-names = "mdp0-mem";
   3438
   3439			iommus = <&apps_smmu 0x900 0x402>;
   3440
   3441			#address-cells = <2>;
   3442			#size-cells = <2>;
   3443			ranges;
   3444
   3445			status = "disabled";
   3446
   3447			mdss_mdp: display-controller@ae01000 {
   3448				compatible = "qcom,sc7280-dpu";
   3449				reg = <0 0x0ae01000 0 0x8f030>,
   3450					<0 0x0aeb0000 0 0x2008>;
   3451				reg-names = "mdp", "vbif";
   3452
   3453				clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
   3454					<&gcc GCC_DISP_SF_AXI_CLK>,
   3455					<&dispcc DISP_CC_MDSS_AHB_CLK>,
   3456					<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
   3457					<&dispcc DISP_CC_MDSS_MDP_CLK>,
   3458					<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
   3459				clock-names = "bus",
   3460					      "nrt_bus",
   3461					      "iface",
   3462					      "lut",
   3463					      "core",
   3464					      "vsync";
   3465				assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
   3466						<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
   3467						<&dispcc DISP_CC_MDSS_AHB_CLK>;
   3468				assigned-clock-rates = <300000000>,
   3469							<19200000>,
   3470							<19200000>;
   3471				operating-points-v2 = <&mdp_opp_table>;
   3472				power-domains = <&rpmhpd SC7280_CX>;
   3473
   3474				interrupt-parent = <&mdss>;
   3475				interrupts = <0>;
   3476
   3477				status = "disabled";
   3478
   3479				ports {
   3480					#address-cells = <1>;
   3481					#size-cells = <0>;
   3482
   3483					port@0 {
   3484						reg = <0>;
   3485						dpu_intf1_out: endpoint {
   3486							remote-endpoint = <&dsi0_in>;
   3487						};
   3488					};
   3489
   3490					port@1 {
   3491						reg = <1>;
   3492						dpu_intf5_out: endpoint {
   3493							remote-endpoint = <&edp_in>;
   3494						};
   3495					};
   3496
   3497					port@2 {
   3498						reg = <2>;
   3499						dpu_intf0_out: endpoint {
   3500							remote-endpoint = <&dp_in>;
   3501						};
   3502					};
   3503				};
   3504
   3505				mdp_opp_table: opp-table {
   3506					compatible = "operating-points-v2";
   3507
   3508					opp-200000000 {
   3509						opp-hz = /bits/ 64 <200000000>;
   3510						required-opps = <&rpmhpd_opp_low_svs>;
   3511					};
   3512
   3513					opp-300000000 {
   3514						opp-hz = /bits/ 64 <300000000>;
   3515						required-opps = <&rpmhpd_opp_svs>;
   3516					};
   3517
   3518					opp-380000000 {
   3519						opp-hz = /bits/ 64 <380000000>;
   3520						required-opps = <&rpmhpd_opp_svs_l1>;
   3521					};
   3522
   3523					opp-506666667 {
   3524						opp-hz = /bits/ 64 <506666667>;
   3525						required-opps = <&rpmhpd_opp_nom>;
   3526					};
   3527				};
   3528			};
   3529
   3530			mdss_dsi: dsi@ae94000 {
   3531				compatible = "qcom,mdss-dsi-ctrl";
   3532				reg = <0 0x0ae94000 0 0x400>;
   3533				reg-names = "dsi_ctrl";
   3534
   3535				interrupt-parent = <&mdss>;
   3536				interrupts = <4>;
   3537
   3538				clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
   3539					 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
   3540					 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
   3541					 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
   3542					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
   3543					 <&gcc GCC_DISP_HF_AXI_CLK>;
   3544				clock-names = "byte",
   3545					      "byte_intf",
   3546					      "pixel",
   3547					      "core",
   3548					      "iface",
   3549					      "bus";
   3550
   3551				operating-points-v2 = <&dsi_opp_table>;
   3552				power-domains = <&rpmhpd SC7280_CX>;
   3553
   3554				phys = <&mdss_dsi_phy>;
   3555				phy-names = "dsi";
   3556
   3557				#address-cells = <1>;
   3558				#size-cells = <0>;
   3559
   3560				status = "disabled";
   3561
   3562				ports {
   3563					#address-cells = <1>;
   3564					#size-cells = <0>;
   3565
   3566					port@0 {
   3567						reg = <0>;
   3568						dsi0_in: endpoint {
   3569							remote-endpoint = <&dpu_intf1_out>;
   3570						};
   3571					};
   3572
   3573					port@1 {
   3574						reg = <1>;
   3575						dsi0_out: endpoint {
   3576						};
   3577					};
   3578				};
   3579
   3580				dsi_opp_table: opp-table {
   3581					compatible = "operating-points-v2";
   3582
   3583					opp-187500000 {
   3584						opp-hz = /bits/ 64 <187500000>;
   3585						required-opps = <&rpmhpd_opp_low_svs>;
   3586					};
   3587
   3588					opp-300000000 {
   3589						opp-hz = /bits/ 64 <300000000>;
   3590						required-opps = <&rpmhpd_opp_svs>;
   3591					};
   3592
   3593					opp-358000000 {
   3594						opp-hz = /bits/ 64 <358000000>;
   3595						required-opps = <&rpmhpd_opp_svs_l1>;
   3596					};
   3597				};
   3598			};
   3599
   3600			mdss_dsi_phy: phy@ae94400 {
   3601				compatible = "qcom,sc7280-dsi-phy-7nm";
   3602				reg = <0 0x0ae94400 0 0x200>,
   3603				      <0 0x0ae94600 0 0x280>,
   3604				      <0 0x0ae94900 0 0x280>;
   3605				reg-names = "dsi_phy",
   3606					    "dsi_phy_lane",
   3607					    "dsi_pll";
   3608
   3609				#clock-cells = <1>;
   3610				#phy-cells = <0>;
   3611
   3612				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
   3613					 <&rpmhcc RPMH_CXO_CLK>;
   3614				clock-names = "iface", "ref";
   3615
   3616				status = "disabled";
   3617			};
   3618
   3619			mdss_edp: edp@aea0000 {
   3620				compatible = "qcom,sc7280-edp";
   3621				pinctrl-names = "default";
   3622				pinctrl-0 = <&edp_hot_plug_det>;
   3623
   3624				reg = <0 0xaea0000 0 0x200>,
   3625				      <0 0xaea0200 0 0x200>,
   3626				      <0 0xaea0400 0 0xc00>,
   3627				      <0 0xaea1000 0 0x400>;
   3628
   3629				interrupt-parent = <&mdss>;
   3630				interrupts = <14>;
   3631
   3632				clocks = <&rpmhcc RPMH_CXO_CLK>,
   3633					 <&gcc GCC_EDP_CLKREF_EN>,
   3634					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
   3635					 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
   3636					 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,
   3637					 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
   3638					 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;
   3639				clock-names = "core_xo",
   3640					      "core_ref",
   3641					      "core_iface",
   3642					      "core_aux",
   3643					      "ctrl_link",
   3644					      "ctrl_link_iface",
   3645					      "stream_pixel";
   3646				#clock-cells = <1>;
   3647				assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
   3648						  <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
   3649				assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
   3650
   3651				phys = <&mdss_edp_phy>;
   3652				phy-names = "dp";
   3653
   3654				operating-points-v2 = <&edp_opp_table>;
   3655				power-domains = <&rpmhpd SC7280_CX>;
   3656
   3657				#address-cells = <1>;
   3658				#size-cells = <0>;
   3659
   3660				status = "disabled";
   3661
   3662				ports {
   3663					#address-cells = <1>;
   3664					#size-cells = <0>;
   3665
   3666					port@0 {
   3667						reg = <0>;
   3668						edp_in: endpoint {
   3669							remote-endpoint = <&dpu_intf5_out>;
   3670						};
   3671					};
   3672
   3673					port@1 {
   3674						reg = <1>;
   3675						mdss_edp_out: endpoint { };
   3676					};
   3677				};
   3678
   3679				edp_opp_table: opp-table {
   3680					compatible = "operating-points-v2";
   3681
   3682					opp-160000000 {
   3683						opp-hz = /bits/ 64 <160000000>;
   3684						required-opps = <&rpmhpd_opp_low_svs>;
   3685					};
   3686
   3687					opp-270000000 {
   3688						opp-hz = /bits/ 64 <270000000>;
   3689						required-opps = <&rpmhpd_opp_svs>;
   3690					};
   3691
   3692					opp-540000000 {
   3693						opp-hz = /bits/ 64 <540000000>;
   3694						required-opps = <&rpmhpd_opp_nom>;
   3695					};
   3696
   3697					opp-810000000 {
   3698						opp-hz = /bits/ 64 <810000000>;
   3699						required-opps = <&rpmhpd_opp_nom>;
   3700					};
   3701				};
   3702			};
   3703
   3704			mdss_edp_phy: phy@aec2a00 {
   3705				compatible = "qcom,sc7280-edp-phy";
   3706
   3707				reg = <0 0xaec2a00 0 0x19c>,
   3708				      <0 0xaec2200 0 0xa0>,
   3709				      <0 0xaec2600 0 0xa0>,
   3710				      <0 0xaec2000 0 0x1c0>;
   3711
   3712				clocks = <&rpmhcc RPMH_CXO_CLK>,
   3713					 <&gcc GCC_EDP_CLKREF_EN>;
   3714				clock-names = "aux",
   3715					      "cfg_ahb";
   3716
   3717				#clock-cells = <1>;
   3718				#phy-cells = <0>;
   3719
   3720				status = "disabled";
   3721			};
   3722
   3723			mdss_dp: displayport-controller@ae90000 {
   3724				compatible = "qcom,sc7280-dp";
   3725
   3726				reg = <0 0x0ae90000 0 0x1400>;
   3727
   3728				interrupt-parent = <&mdss>;
   3729				interrupts = <12>;
   3730
   3731				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
   3732					 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
   3733					 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
   3734					 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
   3735					 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
   3736				clock-names =	"core_iface",
   3737						"core_aux",
   3738						"ctrl_link",
   3739						"ctrl_link_iface",
   3740						"stream_pixel";
   3741				#clock-cells = <1>;
   3742				assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
   3743						  <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
   3744				assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
   3745				phys = <&dp_phy>;
   3746				phy-names = "dp";
   3747
   3748				operating-points-v2 = <&dp_opp_table>;
   3749				power-domains = <&rpmhpd SC7280_CX>;
   3750
   3751				#sound-dai-cells = <0>;
   3752
   3753				status = "disabled";
   3754
   3755				ports {
   3756					#address-cells = <1>;
   3757					#size-cells = <0>;
   3758
   3759					port@0 {
   3760						reg = <0>;
   3761						dp_in: endpoint {
   3762							remote-endpoint = <&dpu_intf0_out>;
   3763						};
   3764					};
   3765
   3766					port@1 {
   3767						reg = <1>;
   3768						dp_out: endpoint { };
   3769					};
   3770				};
   3771
   3772				dp_opp_table: opp-table {
   3773					compatible = "operating-points-v2";
   3774
   3775					opp-160000000 {
   3776						opp-hz = /bits/ 64 <160000000>;
   3777						required-opps = <&rpmhpd_opp_low_svs>;
   3778					};
   3779
   3780					opp-270000000 {
   3781						opp-hz = /bits/ 64 <270000000>;
   3782						required-opps = <&rpmhpd_opp_svs>;
   3783					};
   3784
   3785					opp-540000000 {
   3786						opp-hz = /bits/ 64 <540000000>;
   3787						required-opps = <&rpmhpd_opp_svs_l1>;
   3788					};
   3789
   3790					opp-810000000 {
   3791						opp-hz = /bits/ 64 <810000000>;
   3792						required-opps = <&rpmhpd_opp_nom>;
   3793					};
   3794				};
   3795			};
   3796		};
   3797
   3798		pdc: interrupt-controller@b220000 {
   3799			compatible = "qcom,sc7280-pdc", "qcom,pdc";
   3800			reg = <0 0x0b220000 0 0x30000>;
   3801			qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
   3802					  <55 306 4>, <59 312 3>, <62 374 2>,
   3803					  <64 434 2>, <66 438 3>, <69 86 1>,
   3804					  <70 520 54>, <124 609 31>, <155 63 1>,
   3805					  <156 716 12>;
   3806			#interrupt-cells = <2>;
   3807			interrupt-parent = <&intc>;
   3808			interrupt-controller;
   3809		};
   3810
   3811		pdc_reset: reset-controller@b5e0000 {
   3812			compatible = "qcom,sc7280-pdc-global";
   3813			reg = <0 0x0b5e0000 0 0x20000>;
   3814			#reset-cells = <1>;
   3815		};
   3816
   3817		tsens0: thermal-sensor@c263000 {
   3818			compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
   3819			reg = <0 0x0c263000 0 0x1ff>, /* TM */
   3820				<0 0x0c222000 0 0x1ff>; /* SROT */
   3821			#qcom,sensors = <15>;
   3822			interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
   3823				     <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
   3824			interrupt-names = "uplow","critical";
   3825			#thermal-sensor-cells = <1>;
   3826		};
   3827
   3828		tsens1: thermal-sensor@c265000 {
   3829			compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
   3830			reg = <0 0x0c265000 0 0x1ff>, /* TM */
   3831				<0 0x0c223000 0 0x1ff>; /* SROT */
   3832			#qcom,sensors = <12>;
   3833			interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
   3834				     <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
   3835			interrupt-names = "uplow","critical";
   3836			#thermal-sensor-cells = <1>;
   3837		};
   3838
   3839		aoss_reset: reset-controller@c2a0000 {
   3840			compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
   3841			reg = <0 0x0c2a0000 0 0x31000>;
   3842			#reset-cells = <1>;
   3843		};
   3844
   3845		aoss_qmp: power-controller@c300000 {
   3846			compatible = "qcom,sc7280-aoss-qmp";
   3847			reg = <0 0x0c300000 0 0x400>;
   3848			interrupts-extended = <&ipcc IPCC_CLIENT_AOP
   3849						     IPCC_MPROC_SIGNAL_GLINK_QMP
   3850						     IRQ_TYPE_EDGE_RISING>;
   3851			mboxes = <&ipcc IPCC_CLIENT_AOP
   3852					IPCC_MPROC_SIGNAL_GLINK_QMP>;
   3853
   3854			#clock-cells = <0>;
   3855		};
   3856
   3857		sram@c3f0000 {
   3858			compatible = "qcom,rpmh-stats";
   3859			reg = <0 0x0c3f0000 0 0x400>;
   3860		};
   3861
   3862		spmi_bus: spmi@c440000 {
   3863			compatible = "qcom,spmi-pmic-arb";
   3864			reg = <0 0x0c440000 0 0x1100>,
   3865			      <0 0x0c600000 0 0x2000000>,
   3866			      <0 0x0e600000 0 0x100000>,
   3867			      <0 0x0e700000 0 0xa0000>,
   3868			      <0 0x0c40a000 0 0x26000>;
   3869			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
   3870			interrupt-names = "periph_irq";
   3871			interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
   3872			qcom,ee = <0>;
   3873			qcom,channel = <0>;
   3874			#address-cells = <1>;
   3875			#size-cells = <1>;
   3876			interrupt-controller;
   3877			#interrupt-cells = <4>;
   3878		};
   3879
   3880		tlmm: pinctrl@f100000 {
   3881			compatible = "qcom,sc7280-pinctrl";
   3882			reg = <0 0x0f100000 0 0x300000>;
   3883			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
   3884			gpio-controller;
   3885			#gpio-cells = <2>;
   3886			interrupt-controller;
   3887			#interrupt-cells = <2>;
   3888			gpio-ranges = <&tlmm 0 0 175>;
   3889			wakeup-parent = <&pdc>;
   3890
   3891			dp_hot_plug_det: dp-hot-plug-det {
   3892				pins = "gpio47";
   3893				function = "dp_hot";
   3894			};
   3895
   3896			edp_hot_plug_det: edp-hot-plug-det {
   3897				pins = "gpio60";
   3898				function = "edp_hot";
   3899			};
   3900
   3901			pcie1_clkreq_n: pcie1-clkreq-n {
   3902				pins = "gpio79";
   3903				function = "pcie1_clkreqn";
   3904			};
   3905
   3906			qspi_clk: qspi-clk {
   3907				pins = "gpio14";
   3908				function = "qspi_clk";
   3909			};
   3910
   3911			qspi_cs0: qspi-cs0 {
   3912				pins = "gpio15";
   3913				function = "qspi_cs";
   3914			};
   3915
   3916			qspi_cs1: qspi-cs1 {
   3917				pins = "gpio19";
   3918				function = "qspi_cs";
   3919			};
   3920
   3921			qspi_data01: qspi-data01 {
   3922				pins = "gpio12", "gpio13";
   3923				function = "qspi_data";
   3924			};
   3925
   3926			qspi_data12: qspi-data12 {
   3927				pins = "gpio16", "gpio17";
   3928				function = "qspi_data";
   3929			};
   3930
   3931			qup_i2c0_data_clk: qup-i2c0-data-clk {
   3932				pins = "gpio0", "gpio1";
   3933				function = "qup00";
   3934			};
   3935
   3936			qup_i2c1_data_clk: qup-i2c1-data-clk {
   3937				pins = "gpio4", "gpio5";
   3938				function = "qup01";
   3939			};
   3940
   3941			qup_i2c2_data_clk: qup-i2c2-data-clk {
   3942				pins = "gpio8", "gpio9";
   3943				function = "qup02";
   3944			};
   3945
   3946			qup_i2c3_data_clk: qup-i2c3-data-clk {
   3947				pins = "gpio12", "gpio13";
   3948				function = "qup03";
   3949			};
   3950
   3951			qup_i2c4_data_clk: qup-i2c4-data-clk {
   3952				pins = "gpio16", "gpio17";
   3953				function = "qup04";
   3954			};
   3955
   3956			qup_i2c5_data_clk: qup-i2c5-data-clk {
   3957				pins = "gpio20", "gpio21";
   3958				function = "qup05";
   3959			};
   3960
   3961			qup_i2c6_data_clk: qup-i2c6-data-clk {
   3962				pins = "gpio24", "gpio25";
   3963				function = "qup06";
   3964			};
   3965
   3966			qup_i2c7_data_clk: qup-i2c7-data-clk {
   3967				pins = "gpio28", "gpio29";
   3968				function = "qup07";
   3969			};
   3970
   3971			qup_i2c8_data_clk: qup-i2c8-data-clk {
   3972				pins = "gpio32", "gpio33";
   3973				function = "qup10";
   3974			};
   3975
   3976			qup_i2c9_data_clk: qup-i2c9-data-clk {
   3977				pins = "gpio36", "gpio37";
   3978				function = "qup11";
   3979			};
   3980
   3981			qup_i2c10_data_clk: qup-i2c10-data-clk {
   3982				pins = "gpio40", "gpio41";
   3983				function = "qup12";
   3984			};
   3985
   3986			qup_i2c11_data_clk: qup-i2c11-data-clk {
   3987				pins = "gpio44", "gpio45";
   3988				function = "qup13";
   3989			};
   3990
   3991			qup_i2c12_data_clk: qup-i2c12-data-clk {
   3992				pins = "gpio48", "gpio49";
   3993				function = "qup14";
   3994			};
   3995
   3996			qup_i2c13_data_clk: qup-i2c13-data-clk {
   3997				pins = "gpio52", "gpio53";
   3998				function = "qup15";
   3999			};
   4000
   4001			qup_i2c14_data_clk: qup-i2c14-data-clk {
   4002				pins = "gpio56", "gpio57";
   4003				function = "qup16";
   4004			};
   4005
   4006			qup_i2c15_data_clk: qup-i2c15-data-clk {
   4007				pins = "gpio60", "gpio61";
   4008				function = "qup17";
   4009			};
   4010
   4011			qup_spi0_data_clk: qup-spi0-data-clk {
   4012				pins = "gpio0", "gpio1", "gpio2";
   4013				function = "qup00";
   4014			};
   4015
   4016			qup_spi0_cs: qup-spi0-cs {
   4017				pins = "gpio3";
   4018				function = "qup00";
   4019			};
   4020
   4021			qup_spi0_cs_gpio: qup-spi0-cs-gpio {
   4022				pins = "gpio3";
   4023				function = "gpio";
   4024			};
   4025
   4026			qup_spi1_data_clk: qup-spi1-data-clk {
   4027				pins = "gpio4", "gpio5", "gpio6";
   4028				function = "qup01";
   4029			};
   4030
   4031			qup_spi1_cs: qup-spi1-cs {
   4032				pins = "gpio7";
   4033				function = "qup01";
   4034			};
   4035
   4036			qup_spi1_cs_gpio: qup-spi1-cs-gpio {
   4037				pins = "gpio7";
   4038				function = "gpio";
   4039			};
   4040
   4041			qup_spi2_data_clk: qup-spi2-data-clk {
   4042				pins = "gpio8", "gpio9", "gpio10";
   4043				function = "qup02";
   4044			};
   4045
   4046			qup_spi2_cs: qup-spi2-cs {
   4047				pins = "gpio11";
   4048				function = "qup02";
   4049			};
   4050
   4051			qup_spi2_cs_gpio: qup-spi2-cs-gpio {
   4052				pins = "gpio11";
   4053				function = "gpio";
   4054			};
   4055
   4056			qup_spi3_data_clk: qup-spi3-data-clk {
   4057				pins = "gpio12", "gpio13", "gpio14";
   4058				function = "qup03";
   4059			};
   4060
   4061			qup_spi3_cs: qup-spi3-cs {
   4062				pins = "gpio15";
   4063				function = "qup03";
   4064			};
   4065
   4066			qup_spi3_cs_gpio: qup-spi3-cs-gpio {
   4067				pins = "gpio15";
   4068				function = "gpio";
   4069			};
   4070
   4071			qup_spi4_data_clk: qup-spi4-data-clk {
   4072				pins = "gpio16", "gpio17", "gpio18";
   4073				function = "qup04";
   4074			};
   4075
   4076			qup_spi4_cs: qup-spi4-cs {
   4077				pins = "gpio19";
   4078				function = "qup04";
   4079			};
   4080
   4081			qup_spi4_cs_gpio: qup-spi4-cs-gpio {
   4082				pins = "gpio19";
   4083				function = "gpio";
   4084			};
   4085
   4086			qup_spi5_data_clk: qup-spi5-data-clk {
   4087				pins = "gpio20", "gpio21", "gpio22";
   4088				function = "qup05";
   4089			};
   4090
   4091			qup_spi5_cs: qup-spi5-cs {
   4092				pins = "gpio23";
   4093				function = "qup05";
   4094			};
   4095
   4096			qup_spi5_cs_gpio: qup-spi5-cs-gpio {
   4097				pins = "gpio23";
   4098				function = "gpio";
   4099			};
   4100
   4101			qup_spi6_data_clk: qup-spi6-data-clk {
   4102				pins = "gpio24", "gpio25", "gpio26";
   4103				function = "qup06";
   4104			};
   4105
   4106			qup_spi6_cs: qup-spi6-cs {
   4107				pins = "gpio27";
   4108				function = "qup06";
   4109			};
   4110
   4111			qup_spi6_cs_gpio: qup-spi6-cs-gpio {
   4112				pins = "gpio27";
   4113				function = "gpio";
   4114			};
   4115
   4116			qup_spi7_data_clk: qup-spi7-data-clk {
   4117				pins = "gpio28", "gpio29", "gpio30";
   4118				function = "qup07";
   4119			};
   4120
   4121			qup_spi7_cs: qup-spi7-cs {
   4122				pins = "gpio31";
   4123				function = "qup07";
   4124			};
   4125
   4126			qup_spi7_cs_gpio: qup-spi7-cs-gpio {
   4127				pins = "gpio31";
   4128				function = "gpio";
   4129			};
   4130
   4131			qup_spi8_data_clk: qup-spi8-data-clk {
   4132				pins = "gpio32", "gpio33", "gpio34";
   4133				function = "qup10";
   4134			};
   4135
   4136			qup_spi8_cs: qup-spi8-cs {
   4137				pins = "gpio35";
   4138				function = "qup10";
   4139			};
   4140
   4141			qup_spi8_cs_gpio: qup-spi8-cs-gpio {
   4142				pins = "gpio35";
   4143				function = "gpio";
   4144			};
   4145
   4146			qup_spi9_data_clk: qup-spi9-data-clk {
   4147				pins = "gpio36", "gpio37", "gpio38";
   4148				function = "qup11";
   4149			};
   4150
   4151			qup_spi9_cs: qup-spi9-cs {
   4152				pins = "gpio39";
   4153				function = "qup11";
   4154			};
   4155
   4156			qup_spi9_cs_gpio: qup-spi9-cs-gpio {
   4157				pins = "gpio39";
   4158				function = "gpio";
   4159			};
   4160
   4161			qup_spi10_data_clk: qup-spi10-data-clk {
   4162				pins = "gpio40", "gpio41", "gpio42";
   4163				function = "qup12";
   4164			};
   4165
   4166			qup_spi10_cs: qup-spi10-cs {
   4167				pins = "gpio43";
   4168				function = "qup12";
   4169			};
   4170
   4171			qup_spi10_cs_gpio: qup-spi10-cs-gpio {
   4172				pins = "gpio43";
   4173				function = "gpio";
   4174			};
   4175
   4176			qup_spi11_data_clk: qup-spi11-data-clk {
   4177				pins = "gpio44", "gpio45", "gpio46";
   4178				function = "qup13";
   4179			};
   4180
   4181			qup_spi11_cs: qup-spi11-cs {
   4182				pins = "gpio47";
   4183				function = "qup13";
   4184			};
   4185
   4186			qup_spi11_cs_gpio: qup-spi11-cs-gpio {
   4187				pins = "gpio47";
   4188				function = "gpio";
   4189			};
   4190
   4191			qup_spi12_data_clk: qup-spi12-data-clk {
   4192				pins = "gpio48", "gpio49", "gpio50";
   4193				function = "qup14";
   4194			};
   4195
   4196			qup_spi12_cs: qup-spi12-cs {
   4197				pins = "gpio51";
   4198				function = "qup14";
   4199			};
   4200
   4201			qup_spi12_cs_gpio: qup-spi12-cs-gpio {
   4202				pins = "gpio51";
   4203				function = "gpio";
   4204			};
   4205
   4206			qup_spi13_data_clk: qup-spi13-data-clk {
   4207				pins = "gpio52", "gpio53", "gpio54";
   4208				function = "qup15";
   4209			};
   4210
   4211			qup_spi13_cs: qup-spi13-cs {
   4212				pins = "gpio55";
   4213				function = "qup15";
   4214			};
   4215
   4216			qup_spi13_cs_gpio: qup-spi13-cs-gpio {
   4217				pins = "gpio55";
   4218				function = "gpio";
   4219			};
   4220
   4221			qup_spi14_data_clk: qup-spi14-data-clk {
   4222				pins = "gpio56", "gpio57", "gpio58";
   4223				function = "qup16";
   4224			};
   4225
   4226			qup_spi14_cs: qup-spi14-cs {
   4227				pins = "gpio59";
   4228				function = "qup16";
   4229			};
   4230
   4231			qup_spi14_cs_gpio: qup-spi14-cs-gpio {
   4232				pins = "gpio59";
   4233				function = "gpio";
   4234			};
   4235
   4236			qup_spi15_data_clk: qup-spi15-data-clk {
   4237				pins = "gpio60", "gpio61", "gpio62";
   4238				function = "qup17";
   4239			};
   4240
   4241			qup_spi15_cs: qup-spi15-cs {
   4242				pins = "gpio63";
   4243				function = "qup17";
   4244			};
   4245
   4246			qup_spi15_cs_gpio: qup-spi15-cs-gpio {
   4247				pins = "gpio63";
   4248				function = "gpio";
   4249			};
   4250
   4251			qup_uart0_cts: qup-uart0-cts {
   4252				pins = "gpio0";
   4253				function = "qup00";
   4254			};
   4255
   4256			qup_uart0_rts: qup-uart0-rts {
   4257				pins = "gpio1";
   4258				function = "qup00";
   4259			};
   4260
   4261			qup_uart0_tx: qup-uart0-tx {
   4262				pins = "gpio2";
   4263				function = "qup00";
   4264			};
   4265
   4266			qup_uart0_rx: qup-uart0-rx {
   4267				pins = "gpio3";
   4268				function = "qup00";
   4269			};
   4270
   4271			qup_uart1_cts: qup-uart1-cts {
   4272				pins = "gpio4";
   4273				function = "qup01";
   4274			};
   4275
   4276			qup_uart1_rts: qup-uart1-rts {
   4277				pins = "gpio5";
   4278				function = "qup01";
   4279			};
   4280
   4281			qup_uart1_tx: qup-uart1-tx {
   4282				pins = "gpio6";
   4283				function = "qup01";
   4284			};
   4285
   4286			qup_uart1_rx: qup-uart1-rx {
   4287				pins = "gpio7";
   4288				function = "qup01";
   4289			};
   4290
   4291			qup_uart2_cts: qup-uart2-cts {
   4292				pins = "gpio8";
   4293				function = "qup02";
   4294			};
   4295
   4296			qup_uart2_rts: qup-uart2-rts {
   4297				pins = "gpio9";
   4298				function = "qup02";
   4299			};
   4300
   4301			qup_uart2_tx: qup-uart2-tx {
   4302				pins = "gpio10";
   4303				function = "qup02";
   4304			};
   4305
   4306			qup_uart2_rx: qup-uart2-rx {
   4307				pins = "gpio11";
   4308				function = "qup02";
   4309			};
   4310
   4311			qup_uart3_cts: qup-uart3-cts {
   4312				pins = "gpio12";
   4313				function = "qup03";
   4314			};
   4315
   4316			qup_uart3_rts: qup-uart3-rts {
   4317				pins = "gpio13";
   4318				function = "qup03";
   4319			};
   4320
   4321			qup_uart3_tx: qup-uart3-tx {
   4322				pins = "gpio14";
   4323				function = "qup03";
   4324			};
   4325
   4326			qup_uart3_rx: qup-uart3-rx {
   4327				pins = "gpio15";
   4328				function = "qup03";
   4329			};
   4330
   4331			qup_uart4_cts: qup-uart4-cts {
   4332				pins = "gpio16";
   4333				function = "qup04";
   4334			};
   4335
   4336			qup_uart4_rts: qup-uart4-rts {
   4337				pins = "gpio17";
   4338				function = "qup04";
   4339			};
   4340
   4341			qup_uart4_tx: qup-uart4-tx {
   4342				pins = "gpio18";
   4343				function = "qup04";
   4344			};
   4345
   4346			qup_uart4_rx: qup-uart4-rx {
   4347				pins = "gpio19";
   4348				function = "qup04";
   4349			};
   4350
   4351			qup_uart5_cts: qup-uart5-cts {
   4352				pins = "gpio20";
   4353				function = "qup05";
   4354			};
   4355
   4356			qup_uart5_rts: qup-uart5-rts {
   4357				pins = "gpio21";
   4358				function = "qup05";
   4359			};
   4360
   4361			qup_uart5_tx: qup-uart5-tx {
   4362				pins = "gpio22";
   4363				function = "qup05";
   4364			};
   4365
   4366			qup_uart5_rx: qup-uart5-rx {
   4367				pins = "gpio23";
   4368				function = "qup05";
   4369			};
   4370
   4371			qup_uart6_cts: qup-uart6-cts {
   4372				pins = "gpio24";
   4373				function = "qup06";
   4374			};
   4375
   4376			qup_uart6_rts: qup-uart6-rts {
   4377				pins = "gpio25";
   4378				function = "qup06";
   4379			};
   4380
   4381			qup_uart6_tx: qup-uart6-tx {
   4382				pins = "gpio26";
   4383				function = "qup06";
   4384			};
   4385
   4386			qup_uart6_rx: qup-uart6-rx {
   4387				pins = "gpio27";
   4388				function = "qup06";
   4389			};
   4390
   4391			qup_uart7_cts: qup-uart7-cts {
   4392				pins = "gpio28";
   4393				function = "qup07";
   4394			};
   4395
   4396			qup_uart7_rts: qup-uart7-rts {
   4397				pins = "gpio29";
   4398				function = "qup07";
   4399			};
   4400
   4401			qup_uart7_tx: qup-uart7-tx {
   4402				pins = "gpio30";
   4403				function = "qup07";
   4404			};
   4405
   4406			qup_uart7_rx: qup-uart7-rx {
   4407				pins = "gpio31";
   4408				function = "qup07";
   4409			};
   4410
   4411			qup_uart8_cts: qup-uart8-cts {
   4412				pins = "gpio32";
   4413				function = "qup10";
   4414			};
   4415
   4416			qup_uart8_rts: qup-uart8-rts {
   4417				pins = "gpio33";
   4418				function = "qup10";
   4419			};
   4420
   4421			qup_uart8_tx: qup-uart8-tx {
   4422				pins = "gpio34";
   4423				function = "qup10";
   4424			};
   4425
   4426			qup_uart8_rx: qup-uart8-rx {
   4427				pins = "gpio35";
   4428				function = "qup10";
   4429			};
   4430
   4431			qup_uart9_cts: qup-uart9-cts {
   4432				pins = "gpio36";
   4433				function = "qup11";
   4434			};
   4435
   4436			qup_uart9_rts: qup-uart9-rts {
   4437				pins = "gpio37";
   4438				function = "qup11";
   4439			};
   4440
   4441			qup_uart9_tx: qup-uart9-tx {
   4442				pins = "gpio38";
   4443				function = "qup11";
   4444			};
   4445
   4446			qup_uart9_rx: qup-uart9-rx {
   4447				pins = "gpio39";
   4448				function = "qup11";
   4449			};
   4450
   4451			qup_uart10_cts: qup-uart10-cts {
   4452				pins = "gpio40";
   4453				function = "qup12";
   4454			};
   4455
   4456			qup_uart10_rts: qup-uart10-rts {
   4457				pins = "gpio41";
   4458				function = "qup12";
   4459			};
   4460
   4461			qup_uart10_tx: qup-uart10-tx {
   4462				pins = "gpio42";
   4463				function = "qup12";
   4464			};
   4465
   4466			qup_uart10_rx: qup-uart10-rx {
   4467				pins = "gpio43";
   4468				function = "qup12";
   4469			};
   4470
   4471			qup_uart11_cts: qup-uart11-cts {
   4472				pins = "gpio44";
   4473				function = "qup13";
   4474			};
   4475
   4476			qup_uart11_rts: qup-uart11-rts {
   4477				pins = "gpio45";
   4478				function = "qup13";
   4479			};
   4480
   4481			qup_uart11_tx: qup-uart11-tx {
   4482				pins = "gpio46";
   4483				function = "qup13";
   4484			};
   4485
   4486			qup_uart11_rx: qup-uart11-rx {
   4487				pins = "gpio47";
   4488				function = "qup13";
   4489			};
   4490
   4491			qup_uart12_cts: qup-uart12-cts {
   4492				pins = "gpio48";
   4493				function = "qup14";
   4494			};
   4495
   4496			qup_uart12_rts: qup-uart12-rts {
   4497				pins = "gpio49";
   4498				function = "qup14";
   4499			};
   4500
   4501			qup_uart12_tx: qup-uart12-tx {
   4502				pins = "gpio50";
   4503				function = "qup14";
   4504			};
   4505
   4506			qup_uart12_rx: qup-uart12-rx {
   4507				pins = "gpio51";
   4508				function = "qup14";
   4509			};
   4510
   4511			qup_uart13_cts: qup-uart13-cts {
   4512				pins = "gpio52";
   4513				function = "qup15";
   4514			};
   4515
   4516			qup_uart13_rts: qup-uart13-rts {
   4517				pins = "gpio53";
   4518				function = "qup15";
   4519			};
   4520
   4521			qup_uart13_tx: qup-uart13-tx {
   4522				pins = "gpio54";
   4523				function = "qup15";
   4524			};
   4525
   4526			qup_uart13_rx: qup-uart13-rx {
   4527				pins = "gpio55";
   4528				function = "qup15";
   4529			};
   4530
   4531			qup_uart14_cts: qup-uart14-cts {
   4532				pins = "gpio56";
   4533				function = "qup16";
   4534			};
   4535
   4536			qup_uart14_rts: qup-uart14-rts {
   4537				pins = "gpio57";
   4538				function = "qup16";
   4539			};
   4540
   4541			qup_uart14_tx: qup-uart14-tx {
   4542				pins = "gpio58";
   4543				function = "qup16";
   4544			};
   4545
   4546			qup_uart14_rx: qup-uart14-rx {
   4547				pins = "gpio59";
   4548				function = "qup16";
   4549			};
   4550
   4551			qup_uart15_cts: qup-uart15-cts {
   4552				pins = "gpio60";
   4553				function = "qup17";
   4554			};
   4555
   4556			qup_uart15_rts: qup-uart15-rts {
   4557				pins = "gpio61";
   4558				function = "qup17";
   4559			};
   4560
   4561			qup_uart15_tx: qup-uart15-tx {
   4562				pins = "gpio62";
   4563				function = "qup17";
   4564			};
   4565
   4566			qup_uart15_rx: qup-uart15-rx {
   4567				pins = "gpio63";
   4568				function = "qup17";
   4569			};
   4570
   4571			sdc1_clk: sdc1-clk {
   4572				pins = "sdc1_clk";
   4573			};
   4574
   4575			sdc1_cmd: sdc1-cmd {
   4576				pins = "sdc1_cmd";
   4577			};
   4578
   4579			sdc1_data: sdc1-data {
   4580				pins = "sdc1_data";
   4581			};
   4582
   4583			sdc1_rclk: sdc1-rclk {
   4584				pins = "sdc1_rclk";
   4585			};
   4586
   4587			sdc1_clk_sleep: sdc1-clk-sleep {
   4588				pins = "sdc1_clk";
   4589				drive-strength = <2>;
   4590				bias-bus-hold;
   4591			};
   4592
   4593			sdc1_cmd_sleep: sdc1-cmd-sleep {
   4594				pins = "sdc1_cmd";
   4595				drive-strength = <2>;
   4596				bias-bus-hold;
   4597			};
   4598
   4599			sdc1_data_sleep: sdc1-data-sleep {
   4600				pins = "sdc1_data";
   4601				drive-strength = <2>;
   4602				bias-bus-hold;
   4603			};
   4604
   4605			sdc1_rclk_sleep: sdc1-rclk-sleep {
   4606				pins = "sdc1_rclk";
   4607				drive-strength = <2>;
   4608				bias-bus-hold;
   4609			};
   4610
   4611			sdc2_clk: sdc2-clk {
   4612				pins = "sdc2_clk";
   4613			};
   4614
   4615			sdc2_cmd: sdc2-cmd {
   4616				pins = "sdc2_cmd";
   4617			};
   4618
   4619			sdc2_data: sdc2-data {
   4620				pins = "sdc2_data";
   4621			};
   4622
   4623			sdc2_clk_sleep: sdc2-clk-sleep {
   4624				pins = "sdc2_clk";
   4625				drive-strength = <2>;
   4626				bias-bus-hold;
   4627			};
   4628
   4629			sdc2_cmd_sleep: sdc2-cmd-sleep {
   4630				pins = "sdc2_cmd";
   4631				drive-strength = <2>;
   4632				bias-bus-hold;
   4633			};
   4634
   4635			sdc2_data_sleep: sdc2-data-sleep {
   4636				pins = "sdc2_data";
   4637				drive-strength = <2>;
   4638				bias-bus-hold;
   4639			};
   4640		};
   4641
   4642		imem@146a5000 {
   4643			compatible = "qcom,sc7280-imem", "syscon";
   4644			reg = <0 0x146a5000 0 0x6000>;
   4645
   4646			#address-cells = <1>;
   4647			#size-cells = <1>;
   4648
   4649			ranges = <0 0 0x146a5000 0x6000>;
   4650
   4651			pil-reloc@594c {
   4652				compatible = "qcom,pil-reloc-info";
   4653				reg = <0x594c 0xc8>;
   4654			};
   4655		};
   4656
   4657		apps_smmu: iommu@15000000 {
   4658			compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
   4659			reg = <0 0x15000000 0 0x100000>;
   4660			#iommu-cells = <2>;
   4661			#global-interrupts = <1>;
   4662			dma-coherent;
   4663			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
   4664				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
   4665				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
   4666				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
   4667				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
   4668				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
   4669				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
   4670				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
   4671				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
   4672				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
   4673				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
   4674				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
   4675				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
   4676				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
   4677				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
   4678				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
   4679				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
   4680				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
   4681				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
   4682				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
   4683				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
   4684				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
   4685				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
   4686				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
   4687				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
   4688				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
   4689				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
   4690				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
   4691				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
   4692				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
   4693				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
   4694				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
   4695				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
   4696				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
   4697				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
   4698				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
   4699				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
   4700				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
   4701				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
   4702				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
   4703				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
   4704				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
   4705				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
   4706				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
   4707				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
   4708				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
   4709				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
   4710				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
   4711				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
   4712				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
   4713				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
   4714				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
   4715				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
   4716				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
   4717				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
   4718				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
   4719				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
   4720				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
   4721				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
   4722				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
   4723				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
   4724				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
   4725				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
   4726				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
   4727				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
   4728				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
   4729				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
   4730				     <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
   4731				     <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
   4732				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
   4733				     <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
   4734				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
   4735				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
   4736				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
   4737				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
   4738				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
   4739				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
   4740				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
   4741				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
   4742				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
   4743				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
   4744		};
   4745
   4746		intc: interrupt-controller@17a00000 {
   4747			compatible = "arm,gic-v3";
   4748			#address-cells = <2>;
   4749			#size-cells = <2>;
   4750			ranges;
   4751			#interrupt-cells = <3>;
   4752			interrupt-controller;
   4753			reg = <0 0x17a00000 0 0x10000>,     /* GICD */
   4754			      <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
   4755			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
   4756
   4757			gic-its@17a40000 {
   4758				compatible = "arm,gic-v3-its";
   4759				msi-controller;
   4760				#msi-cells = <1>;
   4761				reg = <0 0x17a40000 0 0x20000>;
   4762				status = "disabled";
   4763			};
   4764		};
   4765
   4766		watchdog@17c10000 {
   4767			compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
   4768			reg = <0 0x17c10000 0 0x1000>;
   4769			clocks = <&sleep_clk>;
   4770			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
   4771		};
   4772
   4773		timer@17c20000 {
   4774			#address-cells = <2>;
   4775			#size-cells = <2>;
   4776			ranges;
   4777			compatible = "arm,armv7-timer-mem";
   4778			reg = <0 0x17c20000 0 0x1000>;
   4779
   4780			frame@17c21000 {
   4781				frame-number = <0>;
   4782				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
   4783					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
   4784				reg = <0 0x17c21000 0 0x1000>,
   4785				      <0 0x17c22000 0 0x1000>;
   4786			};
   4787
   4788			frame@17c23000 {
   4789				frame-number = <1>;
   4790				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
   4791				reg = <0 0x17c23000 0 0x1000>;
   4792				status = "disabled";
   4793			};
   4794
   4795			frame@17c25000 {
   4796				frame-number = <2>;
   4797				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
   4798				reg = <0 0x17c25000 0 0x1000>;
   4799				status = "disabled";
   4800			};
   4801
   4802			frame@17c27000 {
   4803				frame-number = <3>;
   4804				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
   4805				reg = <0 0x17c27000 0 0x1000>;
   4806				status = "disabled";
   4807			};
   4808
   4809			frame@17c29000 {
   4810				frame-number = <4>;
   4811				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
   4812				reg = <0 0x17c29000 0 0x1000>;
   4813				status = "disabled";
   4814			};
   4815
   4816			frame@17c2b000 {
   4817				frame-number = <5>;
   4818				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
   4819				reg = <0 0x17c2b000 0 0x1000>;
   4820				status = "disabled";
   4821			};
   4822
   4823			frame@17c2d000 {
   4824				frame-number = <6>;
   4825				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
   4826				reg = <0 0x17c2d000 0 0x1000>;
   4827				status = "disabled";
   4828			};
   4829		};
   4830
   4831		apps_rsc: rsc@18200000 {
   4832			compatible = "qcom,rpmh-rsc";
   4833			reg = <0 0x18200000 0 0x10000>,
   4834			      <0 0x18210000 0 0x10000>,
   4835			      <0 0x18220000 0 0x10000>;
   4836			reg-names = "drv-0", "drv-1", "drv-2";
   4837			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
   4838				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
   4839				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
   4840			qcom,tcs-offset = <0xd00>;
   4841			qcom,drv-id = <2>;
   4842			qcom,tcs-config = <ACTIVE_TCS  2>,
   4843					  <SLEEP_TCS   3>,
   4844					  <WAKE_TCS    3>,
   4845					  <CONTROL_TCS 1>;
   4846
   4847			apps_bcm_voter: bcm-voter {
   4848				compatible = "qcom,bcm-voter";
   4849			};
   4850
   4851			rpmhpd: power-controller {
   4852				compatible = "qcom,sc7280-rpmhpd";
   4853				#power-domain-cells = <1>;
   4854				operating-points-v2 = <&rpmhpd_opp_table>;
   4855
   4856				rpmhpd_opp_table: opp-table {
   4857					compatible = "operating-points-v2";
   4858
   4859					rpmhpd_opp_ret: opp1 {
   4860						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
   4861					};
   4862
   4863					rpmhpd_opp_low_svs: opp2 {
   4864						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
   4865					};
   4866
   4867					rpmhpd_opp_svs: opp3 {
   4868						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
   4869					};
   4870
   4871					rpmhpd_opp_svs_l1: opp4 {
   4872						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
   4873					};
   4874
   4875					rpmhpd_opp_svs_l2: opp5 {
   4876						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
   4877					};
   4878
   4879					rpmhpd_opp_nom: opp6 {
   4880						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
   4881					};
   4882
   4883					rpmhpd_opp_nom_l1: opp7 {
   4884						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
   4885					};
   4886
   4887					rpmhpd_opp_turbo: opp8 {
   4888						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
   4889					};
   4890
   4891					rpmhpd_opp_turbo_l1: opp9 {
   4892						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
   4893					};
   4894				};
   4895			};
   4896
   4897			rpmhcc: clock-controller {
   4898				compatible = "qcom,sc7280-rpmh-clk";
   4899				clocks = <&xo_board>;
   4900				clock-names = "xo";
   4901				#clock-cells = <1>;
   4902			};
   4903		};
   4904
   4905		epss_l3: interconnect@18590000 {
   4906			compatible = "qcom,sc7280-epss-l3";
   4907			reg = <0 0x18590000 0 0x1000>;
   4908			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
   4909			clock-names = "xo", "alternate";
   4910			#interconnect-cells = <1>;
   4911		};
   4912
   4913		cpufreq_hw: cpufreq@18591000 {
   4914			compatible = "qcom,cpufreq-epss";
   4915			reg = <0 0x18591000 0 0x1000>,
   4916			      <0 0x18592000 0 0x1000>,
   4917			      <0 0x18593000 0 0x1000>;
   4918			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
   4919			clock-names = "xo", "alternate";
   4920			#freq-domain-cells = <1>;
   4921		};
   4922	};
   4923
   4924	thermal_zones: thermal-zones {
   4925		cpu0-thermal {
   4926			polling-delay-passive = <250>;
   4927			polling-delay = <0>;
   4928
   4929			thermal-sensors = <&tsens0 1>;
   4930
   4931			trips {
   4932				cpu0_alert0: trip-point0 {
   4933					temperature = <90000>;
   4934					hysteresis = <2000>;
   4935					type = "passive";
   4936				};
   4937
   4938				cpu0_alert1: trip-point1 {
   4939					temperature = <95000>;
   4940					hysteresis = <2000>;
   4941					type = "passive";
   4942				};
   4943
   4944				cpu0_crit: cpu-crit {
   4945					temperature = <110000>;
   4946					hysteresis = <0>;
   4947					type = "critical";
   4948				};
   4949			};
   4950
   4951			cooling-maps {
   4952				map0 {
   4953					trip = <&cpu0_alert0>;
   4954					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   4955							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   4956							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   4957							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
   4958				};
   4959				map1 {
   4960					trip = <&cpu0_alert1>;
   4961					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   4962							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   4963							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   4964							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
   4965				};
   4966			};
   4967		};
   4968
   4969		cpu1-thermal {
   4970			polling-delay-passive = <250>;
   4971			polling-delay = <0>;
   4972
   4973			thermal-sensors = <&tsens0 2>;
   4974
   4975			trips {
   4976				cpu1_alert0: trip-point0 {
   4977					temperature = <90000>;
   4978					hysteresis = <2000>;
   4979					type = "passive";
   4980				};
   4981
   4982				cpu1_alert1: trip-point1 {
   4983					temperature = <95000>;
   4984					hysteresis = <2000>;
   4985					type = "passive";
   4986				};
   4987
   4988				cpu1_crit: cpu-crit {
   4989					temperature = <110000>;
   4990					hysteresis = <0>;
   4991					type = "critical";
   4992				};
   4993			};
   4994
   4995			cooling-maps {
   4996				map0 {
   4997					trip = <&cpu1_alert0>;
   4998					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   4999							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5000							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5001							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
   5002				};
   5003				map1 {
   5004					trip = <&cpu1_alert1>;
   5005					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5006							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5007							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5008							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
   5009				};
   5010			};
   5011		};
   5012
   5013		cpu2-thermal {
   5014			polling-delay-passive = <250>;
   5015			polling-delay = <0>;
   5016
   5017			thermal-sensors = <&tsens0 3>;
   5018
   5019			trips {
   5020				cpu2_alert0: trip-point0 {
   5021					temperature = <90000>;
   5022					hysteresis = <2000>;
   5023					type = "passive";
   5024				};
   5025
   5026				cpu2_alert1: trip-point1 {
   5027					temperature = <95000>;
   5028					hysteresis = <2000>;
   5029					type = "passive";
   5030				};
   5031
   5032				cpu2_crit: cpu-crit {
   5033					temperature = <110000>;
   5034					hysteresis = <0>;
   5035					type = "critical";
   5036				};
   5037			};
   5038
   5039			cooling-maps {
   5040				map0 {
   5041					trip = <&cpu2_alert0>;
   5042					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5043							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5044							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5045							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
   5046				};
   5047				map1 {
   5048					trip = <&cpu2_alert1>;
   5049					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5050							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5051							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5052							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
   5053				};
   5054			};
   5055		};
   5056
   5057		cpu3-thermal {
   5058			polling-delay-passive = <250>;
   5059			polling-delay = <0>;
   5060
   5061			thermal-sensors = <&tsens0 4>;
   5062
   5063			trips {
   5064				cpu3_alert0: trip-point0 {
   5065					temperature = <90000>;
   5066					hysteresis = <2000>;
   5067					type = "passive";
   5068				};
   5069
   5070				cpu3_alert1: trip-point1 {
   5071					temperature = <95000>;
   5072					hysteresis = <2000>;
   5073					type = "passive";
   5074				};
   5075
   5076				cpu3_crit: cpu-crit {
   5077					temperature = <110000>;
   5078					hysteresis = <0>;
   5079					type = "critical";
   5080				};
   5081			};
   5082
   5083			cooling-maps {
   5084				map0 {
   5085					trip = <&cpu3_alert0>;
   5086					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5087							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5088							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5089							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
   5090				};
   5091				map1 {
   5092					trip = <&cpu3_alert1>;
   5093					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5094							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5095							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5096							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
   5097				};
   5098			};
   5099		};
   5100
   5101		cpu4-thermal {
   5102			polling-delay-passive = <250>;
   5103			polling-delay = <0>;
   5104
   5105			thermal-sensors = <&tsens0 7>;
   5106
   5107			trips {
   5108				cpu4_alert0: trip-point0 {
   5109					temperature = <90000>;
   5110					hysteresis = <2000>;
   5111					type = "passive";
   5112				};
   5113
   5114				cpu4_alert1: trip-point1 {
   5115					temperature = <95000>;
   5116					hysteresis = <2000>;
   5117					type = "passive";
   5118				};
   5119
   5120				cpu4_crit: cpu-crit {
   5121					temperature = <110000>;
   5122					hysteresis = <0>;
   5123					type = "critical";
   5124				};
   5125			};
   5126
   5127			cooling-maps {
   5128				map0 {
   5129					trip = <&cpu4_alert0>;
   5130					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5131							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5132							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5133							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
   5134				};
   5135				map1 {
   5136					trip = <&cpu4_alert1>;
   5137					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5138							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5139							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5140							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
   5141				};
   5142			};
   5143		};
   5144
   5145		cpu5-thermal {
   5146			polling-delay-passive = <250>;
   5147			polling-delay = <0>;
   5148
   5149			thermal-sensors = <&tsens0 8>;
   5150
   5151			trips {
   5152				cpu5_alert0: trip-point0 {
   5153					temperature = <90000>;
   5154					hysteresis = <2000>;
   5155					type = "passive";
   5156				};
   5157
   5158				cpu5_alert1: trip-point1 {
   5159					temperature = <95000>;
   5160					hysteresis = <2000>;
   5161					type = "passive";
   5162				};
   5163
   5164				cpu5_crit: cpu-crit {
   5165					temperature = <110000>;
   5166					hysteresis = <0>;
   5167					type = "critical";
   5168				};
   5169			};
   5170
   5171			cooling-maps {
   5172				map0 {
   5173					trip = <&cpu5_alert0>;
   5174					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5175							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5176							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5177							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
   5178				};
   5179				map1 {
   5180					trip = <&cpu5_alert1>;
   5181					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5182							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5183							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5184							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
   5185				};
   5186			};
   5187		};
   5188
   5189		cpu6-thermal {
   5190			polling-delay-passive = <250>;
   5191			polling-delay = <0>;
   5192
   5193			thermal-sensors = <&tsens0 9>;
   5194
   5195			trips {
   5196				cpu6_alert0: trip-point0 {
   5197					temperature = <90000>;
   5198					hysteresis = <2000>;
   5199					type = "passive";
   5200				};
   5201
   5202				cpu6_alert1: trip-point1 {
   5203					temperature = <95000>;
   5204					hysteresis = <2000>;
   5205					type = "passive";
   5206				};
   5207
   5208				cpu6_crit: cpu-crit {
   5209					temperature = <110000>;
   5210					hysteresis = <0>;
   5211					type = "critical";
   5212				};
   5213			};
   5214
   5215			cooling-maps {
   5216				map0 {
   5217					trip = <&cpu6_alert0>;
   5218					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5219							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5220							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5221							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
   5222				};
   5223				map1 {
   5224					trip = <&cpu6_alert1>;
   5225					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5226							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5227							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5228							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
   5229				};
   5230			};
   5231		};
   5232
   5233		cpu7-thermal {
   5234			polling-delay-passive = <250>;
   5235			polling-delay = <0>;
   5236
   5237			thermal-sensors = <&tsens0 10>;
   5238
   5239			trips {
   5240				cpu7_alert0: trip-point0 {
   5241					temperature = <90000>;
   5242					hysteresis = <2000>;
   5243					type = "passive";
   5244				};
   5245
   5246				cpu7_alert1: trip-point1 {
   5247					temperature = <95000>;
   5248					hysteresis = <2000>;
   5249					type = "passive";
   5250				};
   5251
   5252				cpu7_crit: cpu-crit {
   5253					temperature = <110000>;
   5254					hysteresis = <0>;
   5255					type = "critical";
   5256				};
   5257			};
   5258
   5259			cooling-maps {
   5260				map0 {
   5261					trip = <&cpu7_alert0>;
   5262					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5263							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5264							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5265							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
   5266				};
   5267				map1 {
   5268					trip = <&cpu7_alert1>;
   5269					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5270							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5271							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5272							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
   5273				};
   5274			};
   5275		};
   5276
   5277		cpu8-thermal {
   5278			polling-delay-passive = <250>;
   5279			polling-delay = <0>;
   5280
   5281			thermal-sensors = <&tsens0 11>;
   5282
   5283			trips {
   5284				cpu8_alert0: trip-point0 {
   5285					temperature = <90000>;
   5286					hysteresis = <2000>;
   5287					type = "passive";
   5288				};
   5289
   5290				cpu8_alert1: trip-point1 {
   5291					temperature = <95000>;
   5292					hysteresis = <2000>;
   5293					type = "passive";
   5294				};
   5295
   5296				cpu8_crit: cpu-crit {
   5297					temperature = <110000>;
   5298					hysteresis = <0>;
   5299					type = "critical";
   5300				};
   5301			};
   5302
   5303			cooling-maps {
   5304				map0 {
   5305					trip = <&cpu8_alert0>;
   5306					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5307							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5308							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5309							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
   5310				};
   5311				map1 {
   5312					trip = <&cpu8_alert1>;
   5313					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5314							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5315							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5316							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
   5317				};
   5318			};
   5319		};
   5320
   5321		cpu9-thermal {
   5322			polling-delay-passive = <250>;
   5323			polling-delay = <0>;
   5324
   5325			thermal-sensors = <&tsens0 12>;
   5326
   5327			trips {
   5328				cpu9_alert0: trip-point0 {
   5329					temperature = <90000>;
   5330					hysteresis = <2000>;
   5331					type = "passive";
   5332				};
   5333
   5334				cpu9_alert1: trip-point1 {
   5335					temperature = <95000>;
   5336					hysteresis = <2000>;
   5337					type = "passive";
   5338				};
   5339
   5340				cpu9_crit: cpu-crit {
   5341					temperature = <110000>;
   5342					hysteresis = <0>;
   5343					type = "critical";
   5344				};
   5345			};
   5346
   5347			cooling-maps {
   5348				map0 {
   5349					trip = <&cpu9_alert0>;
   5350					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5351							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5352							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5353							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
   5354				};
   5355				map1 {
   5356					trip = <&cpu9_alert1>;
   5357					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5358							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5359							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5360							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
   5361				};
   5362			};
   5363		};
   5364
   5365		cpu10-thermal {
   5366			polling-delay-passive = <250>;
   5367			polling-delay = <0>;
   5368
   5369			thermal-sensors = <&tsens0 13>;
   5370
   5371			trips {
   5372				cpu10_alert0: trip-point0 {
   5373					temperature = <90000>;
   5374					hysteresis = <2000>;
   5375					type = "passive";
   5376				};
   5377
   5378				cpu10_alert1: trip-point1 {
   5379					temperature = <95000>;
   5380					hysteresis = <2000>;
   5381					type = "passive";
   5382				};
   5383
   5384				cpu10_crit: cpu-crit {
   5385					temperature = <110000>;
   5386					hysteresis = <0>;
   5387					type = "critical";
   5388				};
   5389			};
   5390
   5391			cooling-maps {
   5392				map0 {
   5393					trip = <&cpu10_alert0>;
   5394					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5395							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5396							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5397							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
   5398				};
   5399				map1 {
   5400					trip = <&cpu10_alert1>;
   5401					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5402							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5403							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5404							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
   5405				};
   5406			};
   5407		};
   5408
   5409		cpu11-thermal {
   5410			polling-delay-passive = <250>;
   5411			polling-delay = <0>;
   5412
   5413			thermal-sensors = <&tsens0 14>;
   5414
   5415			trips {
   5416				cpu11_alert0: trip-point0 {
   5417					temperature = <90000>;
   5418					hysteresis = <2000>;
   5419					type = "passive";
   5420				};
   5421
   5422				cpu11_alert1: trip-point1 {
   5423					temperature = <95000>;
   5424					hysteresis = <2000>;
   5425					type = "passive";
   5426				};
   5427
   5428				cpu11_crit: cpu-crit {
   5429					temperature = <110000>;
   5430					hysteresis = <0>;
   5431					type = "critical";
   5432				};
   5433			};
   5434
   5435			cooling-maps {
   5436				map0 {
   5437					trip = <&cpu11_alert0>;
   5438					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5439							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5440							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5441							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
   5442				};
   5443				map1 {
   5444					trip = <&cpu11_alert1>;
   5445					cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5446							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5447							 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
   5448							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
   5449				};
   5450			};
   5451		};
   5452
   5453		aoss0-thermal {
   5454			polling-delay-passive = <0>;
   5455			polling-delay = <0>;
   5456
   5457			thermal-sensors = <&tsens0 0>;
   5458
   5459			trips {
   5460				aoss0_alert0: trip-point0 {
   5461					temperature = <90000>;
   5462					hysteresis = <2000>;
   5463					type = "hot";
   5464				};
   5465
   5466				aoss0_crit: aoss0-crit {
   5467					temperature = <110000>;
   5468					hysteresis = <0>;
   5469					type = "critical";
   5470				};
   5471			};
   5472		};
   5473
   5474		aoss1-thermal {
   5475			polling-delay-passive = <0>;
   5476			polling-delay = <0>;
   5477
   5478			thermal-sensors = <&tsens1 0>;
   5479
   5480			trips {
   5481				aoss1_alert0: trip-point0 {
   5482					temperature = <90000>;
   5483					hysteresis = <2000>;
   5484					type = "hot";
   5485				};
   5486
   5487				aoss1_crit: aoss1-crit {
   5488					temperature = <110000>;
   5489					hysteresis = <0>;
   5490					type = "critical";
   5491				};
   5492			};
   5493		};
   5494
   5495		cpuss0-thermal {
   5496			polling-delay-passive = <0>;
   5497			polling-delay = <0>;
   5498
   5499			thermal-sensors = <&tsens0 5>;
   5500
   5501			trips {
   5502				cpuss0_alert0: trip-point0 {
   5503					temperature = <90000>;
   5504					hysteresis = <2000>;
   5505					type = "hot";
   5506				};
   5507				cpuss0_crit: cluster0-crit {
   5508					temperature = <110000>;
   5509					hysteresis = <0>;
   5510					type = "critical";
   5511				};
   5512			};
   5513		};
   5514
   5515		cpuss1-thermal {
   5516			polling-delay-passive = <0>;
   5517			polling-delay = <0>;
   5518
   5519			thermal-sensors = <&tsens0 6>;
   5520
   5521			trips {
   5522				cpuss1_alert0: trip-point0 {
   5523					temperature = <90000>;
   5524					hysteresis = <2000>;
   5525					type = "hot";
   5526				};
   5527				cpuss1_crit: cluster0-crit {
   5528					temperature = <110000>;
   5529					hysteresis = <0>;
   5530					type = "critical";
   5531				};
   5532			};
   5533		};
   5534
   5535		gpuss0-thermal {
   5536			polling-delay-passive = <100>;
   5537			polling-delay = <0>;
   5538
   5539			thermal-sensors = <&tsens1 1>;
   5540
   5541			trips {
   5542				gpuss0_alert0: trip-point0 {
   5543					temperature = <95000>;
   5544					hysteresis = <2000>;
   5545					type = "passive";
   5546				};
   5547
   5548				gpuss0_crit: gpuss0-crit {
   5549					temperature = <110000>;
   5550					hysteresis = <0>;
   5551					type = "critical";
   5552				};
   5553			};
   5554
   5555			cooling-maps {
   5556				map0 {
   5557					trip = <&gpuss0_alert0>;
   5558					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
   5559				};
   5560			};
   5561		};
   5562
   5563		gpuss1-thermal {
   5564			polling-delay-passive = <100>;
   5565			polling-delay = <0>;
   5566
   5567			thermal-sensors = <&tsens1 2>;
   5568
   5569			trips {
   5570				gpuss1_alert0: trip-point0 {
   5571					temperature = <95000>;
   5572					hysteresis = <2000>;
   5573					type = "passive";
   5574				};
   5575
   5576				gpuss1_crit: gpuss1-crit {
   5577					temperature = <110000>;
   5578					hysteresis = <0>;
   5579					type = "critical";
   5580				};
   5581			};
   5582
   5583			cooling-maps {
   5584				map0 {
   5585					trip = <&gpuss1_alert0>;
   5586					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
   5587				};
   5588			};
   5589		};
   5590
   5591		nspss0-thermal {
   5592			polling-delay-passive = <0>;
   5593			polling-delay = <0>;
   5594
   5595			thermal-sensors = <&tsens1 3>;
   5596
   5597			trips {
   5598				nspss0_alert0: trip-point0 {
   5599					temperature = <90000>;
   5600					hysteresis = <2000>;
   5601					type = "hot";
   5602				};
   5603
   5604				nspss0_crit: nspss0-crit {
   5605					temperature = <110000>;
   5606					hysteresis = <0>;
   5607					type = "critical";
   5608				};
   5609			};
   5610		};
   5611
   5612		nspss1-thermal {
   5613			polling-delay-passive = <0>;
   5614			polling-delay = <0>;
   5615
   5616			thermal-sensors = <&tsens1 4>;
   5617
   5618			trips {
   5619				nspss1_alert0: trip-point0 {
   5620					temperature = <90000>;
   5621					hysteresis = <2000>;
   5622					type = "hot";
   5623				};
   5624
   5625				nspss1_crit: nspss1-crit {
   5626					temperature = <110000>;
   5627					hysteresis = <0>;
   5628					type = "critical";
   5629				};
   5630			};
   5631		};
   5632
   5633		video-thermal {
   5634			polling-delay-passive = <0>;
   5635			polling-delay = <0>;
   5636
   5637			thermal-sensors = <&tsens1 5>;
   5638
   5639			trips {
   5640				video_alert0: trip-point0 {
   5641					temperature = <90000>;
   5642					hysteresis = <2000>;
   5643					type = "hot";
   5644				};
   5645
   5646				video_crit: video-crit {
   5647					temperature = <110000>;
   5648					hysteresis = <0>;
   5649					type = "critical";
   5650				};
   5651			};
   5652		};
   5653
   5654		ddr-thermal {
   5655			polling-delay-passive = <0>;
   5656			polling-delay = <0>;
   5657
   5658			thermal-sensors = <&tsens1 6>;
   5659
   5660			trips {
   5661				ddr_alert0: trip-point0 {
   5662					temperature = <90000>;
   5663					hysteresis = <2000>;
   5664					type = "hot";
   5665				};
   5666
   5667				ddr_crit: ddr-crit {
   5668					temperature = <110000>;
   5669					hysteresis = <0>;
   5670					type = "critical";
   5671				};
   5672			};
   5673		};
   5674
   5675		mdmss0-thermal {
   5676			polling-delay-passive = <0>;
   5677			polling-delay = <0>;
   5678
   5679			thermal-sensors = <&tsens1 7>;
   5680
   5681			trips {
   5682				mdmss0_alert0: trip-point0 {
   5683					temperature = <90000>;
   5684					hysteresis = <2000>;
   5685					type = "hot";
   5686				};
   5687
   5688				mdmss0_crit: mdmss0-crit {
   5689					temperature = <110000>;
   5690					hysteresis = <0>;
   5691					type = "critical";
   5692				};
   5693			};
   5694		};
   5695
   5696		mdmss1-thermal {
   5697			polling-delay-passive = <0>;
   5698			polling-delay = <0>;
   5699
   5700			thermal-sensors = <&tsens1 8>;
   5701
   5702			trips {
   5703				mdmss1_alert0: trip-point0 {
   5704					temperature = <90000>;
   5705					hysteresis = <2000>;
   5706					type = "hot";
   5707				};
   5708
   5709				mdmss1_crit: mdmss1-crit {
   5710					temperature = <110000>;
   5711					hysteresis = <0>;
   5712					type = "critical";
   5713				};
   5714			};
   5715		};
   5716
   5717		mdmss2-thermal {
   5718			polling-delay-passive = <0>;
   5719			polling-delay = <0>;
   5720
   5721			thermal-sensors = <&tsens1 9>;
   5722
   5723			trips {
   5724				mdmss2_alert0: trip-point0 {
   5725					temperature = <90000>;
   5726					hysteresis = <2000>;
   5727					type = "hot";
   5728				};
   5729
   5730				mdmss2_crit: mdmss2-crit {
   5731					temperature = <110000>;
   5732					hysteresis = <0>;
   5733					type = "critical";
   5734				};
   5735			};
   5736		};
   5737
   5738		mdmss3-thermal {
   5739			polling-delay-passive = <0>;
   5740			polling-delay = <0>;
   5741
   5742			thermal-sensors = <&tsens1 10>;
   5743
   5744			trips {
   5745				mdmss3_alert0: trip-point0 {
   5746					temperature = <90000>;
   5747					hysteresis = <2000>;
   5748					type = "hot";
   5749				};
   5750
   5751				mdmss3_crit: mdmss3-crit {
   5752					temperature = <110000>;
   5753					hysteresis = <0>;
   5754					type = "critical";
   5755				};
   5756			};
   5757		};
   5758
   5759		camera0-thermal {
   5760			polling-delay-passive = <0>;
   5761			polling-delay = <0>;
   5762
   5763			thermal-sensors = <&tsens1 11>;
   5764
   5765			trips {
   5766				camera0_alert0: trip-point0 {
   5767					temperature = <90000>;
   5768					hysteresis = <2000>;
   5769					type = "hot";
   5770				};
   5771
   5772				camera0_crit: camera0-crit {
   5773					temperature = <110000>;
   5774					hysteresis = <0>;
   5775					type = "critical";
   5776				};
   5777			};
   5778		};
   5779	};
   5780
   5781	timer {
   5782		compatible = "arm,armv8-timer";
   5783		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
   5784			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
   5785			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
   5786			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
   5787	};
   5788};