sdm630.dtsi (58276B)
1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com> 4 * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com> 5 */ 6 7#include <dt-bindings/clock/qcom,gcc-sdm660.h> 8#include <dt-bindings/clock/qcom,gpucc-sdm660.h> 9#include <dt-bindings/clock/qcom,mmcc-sdm660.h> 10#include <dt-bindings/clock/qcom,rpmcc.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/soc/qcom,apr.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 mmc1 = &sdhc_1; 24 mmc2 = &sdhc_2; 25 }; 26 27 chosen { }; 28 29 clocks { 30 xo_board: xo-board { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <19200000>; 34 clock-output-names = "xo_board"; 35 }; 36 37 sleep_clk: sleep-clk { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <32764>; 41 clock-output-names = "sleep_clk"; 42 }; 43 }; 44 45 cpus { 46 #address-cells = <2>; 47 #size-cells = <0>; 48 49 CPU0: cpu@100 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53"; 52 reg = <0x0 0x100>; 53 enable-method = "psci"; 54 cpu-idle-states = <&PERF_CPU_SLEEP_0 55 &PERF_CPU_SLEEP_1 56 &PERF_CLUSTER_SLEEP_0 57 &PERF_CLUSTER_SLEEP_1 58 &PERF_CLUSTER_SLEEP_2>; 59 capacity-dmips-mhz = <1126>; 60 #cooling-cells = <2>; 61 next-level-cache = <&L2_1>; 62 L2_1: l2-cache { 63 compatible = "cache"; 64 cache-level = <2>; 65 }; 66 }; 67 68 CPU1: cpu@101 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53"; 71 reg = <0x0 0x101>; 72 enable-method = "psci"; 73 cpu-idle-states = <&PERF_CPU_SLEEP_0 74 &PERF_CPU_SLEEP_1 75 &PERF_CLUSTER_SLEEP_0 76 &PERF_CLUSTER_SLEEP_1 77 &PERF_CLUSTER_SLEEP_2>; 78 capacity-dmips-mhz = <1126>; 79 #cooling-cells = <2>; 80 next-level-cache = <&L2_1>; 81 }; 82 83 CPU2: cpu@102 { 84 device_type = "cpu"; 85 compatible = "arm,cortex-a53"; 86 reg = <0x0 0x102>; 87 enable-method = "psci"; 88 cpu-idle-states = <&PERF_CPU_SLEEP_0 89 &PERF_CPU_SLEEP_1 90 &PERF_CLUSTER_SLEEP_0 91 &PERF_CLUSTER_SLEEP_1 92 &PERF_CLUSTER_SLEEP_2>; 93 capacity-dmips-mhz = <1126>; 94 #cooling-cells = <2>; 95 next-level-cache = <&L2_1>; 96 }; 97 98 CPU3: cpu@103 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a53"; 101 reg = <0x0 0x103>; 102 enable-method = "psci"; 103 cpu-idle-states = <&PERF_CPU_SLEEP_0 104 &PERF_CPU_SLEEP_1 105 &PERF_CLUSTER_SLEEP_0 106 &PERF_CLUSTER_SLEEP_1 107 &PERF_CLUSTER_SLEEP_2>; 108 capacity-dmips-mhz = <1126>; 109 #cooling-cells = <2>; 110 next-level-cache = <&L2_1>; 111 }; 112 113 CPU4: cpu@0 { 114 device_type = "cpu"; 115 compatible = "arm,cortex-a53"; 116 reg = <0x0 0x0>; 117 enable-method = "psci"; 118 cpu-idle-states = <&PWR_CPU_SLEEP_0 119 &PWR_CPU_SLEEP_1 120 &PWR_CLUSTER_SLEEP_0 121 &PWR_CLUSTER_SLEEP_1 122 &PWR_CLUSTER_SLEEP_2>; 123 capacity-dmips-mhz = <1024>; 124 #cooling-cells = <2>; 125 next-level-cache = <&L2_0>; 126 L2_0: l2-cache { 127 compatible = "cache"; 128 cache-level = <2>; 129 }; 130 }; 131 132 CPU5: cpu@1 { 133 device_type = "cpu"; 134 compatible = "arm,cortex-a53"; 135 reg = <0x0 0x1>; 136 enable-method = "psci"; 137 cpu-idle-states = <&PWR_CPU_SLEEP_0 138 &PWR_CPU_SLEEP_1 139 &PWR_CLUSTER_SLEEP_0 140 &PWR_CLUSTER_SLEEP_1 141 &PWR_CLUSTER_SLEEP_2>; 142 capacity-dmips-mhz = <1024>; 143 #cooling-cells = <2>; 144 next-level-cache = <&L2_0>; 145 }; 146 147 CPU6: cpu@2 { 148 device_type = "cpu"; 149 compatible = "arm,cortex-a53"; 150 reg = <0x0 0x2>; 151 enable-method = "psci"; 152 cpu-idle-states = <&PWR_CPU_SLEEP_0 153 &PWR_CPU_SLEEP_1 154 &PWR_CLUSTER_SLEEP_0 155 &PWR_CLUSTER_SLEEP_1 156 &PWR_CLUSTER_SLEEP_2>; 157 capacity-dmips-mhz = <1024>; 158 #cooling-cells = <2>; 159 next-level-cache = <&L2_0>; 160 }; 161 162 CPU7: cpu@3 { 163 device_type = "cpu"; 164 compatible = "arm,cortex-a53"; 165 reg = <0x0 0x3>; 166 enable-method = "psci"; 167 cpu-idle-states = <&PWR_CPU_SLEEP_0 168 &PWR_CPU_SLEEP_1 169 &PWR_CLUSTER_SLEEP_0 170 &PWR_CLUSTER_SLEEP_1 171 &PWR_CLUSTER_SLEEP_2>; 172 capacity-dmips-mhz = <1024>; 173 #cooling-cells = <2>; 174 next-level-cache = <&L2_0>; 175 }; 176 177 cpu-map { 178 cluster0 { 179 core0 { 180 cpu = <&CPU4>; 181 }; 182 183 core1 { 184 cpu = <&CPU5>; 185 }; 186 187 core2 { 188 cpu = <&CPU6>; 189 }; 190 191 core3 { 192 cpu = <&CPU7>; 193 }; 194 }; 195 196 cluster1 { 197 core0 { 198 cpu = <&CPU0>; 199 }; 200 201 core1 { 202 cpu = <&CPU1>; 203 }; 204 205 core2 { 206 cpu = <&CPU2>; 207 }; 208 209 core3 { 210 cpu = <&CPU3>; 211 }; 212 }; 213 }; 214 215 idle-states { 216 entry-method = "psci"; 217 218 PWR_CPU_SLEEP_0: cpu-sleep-0-0 { 219 compatible = "arm,idle-state"; 220 idle-state-name = "pwr-retention"; 221 arm,psci-suspend-param = <0x40000002>; 222 entry-latency-us = <338>; 223 exit-latency-us = <423>; 224 min-residency-us = <200>; 225 }; 226 227 PWR_CPU_SLEEP_1: cpu-sleep-0-1 { 228 compatible = "arm,idle-state"; 229 idle-state-name = "pwr-power-collapse"; 230 arm,psci-suspend-param = <0x40000003>; 231 entry-latency-us = <515>; 232 exit-latency-us = <1821>; 233 min-residency-us = <1000>; 234 local-timer-stop; 235 }; 236 237 PERF_CPU_SLEEP_0: cpu-sleep-1-0 { 238 compatible = "arm,idle-state"; 239 idle-state-name = "perf-retention"; 240 arm,psci-suspend-param = <0x40000002>; 241 entry-latency-us = <154>; 242 exit-latency-us = <87>; 243 min-residency-us = <200>; 244 }; 245 246 PERF_CPU_SLEEP_1: cpu-sleep-1-1 { 247 compatible = "arm,idle-state"; 248 idle-state-name = "perf-power-collapse"; 249 arm,psci-suspend-param = <0x40000003>; 250 entry-latency-us = <262>; 251 exit-latency-us = <301>; 252 min-residency-us = <1000>; 253 local-timer-stop; 254 }; 255 256 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 { 257 compatible = "arm,idle-state"; 258 idle-state-name = "pwr-cluster-dynamic-retention"; 259 arm,psci-suspend-param = <0x400000F2>; 260 entry-latency-us = <284>; 261 exit-latency-us = <384>; 262 min-residency-us = <9987>; 263 local-timer-stop; 264 }; 265 266 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 { 267 compatible = "arm,idle-state"; 268 idle-state-name = "pwr-cluster-retention"; 269 arm,psci-suspend-param = <0x400000F3>; 270 entry-latency-us = <338>; 271 exit-latency-us = <423>; 272 min-residency-us = <9987>; 273 local-timer-stop; 274 }; 275 276 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 { 277 compatible = "arm,idle-state"; 278 idle-state-name = "pwr-cluster-retention"; 279 arm,psci-suspend-param = <0x400000F4>; 280 entry-latency-us = <515>; 281 exit-latency-us = <1821>; 282 min-residency-us = <9987>; 283 local-timer-stop; 284 }; 285 286 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 { 287 compatible = "arm,idle-state"; 288 idle-state-name = "perf-cluster-dynamic-retention"; 289 arm,psci-suspend-param = <0x400000F2>; 290 entry-latency-us = <272>; 291 exit-latency-us = <329>; 292 min-residency-us = <9987>; 293 local-timer-stop; 294 }; 295 296 PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 { 297 compatible = "arm,idle-state"; 298 idle-state-name = "perf-cluster-retention"; 299 arm,psci-suspend-param = <0x400000F3>; 300 entry-latency-us = <332>; 301 exit-latency-us = <368>; 302 min-residency-us = <9987>; 303 local-timer-stop; 304 }; 305 306 PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 { 307 compatible = "arm,idle-state"; 308 idle-state-name = "perf-cluster-retention"; 309 arm,psci-suspend-param = <0x400000F4>; 310 entry-latency-us = <545>; 311 exit-latency-us = <1609>; 312 min-residency-us = <9987>; 313 local-timer-stop; 314 }; 315 }; 316 }; 317 318 firmware { 319 scm { 320 compatible = "qcom,scm-msm8998", "qcom,scm"; 321 }; 322 }; 323 324 memory@80000000 { 325 device_type = "memory"; 326 /* We expect the bootloader to fill in the reg */ 327 reg = <0x0 0x80000000 0x0 0x0>; 328 }; 329 330 pmu { 331 compatible = "arm,armv8-pmuv3"; 332 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 333 }; 334 335 psci { 336 compatible = "arm,psci-1.0"; 337 method = "smc"; 338 }; 339 340 reserved-memory { 341 #address-cells = <2>; 342 #size-cells = <2>; 343 ranges; 344 345 wlan_msa_guard: wlan-msa-guard@85600000 { 346 reg = <0x0 0x85600000 0x0 0x100000>; 347 no-map; 348 }; 349 350 wlan_msa_mem: wlan-msa-mem@85700000 { 351 reg = <0x0 0x85700000 0x0 0x100000>; 352 no-map; 353 }; 354 355 qhee_code: qhee-code@85800000 { 356 reg = <0x0 0x85800000 0x0 0x600000>; 357 no-map; 358 }; 359 360 rmtfs_mem: memory@85e00000 { 361 compatible = "qcom,rmtfs-mem"; 362 reg = <0x0 0x85e00000 0x0 0x200000>; 363 no-map; 364 365 qcom,client-id = <1>; 366 qcom,vmid = <15>; 367 }; 368 369 smem_region: smem-mem@86000000 { 370 reg = <0 0x86000000 0 0x200000>; 371 no-map; 372 }; 373 374 tz_mem: memory@86200000 { 375 reg = <0x0 0x86200000 0x0 0x3300000>; 376 no-map; 377 }; 378 379 mpss_region: mpss@8ac00000 { 380 reg = <0x0 0x8ac00000 0x0 0x7e00000>; 381 no-map; 382 }; 383 384 adsp_region: adsp@92a00000 { 385 reg = <0x0 0x92a00000 0x0 0x1e00000>; 386 no-map; 387 }; 388 389 mba_region: mba@94800000 { 390 reg = <0x0 0x94800000 0x0 0x200000>; 391 no-map; 392 }; 393 394 buffer_mem: tzbuffer@94a00000 { 395 reg = <0x0 0x94a00000 0x0 0x100000>; 396 no-map; 397 }; 398 399 venus_region: venus@9f800000 { 400 reg = <0x0 0x9f800000 0x0 0x800000>; 401 no-map; 402 }; 403 404 adsp_mem: adsp-region@f6000000 { 405 reg = <0x0 0xf6000000 0x0 0x800000>; 406 no-map; 407 }; 408 409 qseecom_mem: qseecom-region@f6800000 { 410 reg = <0x0 0xf6800000 0x0 0x1400000>; 411 no-map; 412 }; 413 414 zap_shader_region: gpu@fed00000 { 415 compatible = "shared-dma-pool"; 416 reg = <0x0 0xfed00000 0x0 0xa00000>; 417 no-map; 418 }; 419 }; 420 421 rpm-glink { 422 compatible = "qcom,glink-rpm"; 423 424 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 425 qcom,rpm-msg-ram = <&rpm_msg_ram>; 426 mboxes = <&apcs_glb 0>; 427 428 rpm_requests: rpm-requests { 429 compatible = "qcom,rpm-sdm660"; 430 qcom,glink-channels = "rpm_requests"; 431 432 rpmcc: clock-controller { 433 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; 434 #clock-cells = <1>; 435 }; 436 437 rpmpd: power-controller { 438 compatible = "qcom,sdm660-rpmpd"; 439 #power-domain-cells = <1>; 440 operating-points-v2 = <&rpmpd_opp_table>; 441 442 rpmpd_opp_table: opp-table { 443 compatible = "operating-points-v2"; 444 445 rpmpd_opp_ret: opp1 { 446 opp-level = <RPM_SMD_LEVEL_RETENTION>; 447 }; 448 449 rpmpd_opp_ret_plus: opp2 { 450 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 451 }; 452 453 rpmpd_opp_min_svs: opp3 { 454 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 455 }; 456 457 rpmpd_opp_low_svs: opp4 { 458 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 459 }; 460 461 rpmpd_opp_svs: opp5 { 462 opp-level = <RPM_SMD_LEVEL_SVS>; 463 }; 464 465 rpmpd_opp_svs_plus: opp6 { 466 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 467 }; 468 469 rpmpd_opp_nom: opp7 { 470 opp-level = <RPM_SMD_LEVEL_NOM>; 471 }; 472 473 rpmpd_opp_nom_plus: opp8 { 474 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 475 }; 476 477 rpmpd_opp_turbo: opp9 { 478 opp-level = <RPM_SMD_LEVEL_TURBO>; 479 }; 480 }; 481 }; 482 }; 483 }; 484 485 smem: smem { 486 compatible = "qcom,smem"; 487 memory-region = <&smem_region>; 488 hwlocks = <&tcsr_mutex 3>; 489 }; 490 491 smp2p-adsp { 492 compatible = "qcom,smp2p"; 493 qcom,smem = <443>, <429>; 494 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 495 mboxes = <&apcs_glb 10>; 496 qcom,local-pid = <0>; 497 qcom,remote-pid = <2>; 498 499 adsp_smp2p_out: master-kernel { 500 qcom,entry-name = "master-kernel"; 501 #qcom,smem-state-cells = <1>; 502 }; 503 504 adsp_smp2p_in: slave-kernel { 505 qcom,entry-name = "slave-kernel"; 506 interrupt-controller; 507 #interrupt-cells = <2>; 508 }; 509 }; 510 511 smp2p-mpss { 512 compatible = "qcom,smp2p"; 513 qcom,smem = <435>, <428>; 514 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 515 mboxes = <&apcs_glb 14>; 516 qcom,local-pid = <0>; 517 qcom,remote-pid = <1>; 518 519 modem_smp2p_out: master-kernel { 520 qcom,entry-name = "master-kernel"; 521 #qcom,smem-state-cells = <1>; 522 }; 523 524 modem_smp2p_in: slave-kernel { 525 qcom,entry-name = "slave-kernel"; 526 interrupt-controller; 527 #interrupt-cells = <2>; 528 }; 529 }; 530 531 soc { 532 #address-cells = <1>; 533 #size-cells = <1>; 534 ranges = <0 0 0 0xffffffff>; 535 compatible = "simple-bus"; 536 537 gcc: clock-controller@100000 { 538 compatible = "qcom,gcc-sdm630"; 539 #clock-cells = <1>; 540 #reset-cells = <1>; 541 #power-domain-cells = <1>; 542 reg = <0x00100000 0x94000>; 543 544 clock-names = "xo", "sleep_clk"; 545 clocks = <&xo_board>, 546 <&sleep_clk>; 547 }; 548 549 rpm_msg_ram: sram@778000 { 550 compatible = "qcom,rpm-msg-ram"; 551 reg = <0x00778000 0x7000>; 552 }; 553 554 qfprom: qfprom@780000 { 555 compatible = "qcom,qfprom"; 556 reg = <0x00780000 0x621c>; 557 #address-cells = <1>; 558 #size-cells = <1>; 559 560 qusb2_hstx_trim: hstx-trim@240 { 561 reg = <0x240 0x1>; 562 bits = <25 3>; 563 }; 564 565 gpu_speed_bin: gpu-speed-bin@41a0 { 566 reg = <0x41a0 0x1>; 567 bits = <21 7>; 568 }; 569 }; 570 571 rng: rng@793000 { 572 compatible = "qcom,prng-ee"; 573 reg = <0x00793000 0x1000>; 574 clocks = <&gcc GCC_PRNG_AHB_CLK>; 575 clock-names = "core"; 576 }; 577 578 bimc: interconnect@1008000 { 579 compatible = "qcom,sdm660-bimc"; 580 reg = <0x01008000 0x78000>; 581 #interconnect-cells = <1>; 582 clock-names = "bus", "bus_a"; 583 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 584 <&rpmcc RPM_SMD_BIMC_A_CLK>; 585 }; 586 587 restart@10ac000 { 588 compatible = "qcom,pshold"; 589 reg = <0x010ac000 0x4>; 590 }; 591 592 cnoc: interconnect@1500000 { 593 compatible = "qcom,sdm660-cnoc"; 594 reg = <0x01500000 0x10000>; 595 #interconnect-cells = <1>; 596 clock-names = "bus", "bus_a"; 597 clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 598 <&rpmcc RPM_SMD_CNOC_A_CLK>; 599 }; 600 601 snoc: interconnect@1626000 { 602 compatible = "qcom,sdm660-snoc"; 603 reg = <0x01626000 0x7090>; 604 #interconnect-cells = <1>; 605 clock-names = "bus", "bus_a"; 606 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 607 <&rpmcc RPM_SMD_SNOC_A_CLK>; 608 }; 609 610 anoc2_smmu: iommu@16c0000 { 611 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 612 reg = <0x016c0000 0x40000>; 613 614 assigned-clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 615 assigned-clock-rates = <1000>; 616 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 617 clock-names = "bus"; 618 #global-interrupts = <2>; 619 #iommu-cells = <1>; 620 621 interrupts = 622 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 624 625 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>, 627 <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>, 628 <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>, 629 <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>, 630 <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>, 631 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 654 655 status = "disabled"; 656 }; 657 658 a2noc: interconnect@1704000 { 659 compatible = "qcom,sdm660-a2noc"; 660 reg = <0x01704000 0xc100>; 661 #interconnect-cells = <1>; 662 clock-names = "bus", 663 "bus_a", 664 "ipa", 665 "ufs_axi", 666 "aggre2_ufs_axi", 667 "aggre2_usb3_axi", 668 "cfg_noc_usb2_axi"; 669 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 670 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>, 671 <&rpmcc RPM_SMD_IPA_CLK>, 672 <&gcc GCC_UFS_AXI_CLK>, 673 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 674 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 675 <&gcc GCC_CFG_NOC_USB2_AXI_CLK>; 676 }; 677 678 mnoc: interconnect@1745000 { 679 compatible = "qcom,sdm660-mnoc"; 680 reg = <0x01745000 0xA010>; 681 #interconnect-cells = <1>; 682 clock-names = "bus", "bus_a", "iface"; 683 clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, 684 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>, 685 <&mmcc AHB_CLK_SRC>; 686 }; 687 688 tsens: thermal-sensor@10ae000 { 689 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2"; 690 reg = <0x010ae000 0x1000>, /* TM */ 691 <0x010ad000 0x1000>; /* SROT */ 692 #qcom,sensors = <12>; 693 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 695 interrupt-names = "uplow", "critical"; 696 #thermal-sensor-cells = <1>; 697 }; 698 699 tcsr_mutex_regs: syscon@1f40000 { 700 compatible = "syscon"; 701 reg = <0x01f40000 0x40000>; 702 }; 703 704 tlmm: pinctrl@3100000 { 705 compatible = "qcom,sdm630-pinctrl"; 706 reg = <0x03100000 0x400000>, 707 <0x03500000 0x400000>, 708 <0x03900000 0x400000>; 709 reg-names = "south", "center", "north"; 710 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 711 gpio-controller; 712 gpio-ranges = <&tlmm 0 0 114>; 713 #gpio-cells = <2>; 714 interrupt-controller; 715 #interrupt-cells = <2>; 716 717 blsp1_uart1_default: blsp1-uart1-default { 718 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 719 drive-strength = <2>; 720 bias-disable; 721 }; 722 723 blsp1_uart1_sleep: blsp1-uart1-sleep { 724 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 725 drive-strength = <2>; 726 bias-disable; 727 }; 728 729 blsp1_uart2_default: blsp1-uart2-default { 730 pins = "gpio4", "gpio5"; 731 drive-strength = <2>; 732 bias-disable; 733 }; 734 735 blsp2_uart1_default: blsp2-uart1-active { 736 tx-rts { 737 pins = "gpio16", "gpio19"; 738 function = "blsp_uart5"; 739 drive-strength = <2>; 740 bias-disable; 741 }; 742 743 rx { 744 /* 745 * Avoid garbage data while BT module 746 * is powered off or not driving signal 747 */ 748 pins = "gpio17"; 749 function = "blsp_uart5"; 750 drive-strength = <2>; 751 bias-pull-up; 752 }; 753 754 cts { 755 /* Match the pull of the BT module */ 756 pins = "gpio18"; 757 function = "blsp_uart5"; 758 drive-strength = <2>; 759 bias-pull-down; 760 }; 761 }; 762 763 blsp2_uart1_sleep: blsp2-uart1-sleep { 764 tx { 765 pins = "gpio16"; 766 function = "gpio"; 767 drive-strength = <2>; 768 bias-pull-up; 769 }; 770 771 rx-cts-rts { 772 pins = "gpio17", "gpio18", "gpio19"; 773 function = "gpio"; 774 drive-strength = <2>; 775 bias-no-pull; 776 }; 777 }; 778 779 i2c1_default: i2c1-default { 780 pins = "gpio2", "gpio3"; 781 function = "blsp_i2c1"; 782 drive-strength = <2>; 783 bias-disable; 784 }; 785 786 i2c1_sleep: i2c1-sleep { 787 pins = "gpio2", "gpio3"; 788 function = "blsp_i2c1"; 789 drive-strength = <2>; 790 bias-pull-up; 791 }; 792 793 i2c2_default: i2c2-default { 794 pins = "gpio6", "gpio7"; 795 function = "blsp_i2c2"; 796 drive-strength = <2>; 797 bias-disable; 798 }; 799 800 i2c2_sleep: i2c2-sleep { 801 pins = "gpio6", "gpio7"; 802 function = "blsp_i2c2"; 803 drive-strength = <2>; 804 bias-pull-up; 805 }; 806 807 i2c3_default: i2c3-default { 808 pins = "gpio10", "gpio11"; 809 function = "blsp_i2c3"; 810 drive-strength = <2>; 811 bias-disable; 812 }; 813 814 i2c3_sleep: i2c3-sleep { 815 pins = "gpio10", "gpio11"; 816 function = "blsp_i2c3"; 817 drive-strength = <2>; 818 bias-pull-up; 819 }; 820 821 i2c4_default: i2c4-default { 822 pins = "gpio14", "gpio15"; 823 function = "blsp_i2c4"; 824 drive-strength = <2>; 825 bias-disable; 826 }; 827 828 i2c4_sleep: i2c4-sleep { 829 pins = "gpio14", "gpio15"; 830 function = "blsp_i2c4"; 831 drive-strength = <2>; 832 bias-pull-up; 833 }; 834 835 i2c5_default: i2c5-default { 836 pins = "gpio18", "gpio19"; 837 function = "blsp_i2c5"; 838 drive-strength = <2>; 839 bias-disable; 840 }; 841 842 i2c5_sleep: i2c5-sleep { 843 pins = "gpio18", "gpio19"; 844 function = "blsp_i2c5"; 845 drive-strength = <2>; 846 bias-pull-up; 847 }; 848 849 i2c6_default: i2c6-default { 850 pins = "gpio22", "gpio23"; 851 function = "blsp_i2c6"; 852 drive-strength = <2>; 853 bias-disable; 854 }; 855 856 i2c6_sleep: i2c6-sleep { 857 pins = "gpio22", "gpio23"; 858 function = "blsp_i2c6"; 859 drive-strength = <2>; 860 bias-pull-up; 861 }; 862 863 i2c7_default: i2c7-default { 864 pins = "gpio26", "gpio27"; 865 function = "blsp_i2c7"; 866 drive-strength = <2>; 867 bias-disable; 868 }; 869 870 i2c7_sleep: i2c7-sleep { 871 pins = "gpio26", "gpio27"; 872 function = "blsp_i2c7"; 873 drive-strength = <2>; 874 bias-pull-up; 875 }; 876 877 i2c8_default: i2c8-default { 878 pins = "gpio30", "gpio31"; 879 function = "blsp_i2c8"; 880 drive-strength = <2>; 881 bias-disable; 882 }; 883 884 i2c8_sleep: i2c8-sleep { 885 pins = "gpio30", "gpio31"; 886 function = "blsp_i2c8"; 887 drive-strength = <2>; 888 bias-pull-up; 889 }; 890 891 cci0_default: cci0_default { 892 pinmux { 893 pins = "gpio36","gpio37"; 894 function = "cci_i2c"; 895 }; 896 897 pinconf { 898 pins = "gpio36","gpio37"; 899 bias-pull-up; 900 drive-strength = <2>; 901 }; 902 }; 903 904 cci1_default: cci1_default { 905 pinmux { 906 pins = "gpio38","gpio39"; 907 function = "cci_i2c"; 908 }; 909 910 pinconf { 911 pins = "gpio38","gpio39"; 912 bias-pull-up; 913 drive-strength = <2>; 914 }; 915 }; 916 917 sdc1_state_on: sdc1-on { 918 clk { 919 pins = "sdc1_clk"; 920 bias-disable; 921 drive-strength = <16>; 922 }; 923 924 cmd { 925 pins = "sdc1_cmd"; 926 bias-pull-up; 927 drive-strength = <10>; 928 }; 929 930 data { 931 pins = "sdc1_data"; 932 bias-pull-up; 933 drive-strength = <10>; 934 }; 935 936 rclk { 937 pins = "sdc1_rclk"; 938 bias-pull-down; 939 }; 940 }; 941 942 sdc1_state_off: sdc1-off { 943 clk { 944 pins = "sdc1_clk"; 945 bias-disable; 946 drive-strength = <2>; 947 }; 948 949 cmd { 950 pins = "sdc1_cmd"; 951 bias-pull-up; 952 drive-strength = <2>; 953 }; 954 955 data { 956 pins = "sdc1_data"; 957 bias-pull-up; 958 drive-strength = <2>; 959 }; 960 961 rclk { 962 pins = "sdc1_rclk"; 963 bias-pull-down; 964 }; 965 }; 966 967 sdc2_state_on: sdc2-on { 968 clk { 969 pins = "sdc2_clk"; 970 bias-disable; 971 drive-strength = <16>; 972 }; 973 974 cmd { 975 pins = "sdc2_cmd"; 976 bias-pull-up; 977 drive-strength = <10>; 978 }; 979 980 data { 981 pins = "sdc2_data"; 982 bias-pull-up; 983 drive-strength = <10>; 984 }; 985 986 sd-cd { 987 pins = "gpio54"; 988 bias-pull-up; 989 drive-strength = <2>; 990 }; 991 }; 992 993 sdc2_state_off: sdc2-off { 994 clk { 995 pins = "sdc2_clk"; 996 bias-disable; 997 drive-strength = <2>; 998 }; 999 1000 cmd { 1001 pins = "sdc2_cmd"; 1002 bias-pull-up; 1003 drive-strength = <2>; 1004 }; 1005 1006 data { 1007 pins = "sdc2_data"; 1008 bias-pull-up; 1009 drive-strength = <2>; 1010 }; 1011 1012 sd-cd { 1013 pins = "gpio54"; 1014 bias-disable; 1015 drive-strength = <2>; 1016 }; 1017 }; 1018 }; 1019 1020 adreno_gpu: gpu@5000000 { 1021 compatible = "qcom,adreno-508.0", "qcom,adreno"; 1022 1023 reg = <0x05000000 0x40000>; 1024 reg-names = "kgsl_3d0_reg_memory"; 1025 1026 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 1027 1028 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1029 <&gpucc GPUCC_RBBMTIMER_CLK>, 1030 <&gcc GCC_BIMC_GFX_CLK>, 1031 <&gcc GCC_GPU_BIMC_GFX_CLK>, 1032 <&gpucc GPUCC_RBCPR_CLK>, 1033 <&gpucc GPUCC_GFX3D_CLK>; 1034 1035 clock-names = "iface", 1036 "rbbmtimer", 1037 "mem", 1038 "mem_iface", 1039 "rbcpr", 1040 "core"; 1041 1042 power-domains = <&rpmpd SDM660_VDDMX>; 1043 iommus = <&kgsl_smmu 0>; 1044 1045 nvmem-cells = <&gpu_speed_bin>; 1046 nvmem-cell-names = "speed_bin"; 1047 1048 interconnects = <&gnoc 1 &bimc 5>; 1049 interconnect-names = "gfx-mem"; 1050 1051 operating-points-v2 = <&gpu_sdm630_opp_table>; 1052 1053 gpu_sdm630_opp_table: opp-table { 1054 compatible = "operating-points-v2"; 1055 opp-775000000 { 1056 opp-hz = /bits/ 64 <775000000>; 1057 opp-level = <RPM_SMD_LEVEL_TURBO>; 1058 opp-peak-kBps = <5412000>; 1059 opp-supported-hw = <0xA2>; 1060 }; 1061 opp-647000000 { 1062 opp-hz = /bits/ 64 <647000000>; 1063 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 1064 opp-peak-kBps = <4068000>; 1065 opp-supported-hw = <0xFF>; 1066 }; 1067 opp-588000000 { 1068 opp-hz = /bits/ 64 <588000000>; 1069 opp-level = <RPM_SMD_LEVEL_NOM>; 1070 opp-peak-kBps = <3072000>; 1071 opp-supported-hw = <0xFF>; 1072 }; 1073 opp-465000000 { 1074 opp-hz = /bits/ 64 <465000000>; 1075 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 1076 opp-peak-kBps = <2724000>; 1077 opp-supported-hw = <0xFF>; 1078 }; 1079 opp-370000000 { 1080 opp-hz = /bits/ 64 <370000000>; 1081 opp-level = <RPM_SMD_LEVEL_SVS>; 1082 opp-peak-kBps = <2188000>; 1083 opp-supported-hw = <0xFF>; 1084 }; 1085 opp-240000000 { 1086 opp-hz = /bits/ 64 <240000000>; 1087 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 1088 opp-peak-kBps = <1648000>; 1089 opp-supported-hw = <0xFF>; 1090 }; 1091 opp-160000000 { 1092 opp-hz = /bits/ 64 <160000000>; 1093 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 1094 opp-peak-kBps = <1200000>; 1095 opp-supported-hw = <0xFF>; 1096 }; 1097 }; 1098 }; 1099 1100 kgsl_smmu: iommu@5040000 { 1101 compatible = "qcom,sdm630-smmu-v2", 1102 "qcom,adreno-smmu", "qcom,smmu-v2"; 1103 reg = <0x05040000 0x10000>; 1104 1105 /* 1106 * GX GDSC parent is CX. We need to bring up CX for SMMU 1107 * but we need both up for Adreno. On the other hand, we 1108 * need to manage the GX rpmpd domain in the adreno driver. 1109 * Enable CX/GX GDSCs here so that we can manage just the GX 1110 * RPM Power Domain in the Adreno driver. 1111 */ 1112 power-domains = <&gpucc GPU_GX_GDSC>; 1113 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1114 <&gcc GCC_BIMC_GFX_CLK>, 1115 <&gcc GCC_GPU_BIMC_GFX_CLK>; 1116 clock-names = "iface", "mem", "mem_iface"; 1117 #global-interrupts = <2>; 1118 #iommu-cells = <1>; 1119 1120 interrupts = 1121 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1123 1124 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>; 1132 1133 status = "disabled"; 1134 }; 1135 1136 gpucc: clock-controller@5065000 { 1137 compatible = "qcom,gpucc-sdm630"; 1138 #clock-cells = <1>; 1139 #reset-cells = <1>; 1140 #power-domain-cells = <1>; 1141 reg = <0x05065000 0x9038>; 1142 1143 clocks = <&xo_board>, 1144 <&gcc GCC_GPU_GPLL0_CLK>, 1145 <&gcc GCC_GPU_GPLL0_DIV_CLK>; 1146 clock-names = "xo", 1147 "gcc_gpu_gpll0_clk", 1148 "gcc_gpu_gpll0_div_clk"; 1149 status = "disabled"; 1150 }; 1151 1152 lpass_smmu: iommu@5100000 { 1153 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 1154 reg = <0x05100000 0x40000>; 1155 #iommu-cells = <1>; 1156 1157 #global-interrupts = <2>; 1158 interrupts = 1159 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1161 1162 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1175 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 1179 1180 status = "disabled"; 1181 }; 1182 1183 sram@290000 { 1184 compatible = "qcom,rpm-stats"; 1185 reg = <0x00290000 0x10000>; 1186 }; 1187 1188 spmi_bus: spmi@800f000 { 1189 compatible = "qcom,spmi-pmic-arb"; 1190 reg = <0x0800f000 0x1000>, 1191 <0x08400000 0x1000000>, 1192 <0x09400000 0x1000000>, 1193 <0x0a400000 0x220000>, 1194 <0x0800a000 0x3000>; 1195 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1196 interrupt-names = "periph_irq"; 1197 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1198 qcom,ee = <0>; 1199 qcom,channel = <0>; 1200 #address-cells = <2>; 1201 #size-cells = <0>; 1202 interrupt-controller; 1203 #interrupt-cells = <4>; 1204 cell-index = <0>; 1205 }; 1206 1207 usb3: usb@a8f8800 { 1208 compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; 1209 reg = <0x0a8f8800 0x400>; 1210 status = "disabled"; 1211 #address-cells = <1>; 1212 #size-cells = <1>; 1213 ranges; 1214 1215 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 1216 <&gcc GCC_USB30_MASTER_CLK>, 1217 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 1218 <&gcc GCC_USB30_SLEEP_CLK>, 1219 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1220 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 1221 clock-names = "cfg_noc", 1222 "core", 1223 "iface", 1224 "sleep", 1225 "mock_utmi", 1226 "bus"; 1227 1228 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1229 <&gcc GCC_USB30_MASTER_CLK>, 1230 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 1231 assigned-clock-rates = <19200000>, <120000000>, 1232 <19200000>; 1233 1234 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1236 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1237 1238 power-domains = <&gcc USB_30_GDSC>; 1239 qcom,select-utmi-as-pipe-clk; 1240 1241 resets = <&gcc GCC_USB_30_BCR>; 1242 1243 usb3_dwc3: usb@a800000 { 1244 compatible = "snps,dwc3"; 1245 reg = <0x0a800000 0xc8d0>; 1246 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1247 snps,dis_u2_susphy_quirk; 1248 snps,dis_enblslpm_quirk; 1249 1250 /* 1251 * SDM630 technically supports USB3 but I 1252 * haven't seen any devices making use of it. 1253 */ 1254 maximum-speed = "high-speed"; 1255 phys = <&qusb2phy>; 1256 phy-names = "usb2-phy"; 1257 snps,hird-threshold = /bits/ 8 <0>; 1258 }; 1259 }; 1260 1261 qusb2phy: phy@c012000 { 1262 compatible = "qcom,sdm660-qusb2-phy"; 1263 reg = <0x0c012000 0x180>; 1264 #phy-cells = <0>; 1265 1266 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1267 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 1268 clock-names = "cfg_ahb", "ref"; 1269 1270 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1271 nvmem-cells = <&qusb2_hstx_trim>; 1272 status = "disabled"; 1273 }; 1274 1275 sdhc_2: sdhci@c084000 { 1276 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1277 reg = <0x0c084000 0x1000>; 1278 reg-names = "hc"; 1279 1280 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1281 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1282 interrupt-names = "hc_irq", "pwr_irq"; 1283 1284 bus-width = <4>; 1285 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 1286 <&gcc GCC_SDCC2_AHB_CLK>, 1287 <&xo_board>; 1288 clock-names = "core", "iface", "xo"; 1289 1290 interconnects = <&a2noc 3 &a2noc 10>, 1291 <&gnoc 0 &cnoc 28>; 1292 operating-points-v2 = <&sdhc2_opp_table>; 1293 1294 pinctrl-names = "default", "sleep"; 1295 pinctrl-0 = <&sdc2_state_on>; 1296 pinctrl-1 = <&sdc2_state_off>; 1297 power-domains = <&rpmpd SDM660_VDDCX>; 1298 1299 status = "disabled"; 1300 1301 sdhc2_opp_table: opp-table { 1302 compatible = "operating-points-v2"; 1303 1304 opp-50000000 { 1305 opp-hz = /bits/ 64 <50000000>; 1306 required-opps = <&rpmpd_opp_low_svs>; 1307 opp-peak-kBps = <200000 140000>; 1308 opp-avg-kBps = <130718 133320>; 1309 }; 1310 opp-100000000 { 1311 opp-hz = /bits/ 64 <100000000>; 1312 required-opps = <&rpmpd_opp_svs>; 1313 opp-peak-kBps = <250000 160000>; 1314 opp-avg-kBps = <196078 150000>; 1315 }; 1316 opp-200000000 { 1317 opp-hz = /bits/ 64 <200000000>; 1318 required-opps = <&rpmpd_opp_nom>; 1319 opp-peak-kBps = <4096000 4096000>; 1320 opp-avg-kBps = <1338562 1338562>; 1321 }; 1322 }; 1323 }; 1324 1325 sdhc_1: sdhci@c0c4000 { 1326 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1327 reg = <0x0c0c4000 0x1000>, 1328 <0x0c0c5000 0x1000>, 1329 <0x0c0c8000 0x8000>; 1330 reg-names = "hc", "cqhci", "ice"; 1331 1332 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1333 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1334 interrupt-names = "hc_irq", "pwr_irq"; 1335 1336 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 1337 <&gcc GCC_SDCC1_AHB_CLK>, 1338 <&xo_board>, 1339 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 1340 clock-names = "core", "iface", "xo", "ice"; 1341 1342 interconnects = <&a2noc 2 &a2noc 10>, 1343 <&gnoc 0 &cnoc 27>; 1344 interconnect-names = "sdhc1-ddr", "cpu-sdhc1"; 1345 operating-points-v2 = <&sdhc1_opp_table>; 1346 pinctrl-names = "default", "sleep"; 1347 pinctrl-0 = <&sdc1_state_on>; 1348 pinctrl-1 = <&sdc1_state_off>; 1349 power-domains = <&rpmpd SDM660_VDDCX>; 1350 1351 bus-width = <8>; 1352 non-removable; 1353 1354 status = "disabled"; 1355 1356 sdhc1_opp_table: opp-table { 1357 compatible = "operating-points-v2"; 1358 1359 opp-50000000 { 1360 opp-hz = /bits/ 64 <50000000>; 1361 required-opps = <&rpmpd_opp_low_svs>; 1362 opp-peak-kBps = <200000 140000>; 1363 opp-avg-kBps = <130718 133320>; 1364 }; 1365 opp-100000000 { 1366 opp-hz = /bits/ 64 <100000000>; 1367 required-opps = <&rpmpd_opp_svs>; 1368 opp-peak-kBps = <250000 160000>; 1369 opp-avg-kBps = <196078 150000>; 1370 }; 1371 opp-384000000 { 1372 opp-hz = /bits/ 64 <384000000>; 1373 required-opps = <&rpmpd_opp_nom>; 1374 opp-peak-kBps = <4096000 4096000>; 1375 opp-avg-kBps = <1338562 1338562>; 1376 }; 1377 }; 1378 }; 1379 1380 mmcc: clock-controller@c8c0000 { 1381 compatible = "qcom,mmcc-sdm630"; 1382 reg = <0x0c8c0000 0x40000>; 1383 #clock-cells = <1>; 1384 #reset-cells = <1>; 1385 #power-domain-cells = <1>; 1386 clock-names = "xo", 1387 "sleep_clk", 1388 "gpll0", 1389 "gpll0_div", 1390 "dsi0pll", 1391 "dsi0pllbyte", 1392 "dsi1pll", 1393 "dsi1pllbyte", 1394 "dp_link_2x_clk_divsel_five", 1395 "dp_vco_divided_clk_src_mux"; 1396 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1397 <&sleep_clk>, 1398 <&gcc GCC_MMSS_GPLL0_CLK>, 1399 <&gcc GCC_MMSS_GPLL0_DIV_CLK>, 1400 <&dsi0_phy 1>, 1401 <&dsi0_phy 0>, 1402 <0>, 1403 <0>, 1404 <0>, 1405 <0>; 1406 }; 1407 1408 dsi_opp_table: dsi-opp-table { 1409 compatible = "operating-points-v2"; 1410 1411 opp-131250000 { 1412 opp-hz = /bits/ 64 <131250000>; 1413 required-opps = <&rpmpd_opp_svs>; 1414 }; 1415 1416 opp-210000000 { 1417 opp-hz = /bits/ 64 <210000000>; 1418 required-opps = <&rpmpd_opp_svs_plus>; 1419 }; 1420 1421 opp-262500000 { 1422 opp-hz = /bits/ 64 <262500000>; 1423 required-opps = <&rpmpd_opp_nom>; 1424 }; 1425 }; 1426 1427 mdss: mdss@c900000 { 1428 compatible = "qcom,mdss"; 1429 reg = <0x0c900000 0x1000>, 1430 <0x0c9b0000 0x1040>; 1431 reg-names = "mdss_phys", "vbif_phys"; 1432 1433 power-domains = <&mmcc MDSS_GDSC>; 1434 1435 clocks = <&mmcc MDSS_AHB_CLK>, 1436 <&mmcc MDSS_AXI_CLK>, 1437 <&mmcc MDSS_VSYNC_CLK>, 1438 <&mmcc MDSS_MDP_CLK>; 1439 clock-names = "iface", 1440 "bus", 1441 "vsync", 1442 "core"; 1443 1444 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1445 1446 interrupt-controller; 1447 #interrupt-cells = <1>; 1448 1449 #address-cells = <1>; 1450 #size-cells = <1>; 1451 ranges; 1452 status = "disabled"; 1453 1454 mdp: mdp@c901000 { 1455 compatible = "qcom,mdp5"; 1456 reg = <0x0c901000 0x89000>; 1457 reg-names = "mdp_phys"; 1458 1459 interrupt-parent = <&mdss>; 1460 interrupts = <0>; 1461 1462 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 1463 <&mmcc MDSS_VSYNC_CLK>; 1464 assigned-clock-rates = <300000000>, 1465 <19200000>; 1466 clocks = <&mmcc MDSS_AHB_CLK>, 1467 <&mmcc MDSS_AXI_CLK>, 1468 <&mmcc MDSS_MDP_CLK>, 1469 <&mmcc MDSS_VSYNC_CLK>; 1470 clock-names = "iface", 1471 "bus", 1472 "core", 1473 "vsync"; 1474 1475 interconnects = <&mnoc 2 &bimc 5>, 1476 <&mnoc 3 &bimc 5>, 1477 <&gnoc 0 &mnoc 17>; 1478 interconnect-names = "mdp0-mem", 1479 "mdp1-mem", 1480 "rotator-mem"; 1481 iommus = <&mmss_smmu 0>; 1482 operating-points-v2 = <&mdp_opp_table>; 1483 power-domains = <&rpmpd SDM660_VDDCX>; 1484 1485 ports { 1486 #address-cells = <1>; 1487 #size-cells = <0>; 1488 1489 port@0 { 1490 reg = <0>; 1491 mdp5_intf1_out: endpoint { 1492 remote-endpoint = <&dsi0_in>; 1493 }; 1494 }; 1495 }; 1496 1497 mdp_opp_table: mdp-opp { 1498 compatible = "operating-points-v2"; 1499 1500 opp-150000000 { 1501 opp-hz = /bits/ 64 <150000000>; 1502 opp-peak-kBps = <320000 320000 76800>; 1503 required-opps = <&rpmpd_opp_low_svs>; 1504 }; 1505 opp-275000000 { 1506 opp-hz = /bits/ 64 <275000000>; 1507 opp-peak-kBps = <6400000 6400000 160000>; 1508 required-opps = <&rpmpd_opp_svs>; 1509 }; 1510 opp-300000000 { 1511 opp-hz = /bits/ 64 <300000000>; 1512 opp-peak-kBps = <6400000 6400000 190000>; 1513 required-opps = <&rpmpd_opp_svs_plus>; 1514 }; 1515 opp-330000000 { 1516 opp-hz = /bits/ 64 <330000000>; 1517 opp-peak-kBps = <6400000 6400000 240000>; 1518 required-opps = <&rpmpd_opp_nom>; 1519 }; 1520 opp-412500000 { 1521 opp-hz = /bits/ 64 <412500000>; 1522 opp-peak-kBps = <6400000 6400000 320000>; 1523 required-opps = <&rpmpd_opp_turbo>; 1524 }; 1525 }; 1526 }; 1527 1528 dsi0: dsi@c994000 { 1529 compatible = "qcom,mdss-dsi-ctrl"; 1530 reg = <0x0c994000 0x400>; 1531 reg-names = "dsi_ctrl"; 1532 1533 operating-points-v2 = <&dsi_opp_table>; 1534 power-domains = <&rpmpd SDM660_VDDCX>; 1535 1536 interrupt-parent = <&mdss>; 1537 interrupts = <4>; 1538 1539 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 1540 <&mmcc PCLK0_CLK_SRC>; 1541 assigned-clock-parents = <&dsi0_phy 0>, 1542 <&dsi0_phy 1>; 1543 1544 clocks = <&mmcc MDSS_MDP_CLK>, 1545 <&mmcc MDSS_BYTE0_CLK>, 1546 <&mmcc MDSS_BYTE0_INTF_CLK>, 1547 <&mmcc MNOC_AHB_CLK>, 1548 <&mmcc MDSS_AHB_CLK>, 1549 <&mmcc MDSS_AXI_CLK>, 1550 <&mmcc MISC_AHB_CLK>, 1551 <&mmcc MDSS_PCLK0_CLK>, 1552 <&mmcc MDSS_ESC0_CLK>; 1553 clock-names = "mdp_core", 1554 "byte", 1555 "byte_intf", 1556 "mnoc", 1557 "iface", 1558 "bus", 1559 "core_mmss", 1560 "pixel", 1561 "core"; 1562 1563 phys = <&dsi0_phy>; 1564 phy-names = "dsi"; 1565 1566 ports { 1567 #address-cells = <1>; 1568 #size-cells = <0>; 1569 1570 port@0 { 1571 reg = <0>; 1572 dsi0_in: endpoint { 1573 remote-endpoint = <&mdp5_intf1_out>; 1574 }; 1575 }; 1576 1577 port@1 { 1578 reg = <1>; 1579 dsi0_out: endpoint { 1580 }; 1581 }; 1582 }; 1583 }; 1584 1585 dsi0_phy: dsi-phy@c994400 { 1586 compatible = "qcom,dsi-phy-14nm-660"; 1587 reg = <0x0c994400 0x100>, 1588 <0x0c994500 0x300>, 1589 <0x0c994800 0x188>; 1590 reg-names = "dsi_phy", 1591 "dsi_phy_lane", 1592 "dsi_pll"; 1593 1594 #clock-cells = <1>; 1595 #phy-cells = <0>; 1596 1597 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 1598 clock-names = "iface", "ref"; 1599 }; 1600 }; 1601 1602 blsp1_dma: dma-controller@c144000 { 1603 compatible = "qcom,bam-v1.7.0"; 1604 reg = <0x0c144000 0x1f000>; 1605 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1606 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1607 clock-names = "bam_clk"; 1608 #dma-cells = <1>; 1609 qcom,ee = <0>; 1610 qcom,controlled-remotely; 1611 num-channels = <18>; 1612 qcom,num-ees = <4>; 1613 }; 1614 1615 blsp1_uart1: serial@c16f000 { 1616 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1617 reg = <0x0c16f000 0x200>; 1618 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1619 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 1620 <&gcc GCC_BLSP1_AHB_CLK>; 1621 clock-names = "core", "iface"; 1622 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 1623 dma-names = "tx", "rx"; 1624 pinctrl-names = "default", "sleep"; 1625 pinctrl-0 = <&blsp1_uart1_default>; 1626 pinctrl-1 = <&blsp1_uart1_sleep>; 1627 status = "disabled"; 1628 }; 1629 1630 blsp1_uart2: serial@c170000 { 1631 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1632 reg = <0x0c170000 0x1000>; 1633 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1634 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 1635 <&gcc GCC_BLSP1_AHB_CLK>; 1636 clock-names = "core", "iface"; 1637 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 1638 dma-names = "tx", "rx"; 1639 pinctrl-names = "default"; 1640 pinctrl-0 = <&blsp1_uart2_default>; 1641 status = "disabled"; 1642 }; 1643 1644 blsp_i2c1: i2c@c175000 { 1645 compatible = "qcom,i2c-qup-v2.2.1"; 1646 reg = <0x0c175000 0x600>; 1647 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1648 1649 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1650 <&gcc GCC_BLSP1_AHB_CLK>; 1651 clock-names = "core", "iface"; 1652 clock-frequency = <400000>; 1653 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1654 dma-names = "tx", "rx"; 1655 1656 pinctrl-names = "default", "sleep"; 1657 pinctrl-0 = <&i2c1_default>; 1658 pinctrl-1 = <&i2c1_sleep>; 1659 #address-cells = <1>; 1660 #size-cells = <0>; 1661 status = "disabled"; 1662 }; 1663 1664 blsp_i2c2: i2c@c176000 { 1665 compatible = "qcom,i2c-qup-v2.2.1"; 1666 reg = <0x0c176000 0x600>; 1667 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1668 1669 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1670 <&gcc GCC_BLSP1_AHB_CLK>; 1671 clock-names = "core", "iface"; 1672 clock-frequency = <400000>; 1673 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 1674 dma-names = "tx", "rx"; 1675 1676 pinctrl-names = "default", "sleep"; 1677 pinctrl-0 = <&i2c2_default>; 1678 pinctrl-1 = <&i2c2_sleep>; 1679 #address-cells = <1>; 1680 #size-cells = <0>; 1681 status = "disabled"; 1682 }; 1683 1684 blsp_i2c3: i2c@c177000 { 1685 compatible = "qcom,i2c-qup-v2.2.1"; 1686 reg = <0x0c177000 0x600>; 1687 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1688 1689 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1690 <&gcc GCC_BLSP1_AHB_CLK>; 1691 clock-names = "core", "iface"; 1692 clock-frequency = <400000>; 1693 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 1694 dma-names = "tx", "rx"; 1695 1696 pinctrl-names = "default", "sleep"; 1697 pinctrl-0 = <&i2c3_default>; 1698 pinctrl-1 = <&i2c3_sleep>; 1699 #address-cells = <1>; 1700 #size-cells = <0>; 1701 status = "disabled"; 1702 }; 1703 1704 blsp_i2c4: i2c@c178000 { 1705 compatible = "qcom,i2c-qup-v2.2.1"; 1706 reg = <0x0c178000 0x600>; 1707 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1708 1709 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1710 <&gcc GCC_BLSP1_AHB_CLK>; 1711 clock-names = "core", "iface"; 1712 clock-frequency = <400000>; 1713 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 1714 dma-names = "tx", "rx"; 1715 1716 pinctrl-names = "default", "sleep"; 1717 pinctrl-0 = <&i2c4_default>; 1718 pinctrl-1 = <&i2c4_sleep>; 1719 #address-cells = <1>; 1720 #size-cells = <0>; 1721 status = "disabled"; 1722 }; 1723 1724 blsp2_dma: dma-controller@c184000 { 1725 compatible = "qcom,bam-v1.7.0"; 1726 reg = <0x0c184000 0x1f000>; 1727 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1728 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1729 clock-names = "bam_clk"; 1730 #dma-cells = <1>; 1731 qcom,ee = <0>; 1732 qcom,controlled-remotely; 1733 num-channels = <18>; 1734 qcom,num-ees = <4>; 1735 }; 1736 1737 blsp2_uart1: serial@c1af000 { 1738 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1739 reg = <0x0c1af000 0x200>; 1740 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1741 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, 1742 <&gcc GCC_BLSP2_AHB_CLK>; 1743 clock-names = "core", "iface"; 1744 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1745 dma-names = "tx", "rx"; 1746 pinctrl-names = "default", "sleep"; 1747 pinctrl-0 = <&blsp2_uart1_default>; 1748 pinctrl-1 = <&blsp2_uart1_sleep>; 1749 status = "disabled"; 1750 }; 1751 1752 blsp_i2c5: i2c@c1b5000 { 1753 compatible = "qcom,i2c-qup-v2.2.1"; 1754 reg = <0x0c1b5000 0x600>; 1755 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1756 1757 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1758 <&gcc GCC_BLSP2_AHB_CLK>; 1759 clock-names = "core", "iface"; 1760 clock-frequency = <400000>; 1761 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; 1762 dma-names = "tx", "rx"; 1763 1764 pinctrl-names = "default", "sleep"; 1765 pinctrl-0 = <&i2c5_default>; 1766 pinctrl-1 = <&i2c5_sleep>; 1767 #address-cells = <1>; 1768 #size-cells = <0>; 1769 status = "disabled"; 1770 }; 1771 1772 blsp_i2c6: i2c@c1b6000 { 1773 compatible = "qcom,i2c-qup-v2.2.1"; 1774 reg = <0x0c1b6000 0x600>; 1775 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1776 1777 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1778 <&gcc GCC_BLSP2_AHB_CLK>; 1779 clock-names = "core", "iface"; 1780 clock-frequency = <400000>; 1781 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1782 dma-names = "tx", "rx"; 1783 1784 pinctrl-names = "default", "sleep"; 1785 pinctrl-0 = <&i2c6_default>; 1786 pinctrl-1 = <&i2c6_sleep>; 1787 #address-cells = <1>; 1788 #size-cells = <0>; 1789 status = "disabled"; 1790 }; 1791 1792 blsp_i2c7: i2c@c1b7000 { 1793 compatible = "qcom,i2c-qup-v2.2.1"; 1794 reg = <0x0c1b7000 0x600>; 1795 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1796 1797 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1798 <&gcc GCC_BLSP2_AHB_CLK>; 1799 clock-names = "core", "iface"; 1800 clock-frequency = <400000>; 1801 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 1802 dma-names = "tx", "rx"; 1803 1804 pinctrl-names = "default", "sleep"; 1805 pinctrl-0 = <&i2c7_default>; 1806 pinctrl-1 = <&i2c7_sleep>; 1807 #address-cells = <1>; 1808 #size-cells = <0>; 1809 status = "disabled"; 1810 }; 1811 1812 blsp_i2c8: i2c@c1b8000 { 1813 compatible = "qcom,i2c-qup-v2.2.1"; 1814 reg = <0x0c1b8000 0x600>; 1815 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1816 1817 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1818 <&gcc GCC_BLSP2_AHB_CLK>; 1819 clock-names = "core", "iface"; 1820 clock-frequency = <400000>; 1821 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 1822 dma-names = "tx", "rx"; 1823 1824 pinctrl-names = "default", "sleep"; 1825 pinctrl-0 = <&i2c8_default>; 1826 pinctrl-1 = <&i2c8_sleep>; 1827 #address-cells = <1>; 1828 #size-cells = <0>; 1829 status = "disabled"; 1830 }; 1831 1832 imem@146bf000 { 1833 compatible = "simple-mfd"; 1834 reg = <0x146bf000 0x1000>; 1835 1836 #address-cells = <1>; 1837 #size-cells = <1>; 1838 1839 ranges = <0 0x146bf000 0x1000>; 1840 1841 pil-reloc@94c { 1842 compatible = "qcom,pil-reloc-info"; 1843 reg = <0x94c 0xc8>; 1844 }; 1845 }; 1846 1847 camss: camss@ca00000 { 1848 compatible = "qcom,sdm660-camss"; 1849 reg = <0x0c824000 0x1000>, 1850 <0x0ca00120 0x4>, 1851 <0x0c825000 0x1000>, 1852 <0x0ca00124 0x4>, 1853 <0x0c826000 0x1000>, 1854 <0x0ca00128 0x4>, 1855 <0x0ca30000 0x100>, 1856 <0x0ca30400 0x100>, 1857 <0x0ca30800 0x100>, 1858 <0x0ca30c00 0x100>, 1859 <0x0ca31000 0x500>, 1860 <0x0ca00020 0x10>, 1861 <0x0ca10000 0x1000>, 1862 <0x0ca14000 0x1000>; 1863 reg-names = "csiphy0", 1864 "csiphy0_clk_mux", 1865 "csiphy1", 1866 "csiphy1_clk_mux", 1867 "csiphy2", 1868 "csiphy2_clk_mux", 1869 "csid0", 1870 "csid1", 1871 "csid2", 1872 "csid3", 1873 "ispif", 1874 "csi_clk_mux", 1875 "vfe0", 1876 "vfe1"; 1877 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1878 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1879 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 1880 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 1881 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 1882 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 1883 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 1884 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 1885 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 1886 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 1887 interrupt-names = "csiphy0", 1888 "csiphy1", 1889 "csiphy2", 1890 "csid0", 1891 "csid1", 1892 "csid2", 1893 "csid3", 1894 "ispif", 1895 "vfe0", 1896 "vfe1"; 1897 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 1898 <&mmcc THROTTLE_CAMSS_AXI_CLK>, 1899 <&mmcc CAMSS_ISPIF_AHB_CLK>, 1900 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 1901 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 1902 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 1903 <&mmcc CAMSS_CSI0_AHB_CLK>, 1904 <&mmcc CAMSS_CSI0_CLK>, 1905 <&mmcc CAMSS_CPHY_CSID0_CLK>, 1906 <&mmcc CAMSS_CSI0PIX_CLK>, 1907 <&mmcc CAMSS_CSI0RDI_CLK>, 1908 <&mmcc CAMSS_CSI1_AHB_CLK>, 1909 <&mmcc CAMSS_CSI1_CLK>, 1910 <&mmcc CAMSS_CPHY_CSID1_CLK>, 1911 <&mmcc CAMSS_CSI1PIX_CLK>, 1912 <&mmcc CAMSS_CSI1RDI_CLK>, 1913 <&mmcc CAMSS_CSI2_AHB_CLK>, 1914 <&mmcc CAMSS_CSI2_CLK>, 1915 <&mmcc CAMSS_CPHY_CSID2_CLK>, 1916 <&mmcc CAMSS_CSI2PIX_CLK>, 1917 <&mmcc CAMSS_CSI2RDI_CLK>, 1918 <&mmcc CAMSS_CSI3_AHB_CLK>, 1919 <&mmcc CAMSS_CSI3_CLK>, 1920 <&mmcc CAMSS_CPHY_CSID3_CLK>, 1921 <&mmcc CAMSS_CSI3PIX_CLK>, 1922 <&mmcc CAMSS_CSI3RDI_CLK>, 1923 <&mmcc CAMSS_AHB_CLK>, 1924 <&mmcc CAMSS_VFE0_CLK>, 1925 <&mmcc CAMSS_CSI_VFE0_CLK>, 1926 <&mmcc CAMSS_VFE0_AHB_CLK>, 1927 <&mmcc CAMSS_VFE0_STREAM_CLK>, 1928 <&mmcc CAMSS_VFE1_CLK>, 1929 <&mmcc CAMSS_CSI_VFE1_CLK>, 1930 <&mmcc CAMSS_VFE1_AHB_CLK>, 1931 <&mmcc CAMSS_VFE1_STREAM_CLK>, 1932 <&mmcc CAMSS_VFE_VBIF_AHB_CLK>, 1933 <&mmcc CAMSS_VFE_VBIF_AXI_CLK>, 1934 <&mmcc CSIPHY_AHB2CRIF_CLK>, 1935 <&mmcc CAMSS_CPHY_CSID0_CLK>, 1936 <&mmcc CAMSS_CPHY_CSID1_CLK>, 1937 <&mmcc CAMSS_CPHY_CSID2_CLK>, 1938 <&mmcc CAMSS_CPHY_CSID3_CLK>; 1939 clock-names = "top_ahb", 1940 "throttle_axi", 1941 "ispif_ahb", 1942 "csiphy0_timer", 1943 "csiphy1_timer", 1944 "csiphy2_timer", 1945 "csi0_ahb", 1946 "csi0", 1947 "csi0_phy", 1948 "csi0_pix", 1949 "csi0_rdi", 1950 "csi1_ahb", 1951 "csi1", 1952 "csi1_phy", 1953 "csi1_pix", 1954 "csi1_rdi", 1955 "csi2_ahb", 1956 "csi2", 1957 "csi2_phy", 1958 "csi2_pix", 1959 "csi2_rdi", 1960 "csi3_ahb", 1961 "csi3", 1962 "csi3_phy", 1963 "csi3_pix", 1964 "csi3_rdi", 1965 "ahb", 1966 "vfe0", 1967 "csi_vfe0", 1968 "vfe0_ahb", 1969 "vfe0_stream", 1970 "vfe1", 1971 "csi_vfe1", 1972 "vfe1_ahb", 1973 "vfe1_stream", 1974 "vfe_ahb", 1975 "vfe_axi", 1976 "csiphy_ahb2crif", 1977 "cphy_csid0", 1978 "cphy_csid1", 1979 "cphy_csid2", 1980 "cphy_csid3"; 1981 interconnects = <&mnoc 5 &bimc 5>; 1982 interconnect-names = "vfe-mem"; 1983 iommus = <&mmss_smmu 0xc00>, 1984 <&mmss_smmu 0xc01>, 1985 <&mmss_smmu 0xc02>, 1986 <&mmss_smmu 0xc03>; 1987 power-domains = <&mmcc CAMSS_VFE0_GDSC>, 1988 <&mmcc CAMSS_VFE1_GDSC>; 1989 status = "disabled"; 1990 1991 ports { 1992 #address-cells = <1>; 1993 #size-cells = <0>; 1994 }; 1995 }; 1996 1997 cci: cci@ca0c000 { 1998 compatible = "qcom,msm8996-cci"; 1999 #address-cells = <1>; 2000 #size-cells = <0>; 2001 reg = <0x0ca0c000 0x1000>; 2002 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 2003 2004 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 2005 <&mmcc CAMSS_CCI_CLK>; 2006 assigned-clock-rates = <80800000>, <37500000>; 2007 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2008 <&mmcc CAMSS_CCI_AHB_CLK>, 2009 <&mmcc CAMSS_CCI_CLK>, 2010 <&mmcc CAMSS_AHB_CLK>; 2011 clock-names = "camss_top_ahb", 2012 "cci_ahb", 2013 "cci", 2014 "camss_ahb"; 2015 2016 pinctrl-names = "default"; 2017 pinctrl-0 = <&cci0_default &cci1_default>; 2018 power-domains = <&mmcc CAMSS_TOP_GDSC>; 2019 status = "disabled"; 2020 2021 cci_i2c0: i2c-bus@0 { 2022 reg = <0>; 2023 clock-frequency = <400000>; 2024 #address-cells = <1>; 2025 #size-cells = <0>; 2026 }; 2027 2028 cci_i2c1: i2c-bus@1 { 2029 reg = <1>; 2030 clock-frequency = <400000>; 2031 #address-cells = <1>; 2032 #size-cells = <0>; 2033 }; 2034 }; 2035 2036 venus: video-codec@cc00000 { 2037 compatible = "qcom,sdm660-venus"; 2038 reg = <0x0cc00000 0xff000>; 2039 clocks = <&mmcc VIDEO_CORE_CLK>, 2040 <&mmcc VIDEO_AHB_CLK>, 2041 <&mmcc VIDEO_AXI_CLK>, 2042 <&mmcc THROTTLE_VIDEO_AXI_CLK>; 2043 clock-names = "core", "iface", "bus", "bus_throttle"; 2044 interconnects = <&gnoc 0 &mnoc 13>, 2045 <&mnoc 4 &bimc 5>; 2046 interconnect-names = "cpu-cfg", "video-mem"; 2047 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2048 iommus = <&mmss_smmu 0x400>, 2049 <&mmss_smmu 0x401>, 2050 <&mmss_smmu 0x40a>, 2051 <&mmss_smmu 0x407>, 2052 <&mmss_smmu 0x40e>, 2053 <&mmss_smmu 0x40f>, 2054 <&mmss_smmu 0x408>, 2055 <&mmss_smmu 0x409>, 2056 <&mmss_smmu 0x40b>, 2057 <&mmss_smmu 0x40c>, 2058 <&mmss_smmu 0x40d>, 2059 <&mmss_smmu 0x410>, 2060 <&mmss_smmu 0x421>, 2061 <&mmss_smmu 0x428>, 2062 <&mmss_smmu 0x429>, 2063 <&mmss_smmu 0x42b>, 2064 <&mmss_smmu 0x42c>, 2065 <&mmss_smmu 0x42d>, 2066 <&mmss_smmu 0x411>, 2067 <&mmss_smmu 0x431>; 2068 memory-region = <&venus_region>; 2069 power-domains = <&mmcc VENUS_GDSC>; 2070 status = "disabled"; 2071 2072 video-decoder { 2073 compatible = "venus-decoder"; 2074 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2075 clock-names = "vcodec0_core"; 2076 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2077 }; 2078 2079 video-encoder { 2080 compatible = "venus-encoder"; 2081 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2082 clock-names = "vcodec0_core"; 2083 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2084 }; 2085 }; 2086 2087 mmss_smmu: iommu@cd00000 { 2088 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 2089 reg = <0x0cd00000 0x40000>; 2090 2091 clocks = <&mmcc MNOC_AHB_CLK>, 2092 <&mmcc BIMC_SMMU_AHB_CLK>, 2093 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, 2094 <&mmcc BIMC_SMMU_AXI_CLK>; 2095 clock-names = "iface-mm", "iface-smmu", 2096 "bus-mm", "bus-smmu"; 2097 #global-interrupts = <2>; 2098 #iommu-cells = <1>; 2099 2100 interrupts = 2101 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2102 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2103 2104 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2105 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2106 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2107 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 2109 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 2110 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 2111 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 2112 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 2113 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 2114 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 2115 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 2116 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 2117 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 2118 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 2119 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2120 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2121 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2122 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2123 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 2124 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 2125 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 2126 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 2127 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 2128 2129 status = "disabled"; 2130 }; 2131 2132 adsp_pil: remoteproc@15700000 { 2133 compatible = "qcom,sdm660-adsp-pas"; 2134 reg = <0x15700000 0x4040>; 2135 2136 interrupts-extended = 2137 <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2138 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2139 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2140 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2141 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2142 interrupt-names = "wdog", "fatal", "ready", 2143 "handover", "stop-ack"; 2144 2145 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2146 clock-names = "xo"; 2147 2148 memory-region = <&adsp_region>; 2149 power-domains = <&rpmpd SDM660_VDDCX>; 2150 power-domain-names = "cx"; 2151 2152 qcom,smem-states = <&adsp_smp2p_out 0>; 2153 qcom,smem-state-names = "stop"; 2154 2155 glink-edge { 2156 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 2157 2158 label = "lpass"; 2159 mboxes = <&apcs_glb 9>; 2160 qcom,remote-pid = <2>; 2161 #address-cells = <1>; 2162 #size-cells = <0>; 2163 2164 apr { 2165 compatible = "qcom,apr-v2"; 2166 qcom,glink-channels = "apr_audio_svc"; 2167 qcom,domain = <APR_DOMAIN_ADSP>; 2168 #address-cells = <1>; 2169 #size-cells = <0>; 2170 2171 q6core { 2172 reg = <APR_SVC_ADSP_CORE>; 2173 compatible = "qcom,q6core"; 2174 }; 2175 2176 q6afe: apr-service@4 { 2177 compatible = "qcom,q6afe"; 2178 reg = <APR_SVC_AFE>; 2179 q6afedai: dais { 2180 compatible = "qcom,q6afe-dais"; 2181 #address-cells = <1>; 2182 #size-cells = <0>; 2183 #sound-dai-cells = <1>; 2184 }; 2185 }; 2186 2187 q6asm: apr-service@7 { 2188 compatible = "qcom,q6asm"; 2189 reg = <APR_SVC_ASM>; 2190 q6asmdai: dais { 2191 compatible = "qcom,q6asm-dais"; 2192 #address-cells = <1>; 2193 #size-cells = <0>; 2194 #sound-dai-cells = <1>; 2195 iommus = <&lpass_smmu 1>; 2196 }; 2197 }; 2198 2199 q6adm: apr-service@8 { 2200 compatible = "qcom,q6adm"; 2201 reg = <APR_SVC_ADM>; 2202 q6routing: routing { 2203 compatible = "qcom,q6adm-routing"; 2204 #sound-dai-cells = <0>; 2205 }; 2206 }; 2207 }; 2208 }; 2209 }; 2210 2211 gnoc: interconnect@17900000 { 2212 compatible = "qcom,sdm660-gnoc"; 2213 reg = <0x17900000 0xe000>; 2214 #interconnect-cells = <1>; 2215 /* 2216 * This one apparently features no clocks, 2217 * so let's not mess with the driver needlessly 2218 */ 2219 clock-names = "bus", "bus_a"; 2220 clocks = <&xo_board>, <&xo_board>; 2221 }; 2222 2223 apcs_glb: mailbox@17911000 { 2224 compatible = "qcom,sdm660-apcs-hmss-global"; 2225 reg = <0x17911000 0x1000>; 2226 2227 #mbox-cells = <1>; 2228 }; 2229 2230 timer@17920000 { 2231 #address-cells = <1>; 2232 #size-cells = <1>; 2233 ranges; 2234 compatible = "arm,armv7-timer-mem"; 2235 reg = <0x17920000 0x1000>; 2236 clock-frequency = <19200000>; 2237 2238 frame@17921000 { 2239 frame-number = <0>; 2240 interrupts = <0 8 0x4>, 2241 <0 7 0x4>; 2242 reg = <0x17921000 0x1000>, 2243 <0x17922000 0x1000>; 2244 }; 2245 2246 frame@17923000 { 2247 frame-number = <1>; 2248 interrupts = <0 9 0x4>; 2249 reg = <0x17923000 0x1000>; 2250 status = "disabled"; 2251 }; 2252 2253 frame@17924000 { 2254 frame-number = <2>; 2255 interrupts = <0 10 0x4>; 2256 reg = <0x17924000 0x1000>; 2257 status = "disabled"; 2258 }; 2259 2260 frame@17925000 { 2261 frame-number = <3>; 2262 interrupts = <0 11 0x4>; 2263 reg = <0x17925000 0x1000>; 2264 status = "disabled"; 2265 }; 2266 2267 frame@17926000 { 2268 frame-number = <4>; 2269 interrupts = <0 12 0x4>; 2270 reg = <0x17926000 0x1000>; 2271 status = "disabled"; 2272 }; 2273 2274 frame@17927000 { 2275 frame-number = <5>; 2276 interrupts = <0 13 0x4>; 2277 reg = <0x17927000 0x1000>; 2278 status = "disabled"; 2279 }; 2280 2281 frame@17928000 { 2282 frame-number = <6>; 2283 interrupts = <0 14 0x4>; 2284 reg = <0x17928000 0x1000>; 2285 status = "disabled"; 2286 }; 2287 }; 2288 2289 intc: interrupt-controller@17a00000 { 2290 compatible = "arm,gic-v3"; 2291 reg = <0x17a00000 0x10000>, /* GICD */ 2292 <0x17b00000 0x100000>; /* GICR * 8 */ 2293 #interrupt-cells = <3>; 2294 #address-cells = <1>; 2295 #size-cells = <1>; 2296 ranges; 2297 interrupt-controller; 2298 #redistributor-regions = <1>; 2299 redistributor-stride = <0x0 0x20000>; 2300 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2301 }; 2302 }; 2303 2304 tcsr_mutex: hwlock { 2305 compatible = "qcom,tcsr-mutex"; 2306 syscon = <&tcsr_mutex_regs 0 0x1000>; 2307 #hwlock-cells = <1>; 2308 }; 2309 2310 sound: sound { 2311 }; 2312 2313 thermal-zones { 2314 aoss-thermal { 2315 polling-delay-passive = <250>; 2316 polling-delay = <1000>; 2317 2318 thermal-sensors = <&tsens 0>; 2319 2320 trips { 2321 aoss_alert0: trip-point0 { 2322 temperature = <105000>; 2323 hysteresis = <1000>; 2324 type = "hot"; 2325 }; 2326 }; 2327 }; 2328 2329 cpuss0-thermal { 2330 polling-delay-passive = <250>; 2331 polling-delay = <1000>; 2332 2333 thermal-sensors = <&tsens 1>; 2334 2335 trips { 2336 cpuss0_alert0: trip-point0 { 2337 temperature = <125000>; 2338 hysteresis = <1000>; 2339 type = "hot"; 2340 }; 2341 }; 2342 }; 2343 2344 cpuss1-thermal { 2345 polling-delay-passive = <250>; 2346 polling-delay = <1000>; 2347 2348 thermal-sensors = <&tsens 2>; 2349 2350 trips { 2351 cpuss1_alert0: trip-point0 { 2352 temperature = <125000>; 2353 hysteresis = <1000>; 2354 type = "hot"; 2355 }; 2356 }; 2357 }; 2358 2359 cpu0-thermal { 2360 polling-delay-passive = <250>; 2361 polling-delay = <1000>; 2362 2363 thermal-sensors = <&tsens 3>; 2364 2365 trips { 2366 cpu0_alert0: trip-point0 { 2367 temperature = <70000>; 2368 hysteresis = <1000>; 2369 type = "passive"; 2370 }; 2371 2372 cpu0_crit: cpu_crit { 2373 temperature = <110000>; 2374 hysteresis = <1000>; 2375 type = "critical"; 2376 }; 2377 }; 2378 }; 2379 2380 cpu1-thermal { 2381 polling-delay-passive = <250>; 2382 polling-delay = <1000>; 2383 2384 thermal-sensors = <&tsens 4>; 2385 2386 trips { 2387 cpu1_alert0: trip-point0 { 2388 temperature = <70000>; 2389 hysteresis = <1000>; 2390 type = "passive"; 2391 }; 2392 2393 cpu1_crit: cpu_crit { 2394 temperature = <110000>; 2395 hysteresis = <1000>; 2396 type = "critical"; 2397 }; 2398 }; 2399 }; 2400 2401 cpu2-thermal { 2402 polling-delay-passive = <250>; 2403 polling-delay = <1000>; 2404 2405 thermal-sensors = <&tsens 5>; 2406 2407 trips { 2408 cpu2_alert0: trip-point0 { 2409 temperature = <70000>; 2410 hysteresis = <1000>; 2411 type = "passive"; 2412 }; 2413 2414 cpu2_crit: cpu_crit { 2415 temperature = <110000>; 2416 hysteresis = <1000>; 2417 type = "critical"; 2418 }; 2419 }; 2420 }; 2421 2422 cpu3-thermal { 2423 polling-delay-passive = <250>; 2424 polling-delay = <1000>; 2425 2426 thermal-sensors = <&tsens 6>; 2427 2428 trips { 2429 cpu3_alert0: trip-point0 { 2430 temperature = <70000>; 2431 hysteresis = <1000>; 2432 type = "passive"; 2433 }; 2434 2435 cpu3_crit: cpu_crit { 2436 temperature = <110000>; 2437 hysteresis = <1000>; 2438 type = "critical"; 2439 }; 2440 }; 2441 }; 2442 2443 /* 2444 * According to what downstream DTS says, 2445 * the entire power efficient cluster has 2446 * only a single thermal sensor. 2447 */ 2448 2449 pwr-cluster-thermal { 2450 polling-delay-passive = <250>; 2451 polling-delay = <1000>; 2452 2453 thermal-sensors = <&tsens 7>; 2454 2455 trips { 2456 pwr_cluster_alert0: trip-point0 { 2457 temperature = <70000>; 2458 hysteresis = <1000>; 2459 type = "passive"; 2460 }; 2461 2462 pwr_cluster_crit: cpu_crit { 2463 temperature = <110000>; 2464 hysteresis = <1000>; 2465 type = "critical"; 2466 }; 2467 }; 2468 }; 2469 2470 gpu-thermal { 2471 polling-delay-passive = <250>; 2472 polling-delay = <1000>; 2473 2474 thermal-sensors = <&tsens 8>; 2475 2476 trips { 2477 gpu_alert0: trip-point0 { 2478 temperature = <90000>; 2479 hysteresis = <1000>; 2480 type = "hot"; 2481 }; 2482 }; 2483 }; 2484 }; 2485 2486 timer { 2487 compatible = "arm,armv8-timer"; 2488 interrupts = <GIC_PPI 1 0xf08>, 2489 <GIC_PPI 2 0xf08>, 2490 <GIC_PPI 3 0xf08>, 2491 <GIC_PPI 0 0xf08>; 2492 }; 2493}; 2494