cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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sdm845-cheza-r2.dts (4785B)


      1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      2/*
      3 * Google Cheza board device tree source
      4 *
      5 * Copyright 2018 Google LLC.
      6 */
      7
      8/dts-v1/;
      9
     10#include "sdm845-cheza.dtsi"
     11
     12/ {
     13	model = "Google Cheza (rev2)";
     14	compatible = "google,cheza-rev2", "qcom,sdm845";
     15
     16	/*
     17	 * FIXED REGULATORS (not in sdm845-cheza.dtsi) - parents above children
     18	 */
     19
     20	/*
     21	 * NOTE: Technically pp3500_a is not the exact same signal as
     22	 * pp3500_a_vbob (there's a load switch between them and the EC can
     23	 * control pp3500_a via "en_pp3300_a"), but from the AP's point of
     24	 * view they are the same.
     25	 */
     26	pp3500_a:
     27	pp3500_a_vbob: pp3500-a-vbob-regulator {
     28		compatible = "regulator-fixed";
     29		regulator-name = "vreg_bob";
     30
     31		/*
     32		 * Comes on automatically when pp5000_ldo comes on, which
     33		 * comes on automatically when ppvar_sys comes on
     34		 */
     35		regulator-always-on;
     36		regulator-boot-on;
     37		regulator-min-microvolt = <3500000>;
     38		regulator-max-microvolt = <3500000>;
     39
     40		vin-supply = <&ppvar_sys>;
     41	};
     42
     43	pp3300_dx_edp: pp3300-dx-edp-regulator {
     44		/* Yes, it's really 3.5 despite the name of the signal */
     45		regulator-min-microvolt = <3500000>;
     46		regulator-max-microvolt = <3500000>;
     47
     48		vin-supply = <&pp3500_a>;
     49	};
     50};
     51
     52/* FIXED REGULATOR OVERRIDES (modifications to sdm845-cheza.dtsi) */
     53
     54/*
     55 * L19 and L28 technically go to 3.3V, but most boards have old AOP firmware
     56 * that limits them to 3.0, and trying to run at 3.3V with that old firmware
     57 * prevents the system from booting.
     58 */
     59&src_pp3000_l19a {
     60	regulator-min-microvolt = <3008000>;
     61	regulator-max-microvolt = <3008000>;
     62};
     63
     64&src_pp3300_l22a {
     65	/delete-property/regulator-boot-on;
     66	/delete-property/regulator-always-on;
     67};
     68
     69&src_pp3300_l28a {
     70	regulator-min-microvolt = <3008000>;
     71	regulator-max-microvolt = <3008000>;
     72};
     73
     74&src_vreg_bob {
     75	regulator-min-microvolt = <3500000>;
     76	regulator-max-microvolt = <3500000>;
     77	vin-supply = <&pp3500_a_vbob>;
     78};
     79
     80/*
     81 * NON-REGULATOR OVERRIDES
     82 * (modifications to sdm845-cheza.dtsi) - alphabetized by dtsi label
     83 */
     84
     85/* PINCTRL - board-specific pinctrl */
     86
     87&tlmm {
     88	gpio-line-names = "AP_SPI_FP_MISO",
     89			  "AP_SPI_FP_MOSI",
     90			  "AP_SPI_FP_CLK",
     91			  "AP_SPI_FP_CS_L",
     92			  "UART_AP_TX_DBG_RX",
     93			  "UART_DBG_TX_AP_RX",
     94			  "BRIJ_SUSPEND",
     95			  "FP_RST_L",
     96			  "FCAM_EN",
     97			  "",
     98			  "EDP_BRIJ_IRQ",
     99			  "EC_IN_RW_ODL",
    100			  "",
    101			  "RCAM_MCLK",
    102			  "FCAM_MCLK",
    103			  "",
    104			  "RCAM_EN",
    105			  "CCI0_SDA",
    106			  "CCI0_SCL",
    107			  "CCI1_SDA",
    108			  "CCI1_SCL",
    109			  "FCAM_RST_L",
    110			  "FPMCU_BOOT0",
    111			  "PEN_RST_L",
    112			  "PEN_IRQ_L",
    113			  "FPMCU_SEL_OD",
    114			  "RCAM_VSYNC",
    115			  "ESIM_MISO",
    116			  "ESIM_MOSI",
    117			  "ESIM_CLK",
    118			  "ESIM_CS_L",
    119			  "AP_PEN_1V8_SDA",
    120			  "AP_PEN_1V8_SCL",
    121			  "AP_TS_I2C_SDA",
    122			  "AP_TS_I2C_SCL",
    123			  "RCAM_RST_L",
    124			  "",
    125			  "AP_EDP_BKLTEN",
    126			  "AP_BRD_ID1",
    127			  "BOOT_CONFIG_4",
    128			  "AMP_IRQ_L",
    129			  "EDP_BRIJ_I2C_SDA",
    130			  "EDP_BRIJ_I2C_SCL",
    131			  "EN_PP3300_DX_EDP",
    132			  "SD_CD_ODL",
    133			  "BT_UART_RTS",
    134			  "BT_UART_CTS",
    135			  "BT_UART_RXD",
    136			  "BT_UART_TXD",
    137			  "AMP_I2C_SDA",
    138			  "AMP_I2C_SCL",
    139			  "AP_BRD_ID3",
    140			  "",
    141			  "AP_EC_SPI_CLK",
    142			  "AP_EC_SPI_CS_L",
    143			  "AP_EC_SPI_MISO",
    144			  "AP_EC_SPI_MOSI",
    145			  "FORCED_USB_BOOT",
    146			  "AMP_BCLK",
    147			  "AMP_LRCLK",
    148			  "AMP_DOUT",
    149			  "AMP_DIN",
    150			  "AP_BRD_ID2",
    151			  "PEN_PDCT_L",
    152			  "HP_MCLK",
    153			  "HP_BCLK",
    154			  "HP_LRCLK",
    155			  "HP_DOUT",
    156			  "HP_DIN",
    157			  "",
    158			  "",
    159			  "",
    160			  "",
    161			  "BT_SLIMBUS_DATA",
    162			  "BT_SLIMBUS_CLK",
    163			  "AMP_RESET_L",
    164			  "",
    165			  "FCAM_VSYNC",
    166			  "",
    167			  "AP_SKU_ID1",
    168			  "EC_WOV_BCLK",
    169			  "EC_WOV_LRCLK",
    170			  "EC_WOV_DOUT",
    171			  "",
    172			  "",
    173			  "AP_H1_SPI_MISO",
    174			  "AP_H1_SPI_MOSI",
    175			  "AP_H1_SPI_CLK",
    176			  "AP_H1_SPI_CS_L",
    177			  "",
    178			  "AP_SPI_CS0_L",
    179			  "AP_SPI_MOSI",
    180			  "AP_SPI_MISO",
    181			  "",
    182			  "",
    183			  "AP_SPI_CLK",
    184			  "",
    185			  "RFFE6_CLK",
    186			  "RFFE6_DATA",
    187			  "BOOT_CONFIG_1",
    188			  "BOOT_CONFIG_2",
    189			  "BOOT_CONFIG_0",
    190			  "EDP_BRIJ_EN",
    191			  "",
    192			  "USB_HS_TX_EN",
    193			  "UIM2_DATA",
    194			  "UIM2_CLK",
    195			  "UIM2_RST",
    196			  "UIM2_PRESENT",
    197			  "UIM1_DATA",
    198			  "UIM1_CLK",
    199			  "UIM1_RST",
    200			  "",
    201			  "AP_SKU_ID2",
    202			  "SDM_GRFC_8",
    203			  "SDM_GRFC_9",
    204			  "AP_RST_REQ",
    205			  "HP_IRQ",
    206			  "TS_RESET_L",
    207			  "PEN_EJECT_ODL",
    208			  "HUB_RST_L",
    209			  "FP_TO_AP_IRQ",
    210			  "AP_EC_INT_L",
    211			  "",
    212			  "",
    213			  "TS_INT_L",
    214			  "AP_SUSPEND_L",
    215			  "SDM_GRFC_3",
    216			  "",
    217			  "H1_AP_INT_ODL",
    218			  "QLINK_REQ",
    219			  "QLINK_EN",
    220			  "SDM_GRFC_2",
    221			  "BOOT_CONFIG_3",
    222			  "WMSS_RESET_L",
    223			  "SDM_GRFC_0",
    224			  "SDM_GRFC_1",
    225			  "RFFE3_DATA",
    226			  "RFFE3_CLK",
    227			  "RFFE4_DATA",
    228			  "RFFE4_CLK",
    229			  "RFFE5_DATA",
    230			  "RFFE5_CLK",
    231			  "GNSS_EN",
    232			  "WCI2_LTE_COEX_RXD",
    233			  "WCI2_LTE_COEX_TXD",
    234			  "AP_RAM_ID1",
    235			  "AP_RAM_ID2",
    236			  "RFFE1_DATA",
    237			  "RFFE1_CLK";
    238};