cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

draak.dtsi (13383B)


      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * Device Tree Source for the Draak board
      4 *
      5 * Copyright (C) 2016-2018 Renesas Electronics Corp.
      6 * Copyright (C) 2017 Glider bvba
      7 */
      8
      9#include <dt-bindings/gpio/gpio.h>
     10#include <dt-bindings/input/input.h>
     11
     12/ {
     13	model = "Renesas Draak board";
     14	compatible = "renesas,draak";
     15
     16	aliases {
     17		serial0 = &scif2;
     18		ethernet0 = &avb;
     19	};
     20
     21	audio_clkout: audio-clkout {
     22		/*
     23		 * This is same as <&rcar_sound 0>
     24		 * but needed to avoid cs2000/rcar_sound probe dead-lock
     25		 */
     26		compatible = "fixed-clock";
     27		#clock-cells = <0>;
     28		clock-frequency = <12288000>;
     29	};
     30
     31	backlight: backlight {
     32		compatible = "pwm-backlight";
     33		pwms = <&pwm1 0 50000>;
     34
     35		brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>;
     36		default-brightness-level = <10>;
     37
     38		power-supply = <&reg_12p0v>;
     39		enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
     40	};
     41
     42	chosen {
     43		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
     44		stdout-path = "serial0:115200n8";
     45	};
     46
     47	composite-in {
     48		compatible = "composite-video-connector";
     49
     50		port {
     51			composite_con_in: endpoint {
     52				remote-endpoint = <&adv7180_in>;
     53			};
     54		};
     55	};
     56
     57	hdmi-in {
     58		compatible = "hdmi-connector";
     59		type = "a";
     60
     61		port {
     62			hdmi_con_in: endpoint {
     63				remote-endpoint = <&adv7612_in>;
     64			};
     65		};
     66	};
     67
     68	hdmi-out {
     69		compatible = "hdmi-connector";
     70		type = "a";
     71
     72		port {
     73			hdmi_con_out: endpoint {
     74				remote-endpoint = <&adv7511_out>;
     75			};
     76		};
     77	};
     78
     79	keys {
     80		compatible = "gpio-keys";
     81
     82		pinctrl-0 = <&keys_pins>;
     83		pinctrl-names = "default";
     84
     85		key-1 {
     86			gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
     87			linux,code = <KEY_1>;
     88			label = "SW56-1";
     89			wakeup-source;
     90			debounce-interval = <20>;
     91		};
     92		key-2 {
     93			gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
     94			linux,code = <KEY_2>;
     95			label = "SW56-2";
     96			wakeup-source;
     97			debounce-interval = <20>;
     98		};
     99		key-3 {
    100			gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
    101			linux,code = <KEY_3>;
    102			label = "SW56-3";
    103			wakeup-source;
    104			debounce-interval = <20>;
    105		};
    106		key-4 {
    107			gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
    108			linux,code = <KEY_4>;
    109			label = "SW56-4";
    110			wakeup-source;
    111			debounce-interval = <20>;
    112		};
    113	};
    114
    115	lvds-decoder {
    116		compatible = "thine,thc63lvd1024";
    117		vcc-supply = <&reg_3p3v>;
    118
    119		ports {
    120			#address-cells = <1>;
    121			#size-cells = <0>;
    122
    123			port@0 {
    124				reg = <0>;
    125				thc63lvd1024_in: endpoint {
    126					remote-endpoint = <&lvds0_out>;
    127				};
    128			};
    129
    130			port@2 {
    131				reg = <2>;
    132				thc63lvd1024_out: endpoint {
    133					remote-endpoint = <&adv7511_in>;
    134				};
    135			};
    136		};
    137	};
    138
    139	memory@48000000 {
    140		device_type = "memory";
    141		/* first 128MB is reserved for secure area. */
    142		reg = <0x0 0x48000000 0x0 0x18000000>;
    143	};
    144
    145	reg_1p8v: regulator-1p8v {
    146		compatible = "regulator-fixed";
    147		regulator-name = "fixed-1.8V";
    148		regulator-min-microvolt = <1800000>;
    149		regulator-max-microvolt = <1800000>;
    150		regulator-boot-on;
    151		regulator-always-on;
    152	};
    153
    154	reg_3p3v: regulator-3p3v {
    155		compatible = "regulator-fixed";
    156		regulator-name = "fixed-3.3V";
    157		regulator-min-microvolt = <3300000>;
    158		regulator-max-microvolt = <3300000>;
    159		regulator-boot-on;
    160		regulator-always-on;
    161	};
    162
    163	reg_12p0v: regulator-12p0v {
    164		compatible = "regulator-fixed";
    165		regulator-name = "D12.0V";
    166		regulator-min-microvolt = <12000000>;
    167		regulator-max-microvolt = <12000000>;
    168		regulator-boot-on;
    169		regulator-always-on;
    170	};
    171
    172	sound_card: sound {
    173		compatible = "audio-graph-card";
    174
    175		dais = <&rsnd_port0	/* ak4613 */
    176			/* HDMI is not yet supported */
    177		>;
    178	};
    179
    180	vga {
    181		compatible = "vga-connector";
    182
    183		port {
    184			vga_in: endpoint {
    185				remote-endpoint = <&adv7123_out>;
    186			};
    187		};
    188	};
    189
    190	vga-encoder {
    191		compatible = "adi,adv7123";
    192
    193		ports {
    194			#address-cells = <1>;
    195			#size-cells = <0>;
    196
    197			port@0 {
    198				reg = <0>;
    199				adv7123_in: endpoint {
    200					remote-endpoint = <&du_out_rgb>;
    201				};
    202			};
    203			port@1 {
    204				reg = <1>;
    205				adv7123_out: endpoint {
    206					remote-endpoint = <&vga_in>;
    207				};
    208			};
    209		};
    210	};
    211
    212	x12_clk: x12 {
    213		compatible = "fixed-clock";
    214		#clock-cells = <0>;
    215		clock-frequency = <74250000>;
    216	};
    217
    218	x19_clk: x19 {
    219		compatible = "fixed-clock";
    220		#clock-cells = <0>;
    221		clock-frequency = <24576000>;
    222	};
    223};
    224
    225&audio_clk_b {
    226	/*
    227	 * X11 is connected to VI4_FIELD/SCIF_CLK/AUDIO_CLKB,
    228	 * and R-Car Sound uses AUDIO_CLKB.
    229	 * Note is that schematic indicates VI4_FIELD conection only
    230	 * not AUDIO_CLKB at SoC page.
    231	 * And this VI4_FIELD/SCIF_CLK/AUDIO_CLKB is connected to SW60.
    232	 * SW60 should be 1-2.
    233	 */
    234
    235	clock-frequency = <22579200>;
    236};
    237
    238&avb {
    239	pinctrl-0 = <&avb0_pins>;
    240	pinctrl-names = "default";
    241	renesas,no-ether-link;
    242	phy-handle = <&phy0>;
    243	status = "okay";
    244
    245	phy0: ethernet-phy@0 {
    246		compatible = "ethernet-phy-id0022.1622",
    247			     "ethernet-phy-ieee802.3-c22";
    248		rxc-skew-ps = <1500>;
    249		reg = <0>;
    250		interrupt-parent = <&gpio5>;
    251		interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
    252		reset-gpios = <&gpio5 18 GPIO_ACTIVE_LOW>;
    253		/*
    254		 * TX clock internal delay mode is required for reliable
    255		 * 1Gbps communication using the KSZ9031RNX phy present on
    256		 * the Draak board, however, TX clock internal delay mode
    257		 * isn't supported on R-Car D3(e).  Thus, limit speed to
    258		 * 100Mbps for reliable communication.
    259		 */
    260		max-speed = <100>;
    261	};
    262};
    263
    264&can0 {
    265	pinctrl-0 = <&can0_pins>;
    266	pinctrl-names = "default";
    267	status = "okay";
    268};
    269
    270&can1 {
    271	pinctrl-0 = <&can1_pins>;
    272	pinctrl-names = "default";
    273	status = "okay";
    274};
    275
    276&du {
    277	pinctrl-0 = <&du_pins>;
    278	pinctrl-names = "default";
    279	status = "okay";
    280
    281	clocks = <&cpg CPG_MOD 724>,
    282		 <&cpg CPG_MOD 723>,
    283		 <&x12_clk>;
    284	clock-names = "du.0", "du.1", "dclkin.0";
    285
    286	ports {
    287		port@0 {
    288			du_out_rgb: endpoint {
    289				remote-endpoint = <&adv7123_in>;
    290			};
    291		};
    292	};
    293};
    294
    295&ehci0 {
    296	dr_mode = "host";
    297	status = "okay";
    298};
    299
    300&extal_clk {
    301	clock-frequency = <48000000>;
    302};
    303
    304&hsusb {
    305	dr_mode = "host";
    306	status = "okay";
    307};
    308
    309&i2c0 {
    310	pinctrl-0 = <&i2c0_pins>;
    311	pinctrl-names = "default";
    312	status = "okay";
    313
    314	ak4613: codec@10 {
    315		compatible = "asahi-kasei,ak4613";
    316		#sound-dai-cells = <0>;
    317		reg = <0x10>;
    318		clocks = <&rcar_sound 0>; /* audio_clkout */
    319
    320		asahi-kasei,in1-single-end;
    321		asahi-kasei,in2-single-end;
    322		asahi-kasei,out1-single-end;
    323		asahi-kasei,out2-single-end;
    324		asahi-kasei,out3-single-end;
    325		asahi-kasei,out4-single-end;
    326		asahi-kasei,out5-single-end;
    327		asahi-kasei,out6-single-end;
    328
    329		port {
    330			ak4613_endpoint: endpoint {
    331				remote-endpoint = <&rsnd_for_ak4613>;
    332			};
    333		};
    334	};
    335
    336	composite-in@20 {
    337		compatible = "adi,adv7180cp";
    338		reg = <0x20>;
    339
    340		ports {
    341			#address-cells = <1>;
    342			#size-cells = <0>;
    343
    344			port@0 {
    345				reg = <0>;
    346				adv7180_in: endpoint {
    347					remote-endpoint = <&composite_con_in>;
    348				};
    349			};
    350
    351			port@3 {
    352				reg = <3>;
    353
    354				/*
    355				 * The VIN4 video input path is shared between
    356				 * CVBS and HDMI inputs through SW[49-53]
    357				 * switches.
    358				 *
    359				 * CVBS is the default selection, link it to
    360				 * VIN4 here.
    361				 */
    362				adv7180_out: endpoint {
    363					remote-endpoint = <&vin4_in>;
    364				};
    365			};
    366		};
    367
    368	};
    369
    370	hdmi-encoder@39 {
    371		compatible = "adi,adv7511w";
    372		reg = <0x39>, <0x3f>, <0x3c>, <0x38>;
    373		reg-names = "main", "edid", "cec", "packet";
    374		interrupt-parent = <&gpio1>;
    375		interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
    376
    377		adi,input-depth = <8>;
    378		adi,input-colorspace = "rgb";
    379		adi,input-clock = "1x";
    380
    381		ports {
    382			#address-cells = <1>;
    383			#size-cells = <0>;
    384
    385			port@0 {
    386				reg = <0>;
    387				adv7511_in: endpoint {
    388					remote-endpoint = <&thc63lvd1024_out>;
    389				};
    390			};
    391
    392			port@1 {
    393				reg = <1>;
    394				adv7511_out: endpoint {
    395					remote-endpoint = <&hdmi_con_out>;
    396				};
    397			};
    398		};
    399	};
    400
    401	hdmi-decoder@4c {
    402		compatible = "adi,adv7612";
    403		reg = <0x4c>;
    404		default-input = <0>;
    405
    406		ports {
    407			#address-cells = <1>;
    408			#size-cells = <0>;
    409
    410			port@0 {
    411				reg = <0>;
    412
    413				adv7612_in: endpoint {
    414					remote-endpoint = <&hdmi_con_in>;
    415				};
    416			};
    417
    418			port@2 {
    419				reg = <2>;
    420
    421				/*
    422				 * The VIN4 video input path is shared between
    423				 * CVBS and HDMI inputs through SW[49-53]
    424				 * switches.
    425				 *
    426				 * CVBS is the default selection, leave HDMI
    427				 * not connected here.
    428				 */
    429				adv7612_out: endpoint {
    430					pclk-sample = <0>;
    431					hsync-active = <0>;
    432					vsync-active = <0>;
    433				};
    434			};
    435		};
    436	};
    437
    438	cs2000: clk-multiplier@4f {
    439		#clock-cells = <0>;
    440		compatible = "cirrus,cs2000-cp";
    441		reg = <0x4f>;
    442		clocks = <&audio_clkout>, <&x19_clk>; /* audio_clkout_1, x19 */
    443		clock-names = "clk_in", "ref_clk";
    444
    445		assigned-clocks = <&cs2000>;
    446		assigned-clock-rates = <24576000>; /* 1/1 divide */
    447	};
    448
    449	eeprom@50 {
    450		compatible = "rohm,br24t01", "atmel,24c01";
    451		reg = <0x50>;
    452		pagesize = <8>;
    453	};
    454};
    455
    456&i2c1 {
    457	pinctrl-0 = <&i2c1_pins>;
    458	pinctrl-names = "default";
    459	status = "okay";
    460};
    461
    462&lvds0 {
    463	status = "okay";
    464
    465	clocks = <&cpg CPG_MOD 727>,
    466		 <&x12_clk>,
    467		 <&extal_clk>;
    468	clock-names = "fck", "dclkin.0", "extal";
    469
    470	ports {
    471		port@1 {
    472			lvds0_out: endpoint {
    473				remote-endpoint = <&thc63lvd1024_in>;
    474			};
    475		};
    476	};
    477};
    478
    479&lvds1 {
    480	/*
    481	 * Even though the LVDS1 output is not connected, the encoder must be
    482	 * enabled to supply a pixel clock to the DU for the DPAD output when
    483	 * LVDS0 is in use.
    484	 */
    485	status = "okay";
    486
    487	clocks = <&cpg CPG_MOD 727>,
    488		 <&x12_clk>,
    489		 <&extal_clk>;
    490	clock-names = "fck", "dclkin.0", "extal";
    491};
    492
    493&ohci0 {
    494	dr_mode = "host";
    495	status = "okay";
    496};
    497
    498&pfc {
    499	avb0_pins: avb {
    500		groups = "avb0_link", "avb0_mdio", "avb0_mii";
    501		function = "avb0";
    502	};
    503
    504	can0_pins: can0 {
    505		groups = "can0_data_a";
    506		function = "can0";
    507	};
    508
    509	can1_pins: can1 {
    510		groups = "can1_data_a";
    511		function = "can1";
    512	};
    513
    514	du_pins: du {
    515		groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
    516		function = "du";
    517	};
    518
    519	i2c0_pins: i2c0 {
    520		groups = "i2c0";
    521		function = "i2c0";
    522	};
    523
    524	i2c1_pins: i2c1 {
    525		groups = "i2c1";
    526		function = "i2c1";
    527	};
    528
    529	keys_pins: keys {
    530		pins = "GP_4_12", "GP_4_13", "GP_4_14", "GP_4_15";
    531		bias-pull-up;
    532	};
    533
    534	pwm0_pins: pwm0 {
    535		groups = "pwm0_c";
    536		function = "pwm0";
    537	};
    538
    539	pwm1_pins: pwm1 {
    540		groups = "pwm1_c";
    541		function = "pwm1";
    542	};
    543
    544	rpc_pins: rpc {
    545		groups = "rpc_clk2", "rpc_ctrl", "rpc_data", "rpc_reset",
    546			 "rpc_int";
    547		function = "rpc";
    548	};
    549
    550	scif2_pins: scif2 {
    551		groups = "scif2_data";
    552		function = "scif2";
    553	};
    554
    555	sdhi2_pins: sd2 {
    556		groups = "mmc_data8", "mmc_ctrl";
    557		function = "mmc";
    558		power-source = <1800>;
    559	};
    560
    561	sdhi2_pins_uhs: sd2_uhs {
    562		groups = "mmc_data8", "mmc_ctrl";
    563		function = "mmc";
    564		power-source = <1800>;
    565	};
    566
    567	sound_pins: sound {
    568		groups = "ssi34_ctrl", "ssi3_data", "ssi4_data_a";
    569		function = "ssi";
    570	};
    571
    572	sound_clk_pins: sound-clk {
    573		groups = "audio_clk_a", "audio_clk_b",
    574			 "audio_clkout", "audio_clkout1";
    575		function = "audio_clk";
    576	};
    577
    578	usb0_pins: usb0 {
    579		groups = "usb0";
    580		function = "usb0";
    581	};
    582
    583	vin4_pins_cvbs: vin4 {
    584		groups = "vin4_data8", "vin4_sync", "vin4_clk";
    585		function = "vin4";
    586	};
    587};
    588
    589&pwm0 {
    590	pinctrl-0 = <&pwm0_pins>;
    591	pinctrl-names = "default";
    592
    593	status = "okay";
    594};
    595
    596&pwm1 {
    597	pinctrl-0 = <&pwm1_pins>;
    598	pinctrl-names = "default";
    599
    600	status = "okay";
    601};
    602
    603&rcar_sound {
    604	pinctrl-0 = <&sound_pins>, <&sound_clk_pins>;
    605	pinctrl-names = "default";
    606
    607	/* Single DAI */
    608	#sound-dai-cells = <0>;
    609
    610	/* audio_clkout0/1 */
    611	#clock-cells = <1>;
    612	clock-frequency = <12288000 11289600>;
    613
    614	status = "okay";
    615
    616	clocks = <&cpg CPG_MOD 1005>,
    617		 <&cpg CPG_MOD 1011>, <&cpg CPG_MOD 1012>,
    618		 <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
    619		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
    620		 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
    621		 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
    622		 <&cs2000>, <&audio_clk_b>,
    623		 <&cpg CPG_CORE R8A77995_CLK_ZA2>;
    624
    625	ports {
    626		rsnd_port0: port {
    627			rsnd_for_ak4613: endpoint {
    628				remote-endpoint = <&ak4613_endpoint>;
    629				dai-format = "left_j";
    630				bitclock-master = <&rsnd_for_ak4613>;
    631				frame-master = <&rsnd_for_ak4613>;
    632				playback = <&ssi3>, <&src5>, <&dvc0>;
    633				capture  = <&ssi4>, <&src6>, <&dvc1>;
    634			};
    635		};
    636	};
    637};
    638
    639&rpc {
    640	pinctrl-0 = <&rpc_pins>;
    641	pinctrl-names = "default";
    642
    643	/* Left disabled.  To be enabled by firmware when unlocked. */
    644
    645	flash@0 {
    646		compatible = "cypress,hyperflash", "cfi-flash";
    647		reg = <0>;
    648
    649		partitions {
    650			compatible = "fixed-partitions";
    651			#address-cells = <1>;
    652			#size-cells = <1>;
    653
    654			bootparam@0 {
    655				reg = <0x00000000 0x040000>;
    656				read-only;
    657			};
    658			bl2@40000 {
    659				reg = <0x00040000 0x140000>;
    660				read-only;
    661			};
    662			cert_header_sa6@180000 {
    663				reg = <0x00180000 0x040000>;
    664				read-only;
    665			};
    666			bl31@1c0000 {
    667				reg = <0x001c0000 0x040000>;
    668				read-only;
    669			};
    670			tee@200000 {
    671				reg = <0x00200000 0x440000>;
    672				read-only;
    673			};
    674			uboot@640000 {
    675				reg = <0x00640000 0x100000>;
    676				read-only;
    677			};
    678			dtb@740000 {
    679				reg = <0x00740000 0x080000>;
    680			};
    681			kernel@7c0000 {
    682				reg = <0x007c0000 0x1400000>;
    683			};
    684			user@1bc0000 {
    685				reg = <0x01bc0000 0x2440000>;
    686			};
    687		};
    688	};
    689};
    690
    691&rwdt {
    692	timeout-sec = <60>;
    693	status = "okay";
    694};
    695
    696&scif2 {
    697	pinctrl-0 = <&scif2_pins>;
    698	pinctrl-names = "default";
    699
    700	status = "okay";
    701};
    702
    703&sdhi2 {
    704	/* used for on-board eMMC */
    705	pinctrl-0 = <&sdhi2_pins>;
    706	pinctrl-1 = <&sdhi2_pins_uhs>;
    707	pinctrl-names = "default", "state_uhs";
    708
    709	vmmc-supply = <&reg_3p3v>;
    710	vqmmc-supply = <&reg_1p8v>;
    711	bus-width = <8>;
    712	mmc-hs200-1_8v;
    713	no-sd;
    714	no-sdio;
    715	non-removable;
    716	status = "okay";
    717};
    718
    719&ssi4 {
    720	shared-pin;
    721};
    722
    723&usb2_phy0 {
    724	pinctrl-0 = <&usb0_pins>;
    725	pinctrl-names = "default";
    726
    727	renesas,no-otg-pins;
    728	status = "okay";
    729};
    730
    731&vin4 {
    732	pinctrl-0 = <&vin4_pins_cvbs>;
    733	pinctrl-names = "default";
    734
    735	status = "okay";
    736
    737	ports {
    738		port {
    739			vin4_in: endpoint {
    740				remote-endpoint = <&adv7180_out>;
    741			};
    742		};
    743	};
    744};