cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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r8a77970-eagle.dts (6222B)


      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * Device Tree Source for the Eagle board with R-Car V3M
      4 *
      5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
      6 * Copyright (C) 2017 Cogent Embedded, Inc.
      7 */
      8
      9/dts-v1/;
     10#include "r8a77970.dtsi"
     11#include <dt-bindings/gpio/gpio.h>
     12
     13/ {
     14	model = "Renesas Eagle board based on r8a77970";
     15	compatible = "renesas,eagle", "renesas,r8a77970";
     16
     17	aliases {
     18		serial0 = &scif0;
     19		ethernet0 = &avb;
     20	};
     21
     22	chosen {
     23		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
     24		stdout-path = "serial0:115200n8";
     25	};
     26
     27	d3p3: regulator-fixed {
     28		compatible = "regulator-fixed";
     29		regulator-name = "fixed-3.3V";
     30		regulator-min-microvolt = <3300000>;
     31		regulator-max-microvolt = <3300000>;
     32		regulator-boot-on;
     33		regulator-always-on;
     34	};
     35
     36	hdmi-out {
     37		compatible = "hdmi-connector";
     38		type = "a";
     39
     40		port {
     41			hdmi_con_out: endpoint {
     42				remote-endpoint = <&adv7511_out>;
     43			};
     44		};
     45	};
     46
     47	lvds-decoder {
     48		compatible = "thine,thc63lvd1024";
     49
     50		vcc-supply = <&d3p3>;
     51
     52		ports {
     53			#address-cells = <1>;
     54			#size-cells = <0>;
     55
     56			port@0 {
     57				reg = <0>;
     58				thc63lvd1024_in: endpoint {
     59					remote-endpoint = <&lvds0_out>;
     60				};
     61			};
     62
     63			port@2 {
     64				reg = <2>;
     65				thc63lvd1024_out: endpoint {
     66					remote-endpoint = <&adv7511_in>;
     67				};
     68			};
     69		};
     70	};
     71
     72	memory@48000000 {
     73		device_type = "memory";
     74		/* first 128MB is reserved for secure area. */
     75		reg = <0x0 0x48000000 0x0 0x38000000>;
     76	};
     77
     78	x1_clk: x1-clock {
     79		compatible = "fixed-clock";
     80		#clock-cells = <0>;
     81		clock-frequency = <148500000>;
     82	};
     83};
     84
     85&avb {
     86	pinctrl-0 = <&avb_pins>;
     87	pinctrl-names = "default";
     88
     89	renesas,no-ether-link;
     90	phy-handle = <&phy0>;
     91	rx-internal-delay-ps = <1800>;
     92	tx-internal-delay-ps = <2000>;
     93	status = "okay";
     94
     95	phy0: ethernet-phy@0 {
     96		compatible = "ethernet-phy-id0022.1622",
     97			     "ethernet-phy-ieee802.3-c22";
     98		rxc-skew-ps = <1500>;
     99		reg = <0>;
    100		interrupt-parent = <&gpio1>;
    101		interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
    102		reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
    103	};
    104};
    105
    106&canfd {
    107	pinctrl-0 = <&canfd0_pins>;
    108	pinctrl-names = "default";
    109	status = "okay";
    110
    111	channel0 {
    112		status = "okay";
    113	};
    114};
    115
    116&csi40 {
    117	status = "okay";
    118
    119	ports {
    120		port@0 {
    121			csi40_in: endpoint {
    122				clock-lanes = <0>;
    123				data-lanes = <1 2 3 4>;
    124				remote-endpoint = <&max9286_out0>;
    125			};
    126		};
    127	};
    128};
    129
    130&du {
    131	clocks = <&cpg CPG_MOD 724>, <&x1_clk>;
    132	clock-names = "du.0", "dclkin.0";
    133	status = "okay";
    134};
    135
    136&extal_clk {
    137	clock-frequency = <16666666>;
    138};
    139
    140&extalr_clk {
    141	clock-frequency = <32768>;
    142};
    143
    144&i2c0 {
    145	pinctrl-0 = <&i2c0_pins>;
    146	pinctrl-names = "default";
    147
    148	status = "okay";
    149	clock-frequency = <400000>;
    150
    151	io_expander: gpio@20 {
    152		compatible = "onnn,pca9654";
    153		reg = <0x20>;
    154		gpio-controller;
    155		#gpio-cells = <2>;
    156	};
    157
    158	hdmi@39 {
    159		compatible = "adi,adv7511w";
    160		reg = <0x39>;
    161		interrupt-parent = <&gpio1>;
    162		interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
    163
    164		adi,input-depth = <8>;
    165		adi,input-colorspace = "rgb";
    166		adi,input-clock = "1x";
    167
    168		ports {
    169			#address-cells = <1>;
    170			#size-cells = <0>;
    171
    172			port@0 {
    173				reg = <0>;
    174				adv7511_in: endpoint {
    175					remote-endpoint = <&thc63lvd1024_out>;
    176				};
    177			};
    178
    179			port@1 {
    180				reg = <1>;
    181				adv7511_out: endpoint {
    182					remote-endpoint = <&hdmi_con_out>;
    183				};
    184			};
    185		};
    186	};
    187};
    188
    189&i2c3 {
    190	pinctrl-0 = <&i2c3_pins>;
    191	pinctrl-names = "default";
    192
    193	status = "okay";
    194	clock-frequency = <400000>;
    195
    196	gmsl0: gmsl-deserializer@48 {
    197		compatible = "maxim,max9286";
    198		reg = <0x48>;
    199
    200		maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
    201		enable-gpios = <&io_expander 0 GPIO_ACTIVE_HIGH>;
    202
    203		ports {
    204			#address-cells = <1>;
    205			#size-cells = <0>;
    206
    207			port@0 {
    208				reg = <0>;
    209			};
    210
    211			port@1 {
    212				reg = <1>;
    213			};
    214
    215			port@2 {
    216				reg = <2>;
    217			};
    218
    219			port@3 {
    220				reg = <3>;
    221			};
    222
    223			port@4 {
    224				reg = <4>;
    225				max9286_out0: endpoint {
    226					clock-lanes = <0>;
    227					data-lanes = <1 2 3 4>;
    228					remote-endpoint = <&csi40_in>;
    229				};
    230			};
    231		};
    232
    233		i2c-mux {
    234			#address-cells = <1>;
    235			#size-cells = <0>;
    236
    237			i2c@0 {
    238				#address-cells = <1>;
    239				#size-cells = <0>;
    240				reg = <0>;
    241
    242				status = "disabled";
    243			};
    244
    245			i2c@1 {
    246				#address-cells = <1>;
    247				#size-cells = <0>;
    248				reg = <1>;
    249
    250				status = "disabled";
    251			};
    252
    253			i2c@2 {
    254				#address-cells = <1>;
    255				#size-cells = <0>;
    256				reg = <2>;
    257
    258				status = "disabled";
    259			};
    260
    261			i2c@3 {
    262				#address-cells = <1>;
    263				#size-cells = <0>;
    264				reg = <3>;
    265
    266				status = "disabled";
    267			};
    268		};
    269	};
    270};
    271
    272&lvds0 {
    273	status = "okay";
    274
    275	ports {
    276		port@1 {
    277			lvds0_out: endpoint {
    278				remote-endpoint = <&thc63lvd1024_in>;
    279			};
    280		};
    281	};
    282};
    283
    284&pfc {
    285	avb_pins: avb0 {
    286		groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
    287		function = "avb0";
    288	};
    289
    290	canfd0_pins: canfd0 {
    291		groups = "canfd0_data_a";
    292		function = "canfd0";
    293	};
    294
    295	i2c0_pins: i2c0 {
    296		groups = "i2c0";
    297		function = "i2c0";
    298	};
    299
    300	i2c3_pins: i2c3 {
    301		groups = "i2c3_a";
    302		function = "i2c3";
    303	};
    304
    305	qspi0_pins: qspi0 {
    306		groups = "qspi0_ctrl", "qspi0_data4";
    307		function = "qspi0";
    308	};
    309
    310	scif0_pins: scif0 {
    311		groups = "scif0_data";
    312		function = "scif0";
    313	};
    314};
    315
    316&rpc {
    317	pinctrl-0 = <&qspi0_pins>;
    318	pinctrl-names = "default";
    319
    320	status = "okay";
    321
    322	flash@0 {
    323		compatible = "spansion,s25fs512s", "jedec,spi-nor";
    324		reg = <0>;
    325		spi-max-frequency = <50000000>;
    326		spi-rx-bus-width = <4>;
    327
    328		partitions {
    329			compatible = "fixed-partitions";
    330			#address-cells = <1>;
    331			#size-cells = <1>;
    332
    333			bootparam@0 {
    334				reg = <0x00000000 0x040000>;
    335				read-only;
    336			};
    337			cr7@40000 {
    338				reg = <0x00040000 0x080000>;
    339				read-only;
    340			};
    341			cert_header_sa3@c0000 {
    342				reg = <0x000c0000 0x080000>;
    343				read-only;
    344			};
    345			bl2@140000 {
    346				reg = <0x00140000 0x040000>;
    347				read-only;
    348			};
    349			cert_header_sa6@180000 {
    350				reg = <0x00180000 0x040000>;
    351				read-only;
    352			};
    353			bl31@1c0000 {
    354				reg = <0x001c0000 0x460000>;
    355				read-only;
    356			};
    357			uboot@640000 {
    358				reg = <0x00640000 0x0c0000>;
    359				read-only;
    360			};
    361			uboot-env@700000 {
    362				reg = <0x00700000 0x040000>;
    363				read-only;
    364			};
    365			dtb@740000 {
    366				reg = <0x00740000 0x080000>;
    367			};
    368			kernel@7c0000 {
    369				reg = <0x007c0000 0x1400000>;
    370			};
    371			user@1bc0000 {
    372				reg = <0x01bc0000 0x2440000>;
    373			};
    374		};
    375	};
    376};
    377
    378&rwdt {
    379	timeout-sec = <60>;
    380	status = "okay";
    381};
    382
    383&scif0 {
    384	pinctrl-0 = <&scif0_pins>;
    385	pinctrl-names = "default";
    386
    387	status = "okay";
    388};