r8a77980-condor.dts (8684B)
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the Condor board with R-Car V3H 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 * Copyright (C) 2018 Cogent Embedded, Inc. 7 */ 8 9/dts-v1/; 10#include "r8a77980.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12 13/ { 14 model = "Renesas Condor board based on r8a77980"; 15 compatible = "renesas,condor", "renesas,r8a77980"; 16 17 aliases { 18 serial0 = &scif0; 19 ethernet0 = &gether; 20 }; 21 22 chosen { 23 stdout-path = "serial0:115200n8"; 24 }; 25 26 d1_8v: regulator-2 { 27 compatible = "regulator-fixed"; 28 regulator-name = "D1.8V"; 29 regulator-min-microvolt = <1800000>; 30 regulator-max-microvolt = <1800000>; 31 regulator-boot-on; 32 regulator-always-on; 33 }; 34 35 d3_3v: regulator-0 { 36 compatible = "regulator-fixed"; 37 regulator-name = "D3.3V"; 38 regulator-min-microvolt = <3300000>; 39 regulator-max-microvolt = <3300000>; 40 regulator-boot-on; 41 regulator-always-on; 42 }; 43 44 hdmi-out { 45 compatible = "hdmi-connector"; 46 type = "a"; 47 48 port { 49 hdmi_con: endpoint { 50 remote-endpoint = <&adv7511_out>; 51 }; 52 }; 53 }; 54 55 lvds-decoder { 56 compatible = "thine,thc63lvd1024"; 57 vcc-supply = <&d3_3v>; 58 59 ports { 60 #address-cells = <1>; 61 #size-cells = <0>; 62 63 port@0 { 64 reg = <0>; 65 thc63lvd1024_in: endpoint { 66 remote-endpoint = <&lvds0_out>; 67 }; 68 }; 69 70 port@2 { 71 reg = <2>; 72 thc63lvd1024_out: endpoint { 73 remote-endpoint = <&adv7511_in>; 74 }; 75 }; 76 }; 77 }; 78 79 memory@48000000 { 80 device_type = "memory"; 81 /* first 128MB is reserved for secure area. */ 82 reg = <0 0x48000000 0 0x78000000>; 83 }; 84 85 vddq_vin01: regulator-1 { 86 compatible = "regulator-fixed"; 87 regulator-name = "VDDQ_VIN01"; 88 regulator-min-microvolt = <1800000>; 89 regulator-max-microvolt = <1800000>; 90 regulator-boot-on; 91 regulator-always-on; 92 }; 93 94 x1_clk: x1-clock { 95 compatible = "fixed-clock"; 96 #clock-cells = <0>; 97 clock-frequency = <148500000>; 98 }; 99}; 100 101&canfd { 102 pinctrl-0 = <&canfd0_pins>; 103 pinctrl-names = "default"; 104 status = "okay"; 105 106 channel0 { 107 status = "okay"; 108 }; 109}; 110 111&csi40 { 112 status = "okay"; 113 114 ports { 115 port@0 { 116 csi40_in: endpoint { 117 clock-lanes = <0>; 118 data-lanes = <1 2 3 4>; 119 remote-endpoint = <&max9286_out0>; 120 }; 121 }; 122 }; 123}; 124 125&csi41 { 126 status = "okay"; 127 128 ports { 129 port@0 { 130 csi41_in: endpoint { 131 clock-lanes = <0>; 132 data-lanes = <1 2 3 4>; 133 remote-endpoint = <&max9286_out1>; 134 }; 135 }; 136 }; 137}; 138 139&du { 140 clocks = <&cpg CPG_MOD 724>, 141 <&x1_clk>; 142 clock-names = "du.0", "dclkin.0"; 143 status = "okay"; 144}; 145 146&extal_clk { 147 clock-frequency = <16666666>; 148}; 149 150&extalr_clk { 151 clock-frequency = <32768>; 152}; 153 154&gether { 155 pinctrl-0 = <&gether_pins>; 156 pinctrl-names = "default"; 157 158 phy-mode = "rgmii-id"; 159 phy-handle = <&phy0>; 160 renesas,no-ether-link; 161 status = "okay"; 162 163 phy0: ethernet-phy@0 { 164 compatible = "ethernet-phy-id0022.1622", 165 "ethernet-phy-ieee802.3-c22"; 166 rxc-skew-ps = <1500>; 167 reg = <0>; 168 interrupt-parent = <&gpio4>; 169 interrupts = <23 IRQ_TYPE_LEVEL_LOW>; 170 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 171 }; 172}; 173 174&i2c0 { 175 pinctrl-0 = <&i2c0_pins>; 176 pinctrl-names = "default"; 177 178 status = "okay"; 179 clock-frequency = <400000>; 180 181 io_expander0: gpio@20 { 182 compatible = "onnn,pca9654"; 183 reg = <0x20>; 184 gpio-controller; 185 #gpio-cells = <2>; 186 }; 187 188 io_expander1: gpio@21 { 189 compatible = "onnn,pca9654"; 190 reg = <0x21>; 191 gpio-controller; 192 #gpio-cells = <2>; 193 }; 194 195 hdmi@39 { 196 compatible = "adi,adv7511w"; 197 reg = <0x39>; 198 interrupt-parent = <&gpio1>; 199 interrupts = <20 IRQ_TYPE_LEVEL_LOW>; 200 avdd-supply = <&d1_8v>; 201 dvdd-supply = <&d1_8v>; 202 pvdd-supply = <&d1_8v>; 203 bgvdd-supply = <&d1_8v>; 204 dvdd-3v-supply = <&d3_3v>; 205 206 adi,input-depth = <8>; 207 adi,input-colorspace = "rgb"; 208 adi,input-clock = "1x"; 209 210 ports { 211 #address-cells = <1>; 212 #size-cells = <0>; 213 214 port@0 { 215 reg = <0>; 216 adv7511_in: endpoint { 217 remote-endpoint = <&thc63lvd1024_out>; 218 }; 219 }; 220 221 port@1 { 222 reg = <1>; 223 adv7511_out: endpoint { 224 remote-endpoint = <&hdmi_con>; 225 }; 226 }; 227 }; 228 }; 229}; 230 231&i2c1 { 232 pinctrl-0 = <&i2c1_pins>; 233 pinctrl-names = "default"; 234 235 status = "okay"; 236 clock-frequency = <400000>; 237 238 gmsl0: gmsl-deserializer@48 { 239 compatible = "maxim,max9286"; 240 reg = <0x48>; 241 242 maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>; 243 enable-gpios = <&io_expander0 0 GPIO_ACTIVE_HIGH>; 244 245 ports { 246 #address-cells = <1>; 247 #size-cells = <0>; 248 249 port@0 { 250 reg = <0>; 251 }; 252 253 port@1 { 254 reg = <1>; 255 }; 256 257 port@2 { 258 reg = <2>; 259 }; 260 261 port@3 { 262 reg = <3>; 263 }; 264 265 port@4 { 266 reg = <4>; 267 max9286_out0: endpoint { 268 clock-lanes = <0>; 269 data-lanes = <1 2 3 4>; 270 remote-endpoint = <&csi40_in>; 271 }; 272 }; 273 }; 274 275 i2c-mux { 276 #address-cells = <1>; 277 #size-cells = <0>; 278 279 i2c@0 { 280 #address-cells = <1>; 281 #size-cells = <0>; 282 reg = <0>; 283 284 status = "disabled"; 285 }; 286 287 i2c@1 { 288 #address-cells = <1>; 289 #size-cells = <0>; 290 reg = <1>; 291 292 status = "disabled"; 293 }; 294 295 i2c@2 { 296 #address-cells = <1>; 297 #size-cells = <0>; 298 reg = <2>; 299 300 status = "disabled"; 301 }; 302 303 i2c@3 { 304 #address-cells = <1>; 305 #size-cells = <0>; 306 reg = <3>; 307 308 status = "disabled"; 309 }; 310 }; 311 }; 312 313 gmsl1: gmsl-deserializer@4a { 314 compatible = "maxim,max9286"; 315 reg = <0x4a>; 316 317 maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>; 318 enable-gpios = <&io_expander1 0 GPIO_ACTIVE_HIGH>; 319 320 ports { 321 #address-cells = <1>; 322 #size-cells = <0>; 323 324 port@0 { 325 reg = <0>; 326 }; 327 328 port@1 { 329 reg = <1>; 330 }; 331 332 port@2 { 333 reg = <2>; 334 }; 335 336 port@3 { 337 reg = <3>; 338 }; 339 340 port@4 { 341 reg = <4>; 342 max9286_out1: endpoint { 343 clock-lanes = <0>; 344 data-lanes = <1 2 3 4>; 345 remote-endpoint = <&csi41_in>; 346 }; 347 }; 348 }; 349 350 i2c-mux { 351 #address-cells = <1>; 352 #size-cells = <0>; 353 354 i2c@0 { 355 #address-cells = <1>; 356 #size-cells = <0>; 357 reg = <0>; 358 359 status = "disabled"; 360 }; 361 362 i2c@1 { 363 #address-cells = <1>; 364 #size-cells = <0>; 365 reg = <1>; 366 367 status = "disabled"; 368 }; 369 370 i2c@2 { 371 #address-cells = <1>; 372 #size-cells = <0>; 373 reg = <2>; 374 375 status = "disabled"; 376 }; 377 378 i2c@3 { 379 #address-cells = <1>; 380 #size-cells = <0>; 381 reg = <3>; 382 383 status = "disabled"; 384 }; 385 }; 386 }; 387}; 388 389&lvds0 { 390 status = "okay"; 391 392 ports { 393 port@1 { 394 lvds0_out: endpoint { 395 remote-endpoint = <&thc63lvd1024_in>; 396 }; 397 }; 398 }; 399}; 400 401&mmc0 { 402 pinctrl-0 = <&mmc_pins>; 403 pinctrl-1 = <&mmc_pins>; 404 pinctrl-names = "default", "state_uhs"; 405 406 vmmc-supply = <&d3_3v>; 407 vqmmc-supply = <&vddq_vin01>; 408 mmc-hs200-1_8v; 409 bus-width = <8>; 410 no-sd; 411 no-sdio; 412 non-removable; 413 status = "okay"; 414}; 415 416&pciec { 417 status = "okay"; 418}; 419 420&pcie_bus_clk { 421 clock-frequency = <100000000>; 422}; 423 424&pcie_phy { 425 status = "okay"; 426}; 427 428&pfc { 429 canfd0_pins: canfd0 { 430 groups = "canfd0_data_a"; 431 function = "canfd0"; 432 }; 433 434 gether_pins: gether { 435 groups = "gether_mdio_a", "gether_rgmii", 436 "gether_txcrefclk", "gether_txcrefclk_mega"; 437 function = "gether"; 438 }; 439 440 i2c0_pins: i2c0 { 441 groups = "i2c0"; 442 function = "i2c0"; 443 }; 444 445 i2c1_pins: i2c1 { 446 groups = "i2c1"; 447 function = "i2c1"; 448 }; 449 450 mmc_pins: mmc { 451 groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; 452 function = "mmc"; 453 power-source = <1800>; 454 }; 455 456 qspi0_pins: qspi0 { 457 groups = "qspi0_ctrl", "qspi0_data4"; 458 function = "qspi0"; 459 }; 460 461 scif0_pins: scif0 { 462 groups = "scif0_data"; 463 function = "scif0"; 464 }; 465 466 scif_clk_pins: scif_clk { 467 groups = "scif_clk_b"; 468 function = "scif_clk"; 469 }; 470}; 471 472&rpc { 473 pinctrl-0 = <&qspi0_pins>; 474 pinctrl-names = "default"; 475 476 status = "okay"; 477 478 flash@0 { 479 compatible = "spansion,s25fs512s", "jedec,spi-nor"; 480 reg = <0>; 481 spi-max-frequency = <50000000>; 482 spi-rx-bus-width = <4>; 483 484 partitions { 485 compatible = "fixed-partitions"; 486 #address-cells = <1>; 487 #size-cells = <1>; 488 489 bootparam@0 { 490 reg = <0x00000000 0x040000>; 491 read-only; 492 }; 493 cr7@40000 { 494 reg = <0x00040000 0x080000>; 495 read-only; 496 }; 497 cert_header_sa3@c0000 { 498 reg = <0x000c0000 0x080000>; 499 read-only; 500 }; 501 bl2@140000 { 502 reg = <0x00140000 0x040000>; 503 read-only; 504 }; 505 cert_header_sa6@180000 { 506 reg = <0x00180000 0x040000>; 507 read-only; 508 }; 509 bl31@1c0000 { 510 reg = <0x001c0000 0x460000>; 511 read-only; 512 }; 513 uboot@640000 { 514 reg = <0x00640000 0x0c0000>; 515 read-only; 516 }; 517 uboot-env@700000 { 518 reg = <0x00700000 0x040000>; 519 read-only; 520 }; 521 dtb@740000 { 522 reg = <0x00740000 0x080000>; 523 }; 524 kernel@7c0000 { 525 reg = <0x007c0000 0x1400000>; 526 }; 527 user@1bc0000 { 528 reg = <0x01bc0000 0x2440000>; 529 }; 530 }; 531 }; 532}; 533 534&rwdt { 535 timeout-sec = <60>; 536 status = "okay"; 537}; 538 539&scif0 { 540 pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; 541 pinctrl-names = "default"; 542 543 status = "okay"; 544}; 545 546&scif_clk { 547 clock-frequency = <14745600>; 548};