cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

r8a779a0-falcon-csi-dsi.dtsi (3338B)

      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * Device Tree Source for the Falcon CSI/DSI sub-board
      4 *
      5 * Copyright (C) 2021 Glider bv
      6 */
      7
      8&csi40 {
      9	status = "okay";
     10
     11	ports {
     12		#address-cells = <1>;
     13		#size-cells = <0>;
     14
     15		port@0 {
     16			reg = <0>;
     17
     18			csi40_in: endpoint {
     19				clock-lanes = <0>;
     20				data-lanes = <1 2 3 4>;
     21				remote-endpoint = <&max96712_out0>;
     22			};
     23		};
     24	};
     25};
     26
     27&csi42 {
     28	status = "okay";
     29
     30	ports {
     31		#address-cells = <1>;
     32		#size-cells = <0>;
     33
     34		port@0 {
     35			reg = <0>;
     36
     37			csi42_in: endpoint {
     38				clock-lanes = <0>;
     39				data-lanes = <1 2 3 4>;
     40				remote-endpoint = <&max96712_out1>;
     41			};
     42		};
     43	};
     44};
     45
     46&csi43 {
     47	status = "okay";
     48
     49	ports {
     50		#address-cells = <1>;
     51		#size-cells = <0>;
     52
     53		port@0 {
     54			reg = <0>;
     55
     56			csi43_in: endpoint {
     57				clock-lanes = <0>;
     58				data-lanes = <1 2 3 4>;
     59				remote-endpoint = <&max96712_out2>;
     60			};
     61		};
     62	};
     63};
     64
     65&i2c0 {
     66	pca9654_a: gpio@21 {
     67		compatible = "onnn,pca9654";
     68		reg = <0x21>;
     69		gpio-controller;
     70		#gpio-cells = <2>;
     71	};
     72
     73	pca9654_b: gpio@22 {
     74		compatible = "onnn,pca9654";
     75		reg = <0x22>;
     76		gpio-controller;
     77		#gpio-cells = <2>;
     78	};
     79
     80	pca9654_c: gpio@23 {
     81		compatible = "onnn,pca9654";
     82		reg = <0x23>;
     83		gpio-controller;
     84		#gpio-cells = <2>;
     85	};
     86
     87	eeprom@52 {
     88		compatible = "rohm,br24g01", "atmel,24c01";
     89		label = "csi-dsi-sub-board-id";
     90		reg = <0x52>;
     91		pagesize = <8>;
     92	};
     93};
     94
     95&i2c1 {
     96	gmsl0: gmsl-deserializer@49 {
     97		compatible = "maxim,max96712";
     98		reg = <0x49>;
     99		enable-gpios = <&pca9654_a 0 GPIO_ACTIVE_HIGH>;
    100
    101		ports {
    102			#address-cells = <1>;
    103			#size-cells = <0>;
    104
    105			port@4 {
    106				reg = <4>;
    107				max96712_out0: endpoint {
    108					clock-lanes = <0>;
    109					data-lanes = <1 2 3 4>;
    110					remote-endpoint = <&csi40_in>;
    111				};
    112			};
    113		};
    114	};
    115
    116	gmsl1: gmsl-deserializer@4b {
    117		compatible = "maxim,max96712";
    118		reg = <0x4b>;
    119		enable-gpios = <&pca9654_b 0 GPIO_ACTIVE_HIGH>;
    120
    121		ports {
    122			#address-cells = <1>;
    123			#size-cells = <0>;
    124
    125			port@4 {
    126				reg = <4>;
    127				max96712_out1: endpoint {
    128					clock-lanes = <0>;
    129					data-lanes = <1 2 3 4>;
    130					lane-polarities = <0 0 0 0 1>;
    131					remote-endpoint = <&csi42_in>;
    132				};
    133			};
    134		};
    135	};
    136
    137	gmsl2: gmsl-deserializer@6b {
    138		compatible = "maxim,max96712";
    139		reg = <0x6b>;
    140		enable-gpios = <&pca9654_c 0 GPIO_ACTIVE_HIGH>;
    141
    142		ports {
    143			#address-cells = <1>;
    144			#size-cells = <0>;
    145
    146			port@4 {
    147				reg = <4>;
    148				max96712_out2: endpoint {
    149					clock-lanes = <0>;
    150					data-lanes = <1 2 3 4>;
    151					lane-polarities = <0 0 0 0 1>;
    152					remote-endpoint = <&csi43_in>;
    153				};
    154			};
    155		};
    156	};
    157};
    158
    159&isp0 {
    160	status = "okay";
    161};
    162
    163&isp2 {
    164	status = "okay";
    165};
    166
    167&isp3 {
    168	status = "okay";
    169};
    170
    171&vin00 {
    172	status = "okay";
    173};
    174
    175&vin01 {
    176	status = "okay";
    177};
    178
    179&vin02 {
    180	status = "okay";
    181};
    182
    183&vin03 {
    184	status = "okay";
    185};
    186
    187&vin04 {
    188	status = "okay";
    189};
    190
    191&vin05 {
    192	status = "okay";
    193};
    194
    195&vin06 {
    196	status = "okay";
    197};
    198
    199&vin07 {
    200	status = "okay";
    201};
    202
    203&vin16 {
    204	status = "okay";
    205};
    206
    207&vin17 {
    208	status = "okay";
    209};
    210
    211&vin18 {
    212	status = "okay";
    213};
    214
    215&vin19 {
    216	status = "okay";
    217};
    218
    219&vin20 {
    220	status = "okay";
    221};
    222
    223&vin21 {
    224	status = "okay";
    225};
    226
    227&vin22 {
    228	status = "okay";
    229};
    230
    231&vin23 {
    232	status = "okay";
    233};
    234
    235&vin24 {
    236	status = "okay";
    237};
    238
    239&vin25 {
    240	status = "okay";
    241};
    242
    243&vin26 {
    244	status = "okay";
    245};
    246
    247&vin27 {
    248	status = "okay";
    249};
    250
    251&vin28 {
    252	status = "okay";
    253};
    254
    255&vin29 {
    256	status = "okay";
    257};
    258
    259&vin30 {
    260	status = "okay";
    261};
    262
    263&vin31 {
    264	status = "okay";
    265};