r8a779f0.dtsi (10962B)
1// SPDX-License-Identifier: (GPL-2.0 or MIT) 2/* 3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a779f0-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a779f0-sysc.h> 11 12/ { 13 compatible = "renesas,r8a779f0"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 a55_0: cpu@0 { 22 compatible = "arm,cortex-a55"; 23 reg = <0>; 24 device_type = "cpu"; 25 power-domains = <&sysc R8A779F0_PD_A1E0D0C0>; 26 }; 27 }; 28 29 extal_clk: extal { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 /* This value must be overridden by the board */ 33 clock-frequency = <0>; 34 }; 35 36 extalr_clk: extalr { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 /* This value must be overridden by the board */ 40 clock-frequency = <0>; 41 }; 42 43 pmu_a55 { 44 compatible = "arm,cortex-a55-pmu"; 45 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 46 }; 47 48 /* External SCIF clock - to be overridden by boards that provide it */ 49 scif_clk: scif { 50 compatible = "fixed-clock"; 51 #clock-cells = <0>; 52 clock-frequency = <0>; 53 }; 54 55 soc: soc { 56 compatible = "simple-bus"; 57 interrupt-parent = <&gic>; 58 #address-cells = <2>; 59 #size-cells = <2>; 60 ranges; 61 62 rwdt: watchdog@e6020000 { 63 compatible = "renesas,r8a779f0-wdt", 64 "renesas,rcar-gen4-wdt"; 65 reg = <0 0xe6020000 0 0x0c>; 66 interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>; 67 clocks = <&cpg CPG_MOD 907>; 68 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 69 resets = <&cpg 907>; 70 status = "disabled"; 71 }; 72 73 pfc: pinctrl@e6050000 { 74 compatible = "renesas,pfc-r8a779f0"; 75 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, 76 <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>; 77 }; 78 79 gpio0: gpio@e6050180 { 80 compatible = "renesas,gpio-r8a779f0", 81 "renesas,rcar-gen4-gpio"; 82 reg = <0 0xe6050180 0 0x54>; 83 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; 84 clocks = <&cpg CPG_MOD 915>; 85 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 86 resets = <&cpg 915>; 87 gpio-controller; 88 #gpio-cells = <2>; 89 gpio-ranges = <&pfc 0 0 21>; 90 interrupt-controller; 91 #interrupt-cells = <2>; 92 }; 93 94 gpio1: gpio@e6050980 { 95 compatible = "renesas,gpio-r8a779f0", 96 "renesas,rcar-gen4-gpio"; 97 reg = <0 0xe6050980 0 0x54>; 98 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; 99 clocks = <&cpg CPG_MOD 915>; 100 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 101 resets = <&cpg 915>; 102 gpio-controller; 103 #gpio-cells = <2>; 104 gpio-ranges = <&pfc 0 32 25>; 105 interrupt-controller; 106 #interrupt-cells = <2>; 107 }; 108 109 gpio2: gpio@e6051180 { 110 compatible = "renesas,gpio-r8a779f0", 111 "renesas,rcar-gen4-gpio"; 112 reg = <0 0xe6051180 0 0x54>; 113 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; 114 clocks = <&cpg CPG_MOD 915>; 115 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 116 resets = <&cpg 915>; 117 gpio-controller; 118 #gpio-cells = <2>; 119 gpio-ranges = <&pfc 0 64 17>; 120 interrupt-controller; 121 #interrupt-cells = <2>; 122 }; 123 124 gpio3: gpio@e6051980 { 125 compatible = "renesas,gpio-r8a779f0", 126 "renesas,rcar-gen4-gpio"; 127 reg = <0 0xe6051980 0 0x54>; 128 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; 129 clocks = <&cpg CPG_MOD 915>; 130 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 131 resets = <&cpg 915>; 132 gpio-controller; 133 #gpio-cells = <2>; 134 gpio-ranges = <&pfc 0 96 19>; 135 interrupt-controller; 136 #interrupt-cells = <2>; 137 }; 138 139 cpg: clock-controller@e6150000 { 140 compatible = "renesas,r8a779f0-cpg-mssr"; 141 reg = <0 0xe6150000 0 0x4000>; 142 clocks = <&extal_clk>, <&extalr_clk>; 143 clock-names = "extal", "extalr"; 144 #clock-cells = <2>; 145 #power-domain-cells = <0>; 146 #reset-cells = <1>; 147 }; 148 149 rst: reset-controller@e6160000 { 150 compatible = "renesas,r8a779f0-rst"; 151 reg = <0 0xe6160000 0 0x4000>; 152 }; 153 154 sysc: system-controller@e6180000 { 155 compatible = "renesas,r8a779f0-sysc"; 156 reg = <0 0xe6180000 0 0x4000>; 157 #power-domain-cells = <1>; 158 }; 159 160 i2c0: i2c@e6500000 { 161 compatible = "renesas,i2c-r8a779f0", 162 "renesas,rcar-gen4-i2c"; 163 reg = <0 0xe6500000 0 0x40>; 164 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 165 clocks = <&cpg CPG_MOD 518>; 166 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 167 resets = <&cpg 518>; 168 dmas = <&dmac0 0x91>, <&dmac0 0x90>, 169 <&dmac1 0x91>, <&dmac1 0x90>; 170 dma-names = "tx", "rx", "tx", "rx"; 171 i2c-scl-internal-delay-ns = <110>; 172 #address-cells = <1>; 173 #size-cells = <0>; 174 status = "disabled"; 175 }; 176 177 i2c1: i2c@e6508000 { 178 compatible = "renesas,i2c-r8a779f0", 179 "renesas,rcar-gen4-i2c"; 180 reg = <0 0xe6508000 0 0x40>; 181 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 182 clocks = <&cpg CPG_MOD 519>; 183 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 184 resets = <&cpg 519>; 185 dmas = <&dmac0 0x93>, <&dmac0 0x92>, 186 <&dmac1 0x93>, <&dmac1 0x92>; 187 dma-names = "tx", "rx", "tx", "rx"; 188 i2c-scl-internal-delay-ns = <110>; 189 #address-cells = <1>; 190 #size-cells = <0>; 191 status = "disabled"; 192 }; 193 194 i2c2: i2c@e6510000 { 195 compatible = "renesas,i2c-r8a779f0", 196 "renesas,rcar-gen4-i2c"; 197 reg = <0 0xe6510000 0 0x40>; 198 interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>; 199 clocks = <&cpg CPG_MOD 520>; 200 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 201 resets = <&cpg 520>; 202 dmas = <&dmac0 0x95>, <&dmac0 0x94>, 203 <&dmac1 0x95>, <&dmac1 0x94>; 204 dma-names = "tx", "rx", "tx", "rx"; 205 i2c-scl-internal-delay-ns = <110>; 206 #address-cells = <1>; 207 #size-cells = <0>; 208 status = "disabled"; 209 }; 210 211 i2c3: i2c@e66d0000 { 212 compatible = "renesas,i2c-r8a779f0", 213 "renesas,rcar-gen4-i2c"; 214 reg = <0 0xe66d0000 0 0x40>; 215 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&cpg CPG_MOD 521>; 217 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 218 resets = <&cpg 521>; 219 dmas = <&dmac0 0x97>, <&dmac0 0x96>, 220 <&dmac1 0x97>, <&dmac1 0x96>; 221 dma-names = "tx", "rx", "tx", "rx"; 222 i2c-scl-internal-delay-ns = <110>; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 status = "disabled"; 226 }; 227 228 i2c4: i2c@e66d8000 { 229 compatible = "renesas,i2c-r8a779f0", 230 "renesas,rcar-gen4-i2c"; 231 reg = <0 0xe66d8000 0 0x40>; 232 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 233 clocks = <&cpg CPG_MOD 522>; 234 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 235 resets = <&cpg 522>; 236 dmas = <&dmac0 0x99>, <&dmac0 0x98>, 237 <&dmac1 0x99>, <&dmac1 0x98>; 238 dma-names = "tx", "rx", "tx", "rx"; 239 i2c-scl-internal-delay-ns = <110>; 240 #address-cells = <1>; 241 #size-cells = <0>; 242 status = "disabled"; 243 }; 244 245 i2c5: i2c@e66e0000 { 246 compatible = "renesas,i2c-r8a779f0", 247 "renesas,rcar-gen4-i2c"; 248 reg = <0 0xe66e0000 0 0x40>; 249 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&cpg CPG_MOD 523>; 251 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 252 resets = <&cpg 523>; 253 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>, 254 <&dmac1 0x9b>, <&dmac1 0x9a>; 255 dma-names = "tx", "rx", "tx", "rx"; 256 i2c-scl-internal-delay-ns = <110>; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 status = "disabled"; 260 }; 261 262 scif3: serial@e6c50000 { 263 compatible = "renesas,scif-r8a779f0", 264 "renesas,rcar-gen4-scif", "renesas,scif"; 265 reg = <0 0xe6c50000 0 64>; 266 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&cpg CPG_MOD 704>, 268 <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>, 269 <&scif_clk>; 270 clock-names = "fck", "brg_int", "scif_clk"; 271 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 272 resets = <&cpg 704>; 273 status = "disabled"; 274 }; 275 276 dmac0: dma-controller@e7350000 { 277 compatible = "renesas,dmac-r8a779f0", 278 "renesas,rcar-gen4-dmac"; 279 reg = <0 0xe7350000 0 0x1000>, 280 <0 0xe7300000 0 0x10000>; 281 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 298 interrupt-names = "error", 299 "ch0", "ch1", "ch2", "ch3", "ch4", 300 "ch5", "ch6", "ch7", "ch8", "ch9", 301 "ch10", "ch11", "ch12", "ch13", 302 "ch14", "ch15"; 303 clocks = <&cpg CPG_MOD 709>; 304 clock-names = "fck"; 305 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 306 resets = <&cpg 709>; 307 #dma-cells = <1>; 308 dma-channels = <16>; 309 }; 310 311 dmac1: dma-controller@e7351000 { 312 compatible = "renesas,dmac-r8a779f0", 313 "renesas,rcar-gen4-dmac"; 314 reg = <0 0xe7351000 0 0x1000>, 315 <0 0xe7310000 0 0x10000>; 316 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 333 interrupt-names = "error", 334 "ch0", "ch1", "ch2", "ch3", "ch4", 335 "ch5", "ch6", "ch7", "ch8", "ch9", 336 "ch10", "ch11", "ch12", "ch13", 337 "ch14", "ch15"; 338 clocks = <&cpg CPG_MOD 710>; 339 clock-names = "fck"; 340 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 341 resets = <&cpg 710>; 342 #dma-cells = <1>; 343 dma-channels = <16>; 344 }; 345 346 gic: interrupt-controller@f1000000 { 347 compatible = "arm,gic-v3"; 348 #interrupt-cells = <3>; 349 #address-cells = <0>; 350 interrupt-controller; 351 reg = <0x0 0xf1000000 0 0x20000>, 352 <0x0 0xf1060000 0 0x110000>; 353 interrupts = <GIC_PPI 9 354 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 355 }; 356 357 prr: chipid@fff00044 { 358 compatible = "renesas,prr"; 359 reg = <0 0xfff00044 0 4>; 360 }; 361 }; 362 363 timer { 364 compatible = "arm,armv8-timer"; 365 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 366 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 367 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 368 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 369 }; 370};