cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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r8a779m1-ulcb.dts (1197B)

      1// SPDX-License-Identifier: (GPL-2.0 or MIT)
      2/*
      3 * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) with R-Car H3e-2G
      4 *
      5 * Copyright (C) 2021 Glider bv
      6 *
      7 * Based on r8a77951-ulcb.dts
      8 *
      9 * Copyright (C) 2016 Renesas Electronics Corp.
     10 * Copyright (C) 2016 Cogent Embedded, Inc.
     11 */
     12
     13/dts-v1/;
     14#include "r8a779m1.dtsi"
     15#include "ulcb.dtsi"
     16
     17/ {
     18	model = "Renesas H3ULCB board based on r8a779m1";
     19	compatible = "renesas,h3ulcb", "renesas,r8a779m1", "renesas,r8a7795";
     20
     21	memory@48000000 {
     22		device_type = "memory";
     23		/* first 128MB is reserved for secure area. */
     24		reg = <0x0 0x48000000 0x0 0x38000000>;
     25	};
     26
     27	memory@500000000 {
     28		device_type = "memory";
     29		reg = <0x5 0x00000000 0x0 0x40000000>;
     30	};
     31
     32	memory@600000000 {
     33		device_type = "memory";
     34		reg = <0x6 0x00000000 0x0 0x40000000>;
     35	};
     36
     37	memory@700000000 {
     38		device_type = "memory";
     39		reg = <0x7 0x00000000 0x0 0x40000000>;
     40	};
     41};
     42
     43&du {
     44	clocks = <&cpg CPG_MOD 724>,
     45		 <&cpg CPG_MOD 723>,
     46		 <&cpg CPG_MOD 722>,
     47		 <&cpg CPG_MOD 721>,
     48		 <&versaclock5 1>,
     49		 <&versaclock5 3>,
     50		 <&versaclock5 4>,
     51		 <&versaclock5 2>;
     52	clock-names = "du.0", "du.1", "du.2", "du.3",
     53		      "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
     54};