cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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r9a07g044.dtsi (30712B)


      1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2/*
      3 * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
      4 *
      5 * Copyright (C) 2021 Renesas Electronics Corp.
      6 */
      7
      8#include <dt-bindings/interrupt-controller/arm-gic.h>
      9#include <dt-bindings/clock/r9a07g044-cpg.h>
     10
     11/ {
     12	compatible = "renesas,r9a07g044";
     13	#address-cells = <2>;
     14	#size-cells = <2>;
     15
     16	audio_clk1: audio1-clk {
     17		compatible = "fixed-clock";
     18		#clock-cells = <0>;
     19		/* This value must be overridden by boards that provide it */
     20		clock-frequency = <0>;
     21	};
     22
     23	audio_clk2: audio2-clk {
     24		compatible = "fixed-clock";
     25		#clock-cells = <0>;
     26		/* This value must be overridden by boards that provide it */
     27		clock-frequency = <0>;
     28	};
     29
     30	/* External CAN clock - to be overridden by boards that provide it */
     31	can_clk: can-clk {
     32		compatible = "fixed-clock";
     33		#clock-cells = <0>;
     34		clock-frequency = <0>;
     35	};
     36
     37	/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
     38	extal_clk: extal-clk {
     39		compatible = "fixed-clock";
     40		#clock-cells = <0>;
     41		/* This value must be overridden by the board */
     42		clock-frequency = <0>;
     43	};
     44
     45	cluster0_opp: opp-table-0 {
     46		compatible = "operating-points-v2";
     47		opp-shared;
     48
     49		opp-150000000 {
     50			opp-hz = /bits/ 64 <150000000>;
     51			opp-microvolt = <1100000>;
     52			clock-latency-ns = <300000>;
     53		};
     54		opp-300000000 {
     55			opp-hz = /bits/ 64 <300000000>;
     56			opp-microvolt = <1100000>;
     57			clock-latency-ns = <300000>;
     58		};
     59		opp-600000000 {
     60			opp-hz = /bits/ 64 <600000000>;
     61			opp-microvolt = <1100000>;
     62			clock-latency-ns = <300000>;
     63		};
     64		opp-1200000000 {
     65			opp-hz = /bits/ 64 <1200000000>;
     66			opp-microvolt = <1100000>;
     67			clock-latency-ns = <300000>;
     68			opp-suspend;
     69		};
     70	};
     71
     72	cpus {
     73		#address-cells = <1>;
     74		#size-cells = <0>;
     75
     76		cpu-map {
     77			cluster0 {
     78				core0 {
     79					cpu = <&cpu0>;
     80				};
     81				core1 {
     82					cpu = <&cpu1>;
     83				};
     84			};
     85		};
     86
     87		cpu0: cpu@0 {
     88			compatible = "arm,cortex-a55";
     89			reg = <0>;
     90			device_type = "cpu";
     91			#cooling-cells = <2>;
     92			next-level-cache = <&L3_CA55>;
     93			enable-method = "psci";
     94			clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
     95			operating-points-v2 = <&cluster0_opp>;
     96		};
     97
     98		cpu1: cpu@100 {
     99			compatible = "arm,cortex-a55";
    100			reg = <0x100>;
    101			device_type = "cpu";
    102			next-level-cache = <&L3_CA55>;
    103			enable-method = "psci";
    104			clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
    105			operating-points-v2 = <&cluster0_opp>;
    106		};
    107
    108		L3_CA55: cache-controller-0 {
    109			compatible = "cache";
    110			cache-unified;
    111			cache-size = <0x40000>;
    112		};
    113	};
    114
    115	gpu_opp_table: opp-table-1 {
    116		compatible = "operating-points-v2";
    117
    118		opp-500000000 {
    119			opp-hz = /bits/ 64 <500000000>;
    120			opp-microvolt = <1100000>;
    121		};
    122
    123		opp-400000000 {
    124			opp-hz = /bits/ 64 <400000000>;
    125			opp-microvolt = <1100000>;
    126		};
    127
    128		opp-250000000 {
    129			opp-hz = /bits/ 64 <250000000>;
    130			opp-microvolt = <1100000>;
    131		};
    132
    133		opp-200000000 {
    134			opp-hz = /bits/ 64 <200000000>;
    135			opp-microvolt = <1100000>;
    136		};
    137
    138		opp-125000000 {
    139			opp-hz = /bits/ 64 <125000000>;
    140			opp-microvolt = <1100000>;
    141		};
    142
    143		opp-100000000 {
    144			opp-hz = /bits/ 64 <100000000>;
    145			opp-microvolt = <1100000>;
    146		};
    147
    148		opp-62500000 {
    149			opp-hz = /bits/ 64 <62500000>;
    150			opp-microvolt = <1100000>;
    151		};
    152
    153		opp-50000000 {
    154			opp-hz = /bits/ 64 <50000000>;
    155			opp-microvolt = <1100000>;
    156		};
    157	};
    158
    159	psci {
    160		compatible = "arm,psci-1.0", "arm,psci-0.2";
    161		method = "smc";
    162	};
    163
    164	soc: soc {
    165		compatible = "simple-bus";
    166		interrupt-parent = <&gic>;
    167		#address-cells = <2>;
    168		#size-cells = <2>;
    169		ranges;
    170
    171		ssi0: ssi@10049c00 {
    172			compatible = "renesas,r9a07g044-ssi",
    173				     "renesas,rz-ssi";
    174			reg = <0 0x10049c00 0 0x400>;
    175			interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
    176				     <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
    177				     <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
    178				     <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
    179			interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
    180			clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
    181				 <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
    182				 <&audio_clk1>, <&audio_clk2>;
    183			clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
    184			resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
    185			dmas = <&dmac 0x2655>, <&dmac 0x2656>;
    186			dma-names = "tx", "rx";
    187			power-domains = <&cpg>;
    188			#sound-dai-cells = <0>;
    189			status = "disabled";
    190		};
    191
    192		ssi1: ssi@1004a000 {
    193			compatible = "renesas,r9a07g044-ssi",
    194				     "renesas,rz-ssi";
    195			reg = <0 0x1004a000 0 0x400>;
    196			interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
    197				     <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
    198				     <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
    199				     <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>;
    200			interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
    201			clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>,
    202				 <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>,
    203				 <&audio_clk1>, <&audio_clk2>;
    204			clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
    205			resets = <&cpg R9A07G044_SSI1_RST_M2_REG>;
    206			dmas = <&dmac 0x2659>, <&dmac 0x265a>;
    207			dma-names = "tx", "rx";
    208			power-domains = <&cpg>;
    209			#sound-dai-cells = <0>;
    210			status = "disabled";
    211		};
    212
    213		ssi2: ssi@1004a400 {
    214			compatible = "renesas,r9a07g044-ssi",
    215				     "renesas,rz-ssi";
    216			reg = <0 0x1004a400 0 0x400>;
    217			interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
    218				     <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>,
    219				     <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
    220				     <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
    221			interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
    222			clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>,
    223				 <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>,
    224				 <&audio_clk1>, <&audio_clk2>;
    225			clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
    226			resets = <&cpg R9A07G044_SSI2_RST_M2_REG>;
    227			dmas = <&dmac 0x265f>;
    228			dma-names = "rt";
    229			power-domains = <&cpg>;
    230			#sound-dai-cells = <0>;
    231			status = "disabled";
    232		};
    233
    234		ssi3: ssi@1004a800 {
    235			compatible = "renesas,r9a07g044-ssi",
    236				     "renesas,rz-ssi";
    237			reg = <0 0x1004a800 0 0x400>;
    238			interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
    239				     <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
    240				     <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>,
    241				     <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>;
    242			interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
    243			clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>,
    244				 <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>,
    245				 <&audio_clk1>, <&audio_clk2>;
    246			clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
    247			resets = <&cpg R9A07G044_SSI3_RST_M2_REG>;
    248			dmas = <&dmac 0x2661>, <&dmac 0x2662>;
    249			dma-names = "tx", "rx";
    250			power-domains = <&cpg>;
    251			#sound-dai-cells = <0>;
    252			status = "disabled";
    253		};
    254
    255		spi0: spi@1004ac00 {
    256			compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
    257			reg = <0 0x1004ac00 0 0x400>;
    258			interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
    259				     <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
    260				     <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
    261			interrupt-names = "error", "rx", "tx";
    262			clocks = <&cpg CPG_MOD R9A07G044_RSPI0_CLKB>;
    263			resets = <&cpg R9A07G044_RSPI0_RST>;
    264			power-domains = <&cpg>;
    265			num-cs = <1>;
    266			#address-cells = <1>;
    267			#size-cells = <0>;
    268			status = "disabled";
    269		};
    270
    271		spi1: spi@1004b000 {
    272			compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
    273			reg = <0 0x1004b000 0 0x400>;
    274			interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
    275				     <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
    276				     <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
    277			interrupt-names = "error", "rx", "tx";
    278			clocks = <&cpg CPG_MOD R9A07G044_RSPI1_CLKB>;
    279			resets = <&cpg R9A07G044_RSPI1_RST>;
    280			power-domains = <&cpg>;
    281			num-cs = <1>;
    282			#address-cells = <1>;
    283			#size-cells = <0>;
    284			status = "disabled";
    285		};
    286
    287		spi2: spi@1004b400 {
    288			compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
    289			reg = <0 0x1004b400 0 0x400>;
    290			interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
    291				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
    292				     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
    293			interrupt-names = "error", "rx", "tx";
    294			clocks = <&cpg CPG_MOD R9A07G044_RSPI2_CLKB>;
    295			resets = <&cpg R9A07G044_RSPI2_RST>;
    296			power-domains = <&cpg>;
    297			num-cs = <1>;
    298			#address-cells = <1>;
    299			#size-cells = <0>;
    300			status = "disabled";
    301		};
    302
    303		scif0: serial@1004b800 {
    304			compatible = "renesas,scif-r9a07g044";
    305			reg = <0 0x1004b800 0 0x400>;
    306			interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
    307				     <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
    308				     <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
    309				     <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
    310				     <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
    311				     <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
    312			interrupt-names = "eri", "rxi", "txi",
    313					  "bri", "dri", "tei";
    314			clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>;
    315			clock-names = "fck";
    316			power-domains = <&cpg>;
    317			resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>;
    318			status = "disabled";
    319		};
    320
    321		scif1: serial@1004bc00 {
    322			compatible = "renesas,scif-r9a07g044";
    323			reg = <0 0x1004bc00 0 0x400>;
    324			interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
    325				     <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
    326				     <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
    327				     <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
    328				     <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
    329				     <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
    330			interrupt-names = "eri", "rxi", "txi",
    331					  "bri", "dri", "tei";
    332			clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>;
    333			clock-names = "fck";
    334			power-domains = <&cpg>;
    335			resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>;
    336			status = "disabled";
    337		};
    338
    339		scif2: serial@1004c000 {
    340			compatible = "renesas,scif-r9a07g044";
    341			reg = <0 0x1004c000 0 0x400>;
    342			interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
    343				     <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
    344				     <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
    345				     <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
    346				     <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
    347				     <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
    348			interrupt-names = "eri", "rxi", "txi",
    349					  "bri", "dri", "tei";
    350			clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>;
    351			clock-names = "fck";
    352			power-domains = <&cpg>;
    353			resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>;
    354			status = "disabled";
    355		};
    356
    357		scif3: serial@1004c400 {
    358			compatible = "renesas,scif-r9a07g044";
    359			reg = <0 0x1004c400 0 0x400>;
    360			interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
    361				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
    362				     <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
    363				     <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
    364				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
    365				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
    366			interrupt-names = "eri", "rxi", "txi",
    367					  "bri", "dri", "tei";
    368			clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>;
    369			clock-names = "fck";
    370			power-domains = <&cpg>;
    371			resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>;
    372			status = "disabled";
    373		};
    374
    375		scif4: serial@1004c800 {
    376			compatible = "renesas,scif-r9a07g044";
    377			reg = <0 0x1004c800 0 0x400>;
    378			interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
    379				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
    380				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
    381				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
    382				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
    383				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
    384			interrupt-names = "eri", "rxi", "txi",
    385					  "bri", "dri", "tei";
    386			clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>;
    387			clock-names = "fck";
    388			power-domains = <&cpg>;
    389			resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>;
    390			status = "disabled";
    391		};
    392
    393		sci0: serial@1004d000 {
    394			compatible = "renesas,r9a07g044-sci", "renesas,sci";
    395			reg = <0 0x1004d000 0 0x400>;
    396			interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
    397				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
    398				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
    399				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
    400			interrupt-names = "eri", "rxi", "txi", "tei";
    401			clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>;
    402			clock-names = "fck";
    403			power-domains = <&cpg>;
    404			resets = <&cpg R9A07G044_SCI0_RST>;
    405			status = "disabled";
    406		};
    407
    408		sci1: serial@1004d400 {
    409			compatible = "renesas,r9a07g044-sci", "renesas,sci";
    410			reg = <0 0x1004d400 0 0x400>;
    411			interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
    412				     <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
    413				     <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
    414				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
    415			interrupt-names = "eri", "rxi", "txi", "tei";
    416			clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>;
    417			clock-names = "fck";
    418			power-domains = <&cpg>;
    419			resets = <&cpg R9A07G044_SCI1_RST>;
    420			status = "disabled";
    421		};
    422
    423		canfd: can@10050000 {
    424			compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";
    425			reg = <0 0x10050000 0 0x8000>;
    426			interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
    427				     <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
    428				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
    429				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
    430				     <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
    431				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
    432				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
    433				     <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
    434			interrupt-names = "g_err", "g_recc",
    435					  "ch0_err", "ch0_rec", "ch0_trx",
    436					  "ch1_err", "ch1_rec", "ch1_trx";
    437			clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
    438				 <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
    439				 <&can_clk>;
    440			clock-names = "fck", "canfd", "can_clk";
    441			assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
    442			assigned-clock-rates = <50000000>;
    443			resets = <&cpg R9A07G044_CANFD_RSTP_N>,
    444				 <&cpg R9A07G044_CANFD_RSTC_N>;
    445			reset-names = "rstp_n", "rstc_n";
    446			power-domains = <&cpg>;
    447			status = "disabled";
    448
    449			channel0 {
    450				status = "disabled";
    451			};
    452			channel1 {
    453				status = "disabled";
    454			};
    455		};
    456
    457		i2c0: i2c@10058000 {
    458			#address-cells = <1>;
    459			#size-cells = <0>;
    460			compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
    461			reg = <0 0x10058000 0 0x400>;
    462			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
    463				     <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
    464				     <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
    465				     <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
    466				     <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
    467				     <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
    468				     <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
    469				     <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
    470			interrupt-names = "tei", "ri", "ti", "spi", "sti",
    471					  "naki", "ali", "tmoi";
    472			clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>;
    473			clock-frequency = <100000>;
    474			resets = <&cpg R9A07G044_I2C0_MRST>;
    475			power-domains = <&cpg>;
    476			status = "disabled";
    477		};
    478
    479		i2c1: i2c@10058400 {
    480			#address-cells = <1>;
    481			#size-cells = <0>;
    482			compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
    483			reg = <0 0x10058400 0 0x400>;
    484			interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
    485				     <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
    486				     <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
    487				     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
    488				     <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
    489				     <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
    490				     <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
    491				     <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
    492			interrupt-names = "tei", "ri", "ti", "spi", "sti",
    493					  "naki", "ali", "tmoi";
    494			clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>;
    495			clock-frequency = <100000>;
    496			resets = <&cpg R9A07G044_I2C1_MRST>;
    497			power-domains = <&cpg>;
    498			status = "disabled";
    499		};
    500
    501		i2c2: i2c@10058800 {
    502			#address-cells = <1>;
    503			#size-cells = <0>;
    504			compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
    505			reg = <0 0x10058800 0 0x400>;
    506			interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
    507				     <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
    508				     <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
    509				     <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
    510				     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
    511				     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
    512				     <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
    513				     <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
    514			interrupt-names = "tei", "ri", "ti", "spi", "sti",
    515					  "naki", "ali", "tmoi";
    516			clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>;
    517			clock-frequency = <100000>;
    518			resets = <&cpg R9A07G044_I2C2_MRST>;
    519			power-domains = <&cpg>;
    520			status = "disabled";
    521		};
    522
    523		i2c3: i2c@10058c00 {
    524			#address-cells = <1>;
    525			#size-cells = <0>;
    526			compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
    527			reg = <0 0x10058c00 0 0x400>;
    528			interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
    529				     <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
    530				     <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
    531				     <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
    532				     <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
    533				     <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
    534				     <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
    535				     <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
    536			interrupt-names = "tei", "ri", "ti", "spi", "sti",
    537					  "naki", "ali", "tmoi";
    538			clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>;
    539			clock-frequency = <100000>;
    540			resets = <&cpg R9A07G044_I2C3_MRST>;
    541			power-domains = <&cpg>;
    542			status = "disabled";
    543		};
    544
    545		adc: adc@10059000 {
    546			compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
    547			reg = <0 0x10059000 0 0x400>;
    548			interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
    549			clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
    550				 <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
    551			clock-names = "adclk", "pclk";
    552			resets = <&cpg R9A07G044_ADC_PRESETN>,
    553				 <&cpg R9A07G044_ADC_ADRST_N>;
    554			reset-names = "presetn", "adrst-n";
    555			power-domains = <&cpg>;
    556			status = "disabled";
    557
    558			#address-cells = <1>;
    559			#size-cells = <0>;
    560
    561			channel@0 {
    562				reg = <0>;
    563			};
    564			channel@1 {
    565				reg = <1>;
    566			};
    567			channel@2 {
    568				reg = <2>;
    569			};
    570			channel@3 {
    571				reg = <3>;
    572			};
    573			channel@4 {
    574				reg = <4>;
    575			};
    576			channel@5 {
    577				reg = <5>;
    578			};
    579			channel@6 {
    580				reg = <6>;
    581			};
    582			channel@7 {
    583				reg = <7>;
    584			};
    585		};
    586
    587		tsu: thermal@10059400 {
    588			compatible = "renesas,r9a07g044-tsu",
    589				     "renesas,rzg2l-tsu";
    590			reg = <0 0x10059400 0 0x400>;
    591			clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>;
    592			resets = <&cpg R9A07G044_TSU_PRESETN>;
    593			power-domains = <&cpg>;
    594			#thermal-sensor-cells = <1>;
    595		};
    596
    597		sbc: spi@10060000 {
    598			compatible = "renesas,r9a07g044-rpc-if",
    599				     "renesas,rzg2l-rpc-if";
    600			reg = <0 0x10060000 0 0x10000>,
    601			      <0 0x20000000 0 0x10000000>,
    602			      <0 0x10070000 0 0x10000>;
    603			reg-names = "regs", "dirmap", "wbuf";
    604			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
    605			clocks = <&cpg CPG_MOD R9A07G044_SPI_CLK2>,
    606				 <&cpg CPG_MOD R9A07G044_SPI_CLK>;
    607			resets = <&cpg R9A07G044_SPI_RST>;
    608			power-domains = <&cpg>;
    609			#address-cells = <1>;
    610			#size-cells = <0>;
    611			status = "disabled";
    612		};
    613
    614		cpg: clock-controller@11010000 {
    615			compatible = "renesas,r9a07g044-cpg";
    616			reg = <0 0x11010000 0 0x10000>;
    617			clocks = <&extal_clk>;
    618			clock-names = "extal";
    619			#clock-cells = <2>;
    620			#reset-cells = <1>;
    621			#power-domain-cells = <0>;
    622		};
    623
    624		sysc: system-controller@11020000 {
    625			compatible = "renesas,r9a07g044-sysc";
    626			reg = <0 0x11020000 0 0x10000>;
    627			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
    628				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
    629				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
    630				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
    631			interrupt-names = "lpm_int", "ca55stbydone_int",
    632					  "cm33stbyr_int", "ca55_deny";
    633			status = "disabled";
    634		};
    635
    636		pinctrl: pinctrl@11030000 {
    637			compatible = "renesas,r9a07g044-pinctrl";
    638			reg = <0 0x11030000 0 0x10000>;
    639			gpio-controller;
    640			#gpio-cells = <2>;
    641			gpio-ranges = <&pinctrl 0 0 392>;
    642			clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
    643			power-domains = <&cpg>;
    644			resets = <&cpg R9A07G044_GPIO_RSTN>,
    645				 <&cpg R9A07G044_GPIO_PORT_RESETN>,
    646				 <&cpg R9A07G044_GPIO_SPARE_RESETN>;
    647		};
    648
    649		dmac: dma-controller@11820000 {
    650			compatible = "renesas,r9a07g044-dmac",
    651				     "renesas,rz-dmac";
    652			reg = <0 0x11820000 0 0x10000>,
    653			      <0 0x11830000 0 0x10000>;
    654			interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
    655				     <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
    656				     <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
    657				     <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
    658				     <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
    659				     <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
    660				     <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
    661				     <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
    662				     <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
    663				     <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
    664				     <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
    665				     <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
    666				     <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
    667				     <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
    668				     <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
    669				     <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
    670				     <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
    671			interrupt-names = "error",
    672					  "ch0", "ch1", "ch2", "ch3",
    673					  "ch4", "ch5", "ch6", "ch7",
    674					  "ch8", "ch9", "ch10", "ch11",
    675					  "ch12", "ch13", "ch14", "ch15";
    676			clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
    677				 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
    678			power-domains = <&cpg>;
    679			resets = <&cpg R9A07G044_DMAC_ARESETN>,
    680				 <&cpg R9A07G044_DMAC_RST_ASYNC>;
    681			#dma-cells = <1>;
    682			dma-channels = <16>;
    683		};
    684
    685		gpu: gpu@11840000 {
    686			compatible = "renesas,r9a07g044-mali",
    687				     "arm,mali-bifrost";
    688			reg = <0x0 0x11840000 0x0 0x10000>;
    689			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
    690				     <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
    691				     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
    692				     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
    693			interrupt-names = "job", "mmu", "gpu", "event";
    694			clocks = <&cpg CPG_MOD R9A07G044_GPU_CLK>,
    695				 <&cpg CPG_MOD R9A07G044_GPU_AXI_CLK>,
    696				 <&cpg CPG_MOD R9A07G044_GPU_ACE_CLK>;
    697			clock-names = "gpu", "bus", "bus_ace";
    698			power-domains = <&cpg>;
    699			resets = <&cpg R9A07G044_GPU_RESETN>,
    700				 <&cpg R9A07G044_GPU_AXI_RESETN>,
    701				 <&cpg R9A07G044_GPU_ACE_RESETN>;
    702			reset-names = "rst", "axi_rst", "ace_rst";
    703			operating-points-v2 = <&gpu_opp_table>;
    704		};
    705
    706		gic: interrupt-controller@11900000 {
    707			compatible = "arm,gic-v3";
    708			#interrupt-cells = <3>;
    709			#address-cells = <0>;
    710			interrupt-controller;
    711			reg = <0x0 0x11900000 0 0x40000>,
    712			      <0x0 0x11940000 0 0x60000>;
    713			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
    714		};
    715
    716		sdhi0: mmc@11c00000  {
    717			compatible = "renesas,sdhi-r9a07g044",
    718				     "renesas,rcar-gen3-sdhi";
    719			reg = <0x0 0x11c00000 0 0x10000>;
    720			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
    721				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
    722			clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>,
    723				 <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>,
    724				 <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
    725				 <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>;
    726			clock-names = "core", "clkh", "cd", "aclk";
    727			resets = <&cpg R9A07G044_SDHI0_IXRST>;
    728			power-domains = <&cpg>;
    729			status = "disabled";
    730		};
    731
    732		sdhi1: mmc@11c10000 {
    733			compatible = "renesas,sdhi-r9a07g044",
    734				     "renesas,rcar-gen3-sdhi";
    735			reg = <0x0 0x11c10000 0 0x10000>;
    736			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
    737				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
    738			clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>,
    739				 <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>,
    740				 <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
    741				 <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>;
    742			clock-names = "core", "clkh", "cd", "aclk";
    743			resets = <&cpg R9A07G044_SDHI1_IXRST>;
    744			power-domains = <&cpg>;
    745			status = "disabled";
    746		};
    747
    748		eth0: ethernet@11c20000 {
    749			compatible = "renesas,r9a07g044-gbeth",
    750				     "renesas,rzg2l-gbeth";
    751			reg = <0 0x11c20000 0 0x10000>;
    752			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
    753				     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
    754				     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
    755			interrupt-names = "mux", "fil", "arp_ns";
    756			phy-mode = "rgmii";
    757			clocks = <&cpg CPG_MOD R9A07G044_ETH0_CLK_AXI>,
    758				 <&cpg CPG_MOD R9A07G044_ETH0_CLK_CHI>,
    759				 <&cpg CPG_CORE R9A07G044_CLK_HP>;
    760			clock-names = "axi", "chi", "refclk";
    761			resets = <&cpg R9A07G044_ETH0_RST_HW_N>;
    762			power-domains = <&cpg>;
    763			#address-cells = <1>;
    764			#size-cells = <0>;
    765			status = "disabled";
    766		};
    767
    768		eth1: ethernet@11c30000 {
    769			compatible = "renesas,r9a07g044-gbeth",
    770				     "renesas,rzg2l-gbeth";
    771			reg = <0 0x11c30000 0 0x10000>;
    772			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
    773				     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
    774				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
    775			interrupt-names = "mux", "fil", "arp_ns";
    776			phy-mode = "rgmii";
    777			clocks = <&cpg CPG_MOD R9A07G044_ETH1_CLK_AXI>,
    778				 <&cpg CPG_MOD R9A07G044_ETH1_CLK_CHI>,
    779				 <&cpg CPG_CORE R9A07G044_CLK_HP>;
    780			clock-names = "axi", "chi", "refclk";
    781			resets = <&cpg R9A07G044_ETH1_RST_HW_N>;
    782			power-domains = <&cpg>;
    783			#address-cells = <1>;
    784			#size-cells = <0>;
    785			status = "disabled";
    786		};
    787
    788		phyrst: usbphy-ctrl@11c40000 {
    789			compatible = "renesas,r9a07g044-usbphy-ctrl",
    790				     "renesas,rzg2l-usbphy-ctrl";
    791			reg = <0 0x11c40000 0 0x10000>;
    792			clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
    793			resets = <&cpg R9A07G044_USB_PRESETN>;
    794			power-domains = <&cpg>;
    795			#reset-cells = <1>;
    796			status = "disabled";
    797		};
    798
    799		ohci0: usb@11c50000 {
    800			compatible = "generic-ohci";
    801			reg = <0 0x11c50000 0 0x100>;
    802			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
    803			clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
    804				 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
    805			resets = <&phyrst 0>,
    806				 <&cpg R9A07G044_USB_U2H0_HRESETN>;
    807			phys = <&usb2_phy0 1>;
    808			phy-names = "usb";
    809			power-domains = <&cpg>;
    810			status = "disabled";
    811		};
    812
    813		ohci1: usb@11c70000 {
    814			compatible = "generic-ohci";
    815			reg = <0 0x11c70000 0 0x100>;
    816			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
    817			clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
    818				 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
    819			resets = <&phyrst 1>,
    820				 <&cpg R9A07G044_USB_U2H1_HRESETN>;
    821			phys = <&usb2_phy1 1>;
    822			phy-names = "usb";
    823			power-domains = <&cpg>;
    824			status = "disabled";
    825		};
    826
    827		ehci0: usb@11c50100 {
    828			compatible = "generic-ehci";
    829			reg = <0 0x11c50100 0 0x100>;
    830			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
    831			clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
    832				 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
    833			resets = <&phyrst 0>,
    834				 <&cpg R9A07G044_USB_U2H0_HRESETN>;
    835			phys = <&usb2_phy0 2>;
    836			phy-names = "usb";
    837			companion = <&ohci0>;
    838			power-domains = <&cpg>;
    839			status = "disabled";
    840		};
    841
    842		ehci1: usb@11c70100 {
    843			compatible = "generic-ehci";
    844			reg = <0 0x11c70100 0 0x100>;
    845			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
    846			clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
    847				 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
    848			resets = <&phyrst 1>,
    849				 <&cpg R9A07G044_USB_U2H1_HRESETN>;
    850			phys = <&usb2_phy1 2>;
    851			phy-names = "usb";
    852			companion = <&ohci1>;
    853			power-domains = <&cpg>;
    854			status = "disabled";
    855		};
    856
    857		usb2_phy0: usb-phy@11c50200 {
    858			compatible = "renesas,usb2-phy-r9a07g044",
    859				     "renesas,rzg2l-usb2-phy";
    860			reg = <0 0x11c50200 0 0x700>;
    861			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
    862			clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
    863				 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
    864			resets = <&phyrst 0>;
    865			#phy-cells = <1>;
    866			power-domains = <&cpg>;
    867			status = "disabled";
    868		};
    869
    870		usb2_phy1: usb-phy@11c70200 {
    871			compatible = "renesas,usb2-phy-r9a07g044",
    872				     "renesas,rzg2l-usb2-phy";
    873			reg = <0 0x11c70200 0 0x700>;
    874			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
    875			clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
    876				 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
    877			resets = <&phyrst 1>;
    878			#phy-cells = <1>;
    879			power-domains = <&cpg>;
    880			status = "disabled";
    881		};
    882
    883		hsusb: usb@11c60000 {
    884			compatible = "renesas,usbhs-r9a07g044",
    885				     "renesas,rza2-usbhs";
    886			reg = <0 0x11c60000 0 0x10000>;
    887			interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
    888				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
    889				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
    890				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
    891			clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
    892				 <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>;
    893			resets = <&phyrst 0>,
    894				 <&cpg R9A07G044_USB_U2P_EXL_SYSRST>;
    895			renesas,buswait = <7>;
    896			phys = <&usb2_phy0 3>;
    897			phy-names = "usb";
    898			power-domains = <&cpg>;
    899			status = "disabled";
    900		};
    901
    902		wdt0: watchdog@12800800 {
    903			compatible = "renesas,r9a07g044-wdt",
    904				     "renesas,rzg2l-wdt";
    905			reg = <0 0x12800800 0 0x400>;
    906			clocks = <&cpg CPG_MOD R9A07G044_WDT0_PCLK>,
    907				 <&cpg CPG_MOD R9A07G044_WDT0_CLK>;
    908			clock-names = "pclk", "oscclk";
    909			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
    910				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
    911			interrupt-names = "wdt", "perrout";
    912			resets = <&cpg R9A07G044_WDT0_PRESETN>;
    913			power-domains = <&cpg>;
    914			status = "disabled";
    915		};
    916
    917		wdt1: watchdog@12800c00 {
    918			compatible = "renesas,r9a07g044-wdt",
    919				     "renesas,rzg2l-wdt";
    920			reg = <0 0x12800C00 0 0x400>;
    921			clocks = <&cpg CPG_MOD R9A07G044_WDT1_PCLK>,
    922				 <&cpg CPG_MOD R9A07G044_WDT1_CLK>;
    923			clock-names = "pclk", "oscclk";
    924			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
    925				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
    926			interrupt-names = "wdt", "perrout";
    927			resets = <&cpg R9A07G044_WDT1_PRESETN>;
    928			power-domains = <&cpg>;
    929			status = "disabled";
    930		};
    931
    932		wdt2: watchdog@12800400 {
    933			compatible = "renesas,r9a07g044-wdt",
    934				     "renesas,rzg2l-wdt";
    935			reg = <0 0x12800400 0 0x400>;
    936			clocks = <&cpg CPG_MOD R9A07G044_WDT2_PCLK>,
    937				 <&cpg CPG_MOD R9A07G044_WDT2_CLK>;
    938			clock-names = "pclk", "oscclk";
    939			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
    940				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
    941			interrupt-names = "wdt", "perrout";
    942			resets = <&cpg R9A07G044_WDT2_PRESETN>;
    943			power-domains = <&cpg>;
    944			status = "disabled";
    945		};
    946
    947		ostm0: timer@12801000 {
    948			compatible = "renesas,r9a07g044-ostm",
    949				     "renesas,ostm";
    950			reg = <0x0 0x12801000 0x0 0x400>;
    951			interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
    952			clocks = <&cpg CPG_MOD R9A07G044_OSTM0_PCLK>;
    953			resets = <&cpg R9A07G044_OSTM0_PRESETZ>;
    954			power-domains = <&cpg>;
    955			status = "disabled";
    956		};
    957
    958		ostm1: timer@12801400 {
    959			compatible = "renesas,r9a07g044-ostm",
    960				     "renesas,ostm";
    961			reg = <0x0 0x12801400 0x0 0x400>;
    962			interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
    963			clocks = <&cpg CPG_MOD R9A07G044_OSTM1_PCLK>;
    964			resets = <&cpg R9A07G044_OSTM1_PRESETZ>;
    965			power-domains = <&cpg>;
    966			status = "disabled";
    967		};
    968
    969		ostm2: timer@12801800 {
    970			compatible = "renesas,r9a07g044-ostm",
    971				     "renesas,ostm";
    972			reg = <0x0 0x12801800 0x0 0x400>;
    973			interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
    974			clocks = <&cpg CPG_MOD R9A07G044_OSTM2_PCLK>;
    975			resets = <&cpg R9A07G044_OSTM2_PRESETZ>;
    976			power-domains = <&cpg>;
    977			status = "disabled";
    978		};
    979	};
    980
    981	thermal-zones {
    982		cpu-thermal {
    983			polling-delay-passive = <250>;
    984			polling-delay = <1000>;
    985			thermal-sensors = <&tsu 0>;
    986			sustainable-power = <717>;
    987
    988			cooling-maps {
    989				map0 {
    990					trip = <&target>;
    991					cooling-device = <&cpu0 0 2>;
    992					contribution = <1024>;
    993				};
    994			};
    995
    996			trips {
    997				sensor_crit: sensor-crit {
    998					temperature = <125000>;
    999					hysteresis = <1000>;
   1000					type = "critical";
   1001				};
   1002
   1003				target: trip-point {
   1004					temperature = <100000>;
   1005					hysteresis = <1000>;
   1006					type = "passive";
   1007				};
   1008			};
   1009		};
   1010	};
   1011
   1012	timer {
   1013		compatible = "arm,armv8-timer";
   1014		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
   1015				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
   1016				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
   1017				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
   1018	};
   1019};