cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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r9a09g011.dtsi (2347B)

      1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2/*
      3 * Device Tree Source for the RZ/V2M SoC
      4 *
      5 * Copyright (C) 2022 Renesas Electronics Corp.
      6 */
      7
      8#include <dt-bindings/interrupt-controller/arm-gic.h>
      9#include <dt-bindings/clock/r9a09g011-cpg.h>
     10
     11/ {
     12	compatible = "renesas,r9a09g011";
     13	#address-cells = <2>;
     14	#size-cells = <2>;
     15
     16	/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
     17	extal_clk: extal {
     18		compatible = "fixed-clock";
     19		#clock-cells = <0>;
     20		/* This value must be overridden by the board */
     21		clock-frequency = <0>;
     22	};
     23
     24	cpus {
     25		#address-cells = <1>;
     26		#size-cells = <0>;
     27
     28		cpu-map {
     29			cluster0 {
     30				core0 {
     31					cpu = <&cpu0>;
     32				};
     33			};
     34		};
     35
     36		cpu0: cpu@0 {
     37			compatible = "arm,cortex-a53";
     38			reg = <0>;
     39			device_type = "cpu";
     40			clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>;
     41		};
     42	};
     43
     44	soc: soc {
     45		compatible = "simple-bus";
     46		interrupt-parent = <&gic>;
     47		#address-cells = <2>;
     48		#size-cells = <2>;
     49		ranges;
     50
     51		gic: interrupt-controller@82000000 {
     52			compatible = "arm,gic-400";
     53			#interrupt-cells = <3>;
     54			#address-cells = <0>;
     55			interrupt-controller;
     56			reg = <0x0 0x82010000 0 0x1000>,
     57			      <0x0 0x82020000 0 0x20000>,
     58			      <0x0 0x82040000 0 0x20000>,
     59			      <0x0 0x82060000 0 0x20000>;
     60			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
     61			clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>;
     62			clock-names = "clk";
     63		};
     64
     65		cpg: clock-controller@a3500000 {
     66			compatible = "renesas,r9a09g011-cpg";
     67			reg = <0 0xa3500000 0 0x1000>;
     68			clocks = <&extal_clk>;
     69			clock-names = "extal";
     70			#clock-cells = <2>;
     71			#reset-cells = <1>;
     72			#power-domain-cells = <0>;
     73		};
     74
     75		uart0: serial@a4040000 {
     76			compatible = "renesas,r9a09g011-uart", "renesas,em-uart";
     77			reg = <0 0xa4040000 0 0x80>;
     78			interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
     79			clocks = <&cpg CPG_MOD R9A09G011_URT0_CLK>,
     80				 <&cpg CPG_MOD R9A09G011_URT_PCLK>;
     81			clock-names = "sclk", "pclk";
     82			status = "disabled";
     83		};
     84	};
     85
     86	timer {
     87		compatible = "arm,armv8-timer";
     88		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
     89				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
     90				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
     91				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
     92	};
     93};