px30.dtsi (59634B)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/px30-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/px30-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,px30"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 ethernet0 = &gmac; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 serial0 = &uart0; 29 serial1 = &uart1; 30 serial2 = &uart2; 31 serial3 = &uart3; 32 serial4 = &uart4; 33 serial5 = &uart5; 34 spi0 = &spi0; 35 spi1 = &spi1; 36 }; 37 38 cpus { 39 #address-cells = <2>; 40 #size-cells = <0>; 41 42 cpu0: cpu@0 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a35"; 45 reg = <0x0 0x0>; 46 enable-method = "psci"; 47 clocks = <&cru ARMCLK>; 48 #cooling-cells = <2>; 49 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 50 dynamic-power-coefficient = <90>; 51 operating-points-v2 = <&cpu0_opp_table>; 52 }; 53 54 cpu1: cpu@1 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a35"; 57 reg = <0x0 0x1>; 58 enable-method = "psci"; 59 clocks = <&cru ARMCLK>; 60 #cooling-cells = <2>; 61 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 62 dynamic-power-coefficient = <90>; 63 operating-points-v2 = <&cpu0_opp_table>; 64 }; 65 66 cpu2: cpu@2 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a35"; 69 reg = <0x0 0x2>; 70 enable-method = "psci"; 71 clocks = <&cru ARMCLK>; 72 #cooling-cells = <2>; 73 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 74 dynamic-power-coefficient = <90>; 75 operating-points-v2 = <&cpu0_opp_table>; 76 }; 77 78 cpu3: cpu@3 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a35"; 81 reg = <0x0 0x3>; 82 enable-method = "psci"; 83 clocks = <&cru ARMCLK>; 84 #cooling-cells = <2>; 85 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 86 dynamic-power-coefficient = <90>; 87 operating-points-v2 = <&cpu0_opp_table>; 88 }; 89 90 idle-states { 91 entry-method = "psci"; 92 93 CPU_SLEEP: cpu-sleep { 94 compatible = "arm,idle-state"; 95 local-timer-stop; 96 arm,psci-suspend-param = <0x0010000>; 97 entry-latency-us = <120>; 98 exit-latency-us = <250>; 99 min-residency-us = <900>; 100 }; 101 102 CLUSTER_SLEEP: cluster-sleep { 103 compatible = "arm,idle-state"; 104 local-timer-stop; 105 arm,psci-suspend-param = <0x1010000>; 106 entry-latency-us = <400>; 107 exit-latency-us = <500>; 108 min-residency-us = <2000>; 109 }; 110 }; 111 }; 112 113 cpu0_opp_table: opp-table-0 { 114 compatible = "operating-points-v2"; 115 opp-shared; 116 117 opp-600000000 { 118 opp-hz = /bits/ 64 <600000000>; 119 opp-microvolt = <950000 950000 1350000>; 120 clock-latency-ns = <40000>; 121 opp-suspend; 122 }; 123 opp-816000000 { 124 opp-hz = /bits/ 64 <816000000>; 125 opp-microvolt = <1050000 1050000 1350000>; 126 clock-latency-ns = <40000>; 127 }; 128 opp-1008000000 { 129 opp-hz = /bits/ 64 <1008000000>; 130 opp-microvolt = <1175000 1175000 1350000>; 131 clock-latency-ns = <40000>; 132 }; 133 opp-1200000000 { 134 opp-hz = /bits/ 64 <1200000000>; 135 opp-microvolt = <1300000 1300000 1350000>; 136 clock-latency-ns = <40000>; 137 }; 138 opp-1296000000 { 139 opp-hz = /bits/ 64 <1296000000>; 140 opp-microvolt = <1350000 1350000 1350000>; 141 clock-latency-ns = <40000>; 142 }; 143 }; 144 145 arm-pmu { 146 compatible = "arm,cortex-a35-pmu"; 147 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 152 }; 153 154 display_subsystem: display-subsystem { 155 compatible = "rockchip,display-subsystem"; 156 ports = <&vopb_out>, <&vopl_out>; 157 status = "disabled"; 158 }; 159 160 gmac_clkin: external-gmac-clock { 161 compatible = "fixed-clock"; 162 clock-frequency = <50000000>; 163 clock-output-names = "gmac_clkin"; 164 #clock-cells = <0>; 165 }; 166 167 psci { 168 compatible = "arm,psci-1.0"; 169 method = "smc"; 170 }; 171 172 timer { 173 compatible = "arm,armv8-timer"; 174 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 175 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 176 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 177 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 178 }; 179 180 thermal_zones: thermal-zones { 181 soc_thermal: soc-thermal { 182 polling-delay-passive = <20>; 183 polling-delay = <1000>; 184 sustainable-power = <750>; 185 thermal-sensors = <&tsadc 0>; 186 187 trips { 188 threshold: trip-point-0 { 189 temperature = <70000>; 190 hysteresis = <2000>; 191 type = "passive"; 192 }; 193 194 target: trip-point-1 { 195 temperature = <85000>; 196 hysteresis = <2000>; 197 type = "passive"; 198 }; 199 200 soc_crit: soc-crit { 201 temperature = <115000>; 202 hysteresis = <2000>; 203 type = "critical"; 204 }; 205 }; 206 207 cooling-maps { 208 map0 { 209 trip = <&target>; 210 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 211 contribution = <4096>; 212 }; 213 214 map1 { 215 trip = <&target>; 216 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 217 contribution = <4096>; 218 }; 219 }; 220 }; 221 222 gpu_thermal: gpu-thermal { 223 polling-delay-passive = <100>; /* milliseconds */ 224 polling-delay = <1000>; /* milliseconds */ 225 thermal-sensors = <&tsadc 1>; 226 }; 227 }; 228 229 xin24m: xin24m { 230 compatible = "fixed-clock"; 231 #clock-cells = <0>; 232 clock-frequency = <24000000>; 233 clock-output-names = "xin24m"; 234 }; 235 236 pmu: power-management@ff000000 { 237 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; 238 reg = <0x0 0xff000000 0x0 0x1000>; 239 240 power: power-controller { 241 compatible = "rockchip,px30-power-controller"; 242 #power-domain-cells = <1>; 243 #address-cells = <1>; 244 #size-cells = <0>; 245 246 /* These power domains are grouped by VD_LOGIC */ 247 power-domain@PX30_PD_USB { 248 reg = <PX30_PD_USB>; 249 clocks = <&cru HCLK_HOST>, 250 <&cru HCLK_OTG>, 251 <&cru SCLK_OTG_ADP>; 252 pm_qos = <&qos_usb_host>, <&qos_usb_otg>; 253 #power-domain-cells = <0>; 254 }; 255 power-domain@PX30_PD_SDCARD { 256 reg = <PX30_PD_SDCARD>; 257 clocks = <&cru HCLK_SDMMC>, 258 <&cru SCLK_SDMMC>; 259 pm_qos = <&qos_sdmmc>; 260 #power-domain-cells = <0>; 261 }; 262 power-domain@PX30_PD_GMAC { 263 reg = <PX30_PD_GMAC>; 264 clocks = <&cru ACLK_GMAC>, 265 <&cru PCLK_GMAC>, 266 <&cru SCLK_MAC_REF>, 267 <&cru SCLK_GMAC_RX_TX>; 268 pm_qos = <&qos_gmac>; 269 #power-domain-cells = <0>; 270 }; 271 power-domain@PX30_PD_MMC_NAND { 272 reg = <PX30_PD_MMC_NAND>; 273 clocks = <&cru HCLK_NANDC>, 274 <&cru HCLK_EMMC>, 275 <&cru HCLK_SDIO>, 276 <&cru HCLK_SFC>, 277 <&cru SCLK_EMMC>, 278 <&cru SCLK_NANDC>, 279 <&cru SCLK_SDIO>, 280 <&cru SCLK_SFC>; 281 pm_qos = <&qos_emmc>, <&qos_nand>, 282 <&qos_sdio>, <&qos_sfc>; 283 #power-domain-cells = <0>; 284 }; 285 power-domain@PX30_PD_VPU { 286 reg = <PX30_PD_VPU>; 287 clocks = <&cru ACLK_VPU>, 288 <&cru HCLK_VPU>, 289 <&cru SCLK_CORE_VPU>; 290 pm_qos = <&qos_vpu>, <&qos_vpu_r128>; 291 #power-domain-cells = <0>; 292 }; 293 power-domain@PX30_PD_VO { 294 reg = <PX30_PD_VO>; 295 clocks = <&cru ACLK_RGA>, 296 <&cru ACLK_VOPB>, 297 <&cru ACLK_VOPL>, 298 <&cru DCLK_VOPB>, 299 <&cru DCLK_VOPL>, 300 <&cru HCLK_RGA>, 301 <&cru HCLK_VOPB>, 302 <&cru HCLK_VOPL>, 303 <&cru PCLK_MIPI_DSI>, 304 <&cru SCLK_RGA_CORE>, 305 <&cru SCLK_VOPB_PWM>; 306 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, 307 <&qos_vop_m0>, <&qos_vop_m1>; 308 #power-domain-cells = <0>; 309 }; 310 power-domain@PX30_PD_VI { 311 reg = <PX30_PD_VI>; 312 clocks = <&cru ACLK_CIF>, 313 <&cru ACLK_ISP>, 314 <&cru HCLK_CIF>, 315 <&cru HCLK_ISP>, 316 <&cru SCLK_ISP>; 317 pm_qos = <&qos_isp_128>, <&qos_isp_rd>, 318 <&qos_isp_wr>, <&qos_isp_m1>, 319 <&qos_vip>; 320 #power-domain-cells = <0>; 321 }; 322 power-domain@PX30_PD_GPU { 323 reg = <PX30_PD_GPU>; 324 clocks = <&cru SCLK_GPU>; 325 pm_qos = <&qos_gpu>; 326 #power-domain-cells = <0>; 327 }; 328 }; 329 }; 330 331 pmugrf: syscon@ff010000 { 332 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; 333 reg = <0x0 0xff010000 0x0 0x1000>; 334 #address-cells = <1>; 335 #size-cells = <1>; 336 337 pmu_io_domains: io-domains { 338 compatible = "rockchip,px30-pmu-io-voltage-domain"; 339 status = "disabled"; 340 }; 341 342 reboot-mode { 343 compatible = "syscon-reboot-mode"; 344 offset = <0x200>; 345 mode-bootloader = <BOOT_BL_DOWNLOAD>; 346 mode-fastboot = <BOOT_FASTBOOT>; 347 mode-loader = <BOOT_BL_DOWNLOAD>; 348 mode-normal = <BOOT_NORMAL>; 349 mode-recovery = <BOOT_RECOVERY>; 350 }; 351 }; 352 353 uart0: serial@ff030000 { 354 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 355 reg = <0x0 0xff030000 0x0 0x100>; 356 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>; 358 clock-names = "baudclk", "apb_pclk"; 359 dmas = <&dmac 0>, <&dmac 1>; 360 dma-names = "tx", "rx"; 361 reg-shift = <2>; 362 reg-io-width = <4>; 363 pinctrl-names = "default"; 364 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 365 status = "disabled"; 366 }; 367 368 i2s1_2ch: i2s@ff070000 { 369 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 370 reg = <0x0 0xff070000 0x0 0x1000>; 371 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 372 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; 373 clock-names = "i2s_clk", "i2s_hclk"; 374 dmas = <&dmac 18>, <&dmac 19>; 375 dma-names = "tx", "rx"; 376 pinctrl-names = "default"; 377 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck 378 &i2s1_2ch_sdi &i2s1_2ch_sdo>; 379 #sound-dai-cells = <0>; 380 status = "disabled"; 381 }; 382 383 i2s2_2ch: i2s@ff080000 { 384 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 385 reg = <0x0 0xff080000 0x0 0x1000>; 386 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; 388 clock-names = "i2s_clk", "i2s_hclk"; 389 dmas = <&dmac 20>, <&dmac 21>; 390 dma-names = "tx", "rx"; 391 pinctrl-names = "default"; 392 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck 393 &i2s2_2ch_sdi &i2s2_2ch_sdo>; 394 #sound-dai-cells = <0>; 395 status = "disabled"; 396 }; 397 398 gic: interrupt-controller@ff131000 { 399 compatible = "arm,gic-400"; 400 #interrupt-cells = <3>; 401 #address-cells = <0>; 402 interrupt-controller; 403 reg = <0x0 0xff131000 0 0x1000>, 404 <0x0 0xff132000 0 0x2000>, 405 <0x0 0xff134000 0 0x2000>, 406 <0x0 0xff136000 0 0x2000>; 407 interrupts = <GIC_PPI 9 408 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 409 }; 410 411 grf: syscon@ff140000 { 412 compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; 413 reg = <0x0 0xff140000 0x0 0x1000>; 414 #address-cells = <1>; 415 #size-cells = <1>; 416 417 io_domains: io-domains { 418 compatible = "rockchip,px30-io-voltage-domain"; 419 status = "disabled"; 420 }; 421 422 lvds: lvds { 423 compatible = "rockchip,px30-lvds"; 424 phys = <&dsi_dphy>; 425 phy-names = "dphy"; 426 rockchip,grf = <&grf>; 427 rockchip,output = "lvds"; 428 status = "disabled"; 429 430 ports { 431 #address-cells = <1>; 432 #size-cells = <0>; 433 434 port@0 { 435 reg = <0>; 436 #address-cells = <1>; 437 #size-cells = <0>; 438 439 lvds_vopb_in: endpoint@0 { 440 reg = <0>; 441 remote-endpoint = <&vopb_out_lvds>; 442 }; 443 444 lvds_vopl_in: endpoint@1 { 445 reg = <1>; 446 remote-endpoint = <&vopl_out_lvds>; 447 }; 448 }; 449 }; 450 }; 451 }; 452 453 uart1: serial@ff158000 { 454 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 455 reg = <0x0 0xff158000 0x0 0x100>; 456 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 457 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 458 clock-names = "baudclk", "apb_pclk"; 459 dmas = <&dmac 2>, <&dmac 3>; 460 dma-names = "tx", "rx"; 461 reg-shift = <2>; 462 reg-io-width = <4>; 463 pinctrl-names = "default"; 464 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 465 status = "disabled"; 466 }; 467 468 uart2: serial@ff160000 { 469 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 470 reg = <0x0 0xff160000 0x0 0x100>; 471 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 473 clock-names = "baudclk", "apb_pclk"; 474 dmas = <&dmac 4>, <&dmac 5>; 475 dma-names = "tx", "rx"; 476 reg-shift = <2>; 477 reg-io-width = <4>; 478 pinctrl-names = "default"; 479 pinctrl-0 = <&uart2m0_xfer>; 480 status = "disabled"; 481 }; 482 483 uart3: serial@ff168000 { 484 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 485 reg = <0x0 0xff168000 0x0 0x100>; 486 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 488 clock-names = "baudclk", "apb_pclk"; 489 dmas = <&dmac 6>, <&dmac 7>; 490 dma-names = "tx", "rx"; 491 reg-shift = <2>; 492 reg-io-width = <4>; 493 pinctrl-names = "default"; 494 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>; 495 status = "disabled"; 496 }; 497 498 uart4: serial@ff170000 { 499 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 500 reg = <0x0 0xff170000 0x0 0x100>; 501 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 503 clock-names = "baudclk", "apb_pclk"; 504 dmas = <&dmac 8>, <&dmac 9>; 505 dma-names = "tx", "rx"; 506 reg-shift = <2>; 507 reg-io-width = <4>; 508 pinctrl-names = "default"; 509 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 510 status = "disabled"; 511 }; 512 513 uart5: serial@ff178000 { 514 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 515 reg = <0x0 0xff178000 0x0 0x100>; 516 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 518 clock-names = "baudclk", "apb_pclk"; 519 dmas = <&dmac 10>, <&dmac 11>; 520 dma-names = "tx", "rx"; 521 reg-shift = <2>; 522 reg-io-width = <4>; 523 pinctrl-names = "default"; 524 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>; 525 status = "disabled"; 526 }; 527 528 i2c0: i2c@ff180000 { 529 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 530 reg = <0x0 0xff180000 0x0 0x1000>; 531 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 532 clock-names = "i2c", "pclk"; 533 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 534 pinctrl-names = "default"; 535 pinctrl-0 = <&i2c0_xfer>; 536 #address-cells = <1>; 537 #size-cells = <0>; 538 status = "disabled"; 539 }; 540 541 i2c1: i2c@ff190000 { 542 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 543 reg = <0x0 0xff190000 0x0 0x1000>; 544 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 545 clock-names = "i2c", "pclk"; 546 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 547 pinctrl-names = "default"; 548 pinctrl-0 = <&i2c1_xfer>; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 status = "disabled"; 552 }; 553 554 i2c2: i2c@ff1a0000 { 555 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 556 reg = <0x0 0xff1a0000 0x0 0x1000>; 557 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 558 clock-names = "i2c", "pclk"; 559 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 560 pinctrl-names = "default"; 561 pinctrl-0 = <&i2c2_xfer>; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 status = "disabled"; 565 }; 566 567 i2c3: i2c@ff1b0000 { 568 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 569 reg = <0x0 0xff1b0000 0x0 0x1000>; 570 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 571 clock-names = "i2c", "pclk"; 572 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 573 pinctrl-names = "default"; 574 pinctrl-0 = <&i2c3_xfer>; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 status = "disabled"; 578 }; 579 580 spi0: spi@ff1d0000 { 581 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 582 reg = <0x0 0xff1d0000 0x0 0x1000>; 583 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 584 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 585 clock-names = "spiclk", "apb_pclk"; 586 dmas = <&dmac 12>, <&dmac 13>; 587 dma-names = "tx", "rx"; 588 pinctrl-names = "default"; 589 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 590 #address-cells = <1>; 591 #size-cells = <0>; 592 status = "disabled"; 593 }; 594 595 spi1: spi@ff1d8000 { 596 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 597 reg = <0x0 0xff1d8000 0x0 0x1000>; 598 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 599 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 600 clock-names = "spiclk", "apb_pclk"; 601 dmas = <&dmac 14>, <&dmac 15>; 602 dma-names = "tx", "rx"; 603 pinctrl-names = "default"; 604 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>; 605 #address-cells = <1>; 606 #size-cells = <0>; 607 status = "disabled"; 608 }; 609 610 wdt: watchdog@ff1e0000 { 611 compatible = "rockchip,px30-wdt", "snps,dw-wdt"; 612 reg = <0x0 0xff1e0000 0x0 0x100>; 613 clocks = <&cru PCLK_WDT_NS>; 614 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 615 status = "disabled"; 616 }; 617 618 pwm0: pwm@ff200000 { 619 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 620 reg = <0x0 0xff200000 0x0 0x10>; 621 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 622 clock-names = "pwm", "pclk"; 623 pinctrl-names = "default"; 624 pinctrl-0 = <&pwm0_pin>; 625 #pwm-cells = <3>; 626 status = "disabled"; 627 }; 628 629 pwm1: pwm@ff200010 { 630 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 631 reg = <0x0 0xff200010 0x0 0x10>; 632 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 633 clock-names = "pwm", "pclk"; 634 pinctrl-names = "default"; 635 pinctrl-0 = <&pwm1_pin>; 636 #pwm-cells = <3>; 637 status = "disabled"; 638 }; 639 640 pwm2: pwm@ff200020 { 641 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 642 reg = <0x0 0xff200020 0x0 0x10>; 643 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 644 clock-names = "pwm", "pclk"; 645 pinctrl-names = "default"; 646 pinctrl-0 = <&pwm2_pin>; 647 #pwm-cells = <3>; 648 status = "disabled"; 649 }; 650 651 pwm3: pwm@ff200030 { 652 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 653 reg = <0x0 0xff200030 0x0 0x10>; 654 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 655 clock-names = "pwm", "pclk"; 656 pinctrl-names = "default"; 657 pinctrl-0 = <&pwm3_pin>; 658 #pwm-cells = <3>; 659 status = "disabled"; 660 }; 661 662 pwm4: pwm@ff208000 { 663 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 664 reg = <0x0 0xff208000 0x0 0x10>; 665 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 666 clock-names = "pwm", "pclk"; 667 pinctrl-names = "default"; 668 pinctrl-0 = <&pwm4_pin>; 669 #pwm-cells = <3>; 670 status = "disabled"; 671 }; 672 673 pwm5: pwm@ff208010 { 674 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 675 reg = <0x0 0xff208010 0x0 0x10>; 676 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 677 clock-names = "pwm", "pclk"; 678 pinctrl-names = "default"; 679 pinctrl-0 = <&pwm5_pin>; 680 #pwm-cells = <3>; 681 status = "disabled"; 682 }; 683 684 pwm6: pwm@ff208020 { 685 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 686 reg = <0x0 0xff208020 0x0 0x10>; 687 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 688 clock-names = "pwm", "pclk"; 689 pinctrl-names = "default"; 690 pinctrl-0 = <&pwm6_pin>; 691 #pwm-cells = <3>; 692 status = "disabled"; 693 }; 694 695 pwm7: pwm@ff208030 { 696 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 697 reg = <0x0 0xff208030 0x0 0x10>; 698 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 699 clock-names = "pwm", "pclk"; 700 pinctrl-names = "default"; 701 pinctrl-0 = <&pwm7_pin>; 702 #pwm-cells = <3>; 703 status = "disabled"; 704 }; 705 706 rktimer: timer@ff210000 { 707 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer"; 708 reg = <0x0 0xff210000 0x0 0x1000>; 709 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 710 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 711 clock-names = "pclk", "timer"; 712 }; 713 714 dmac: dma-controller@ff240000 { 715 compatible = "arm,pl330", "arm,primecell"; 716 reg = <0x0 0xff240000 0x0 0x4000>; 717 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 719 arm,pl330-periph-burst; 720 clocks = <&cru ACLK_DMAC>; 721 clock-names = "apb_pclk"; 722 #dma-cells = <1>; 723 }; 724 725 tsadc: tsadc@ff280000 { 726 compatible = "rockchip,px30-tsadc"; 727 reg = <0x0 0xff280000 0x0 0x100>; 728 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 729 assigned-clocks = <&cru SCLK_TSADC>; 730 assigned-clock-rates = <50000>; 731 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 732 clock-names = "tsadc", "apb_pclk"; 733 resets = <&cru SRST_TSADC>; 734 reset-names = "tsadc-apb"; 735 rockchip,grf = <&grf>; 736 rockchip,hw-tshut-temp = <120000>; 737 pinctrl-names = "init", "default", "sleep"; 738 pinctrl-0 = <&tsadc_otp_pin>; 739 pinctrl-1 = <&tsadc_otp_out>; 740 pinctrl-2 = <&tsadc_otp_pin>; 741 #thermal-sensor-cells = <1>; 742 status = "disabled"; 743 }; 744 745 saradc: saradc@ff288000 { 746 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc"; 747 reg = <0x0 0xff288000 0x0 0x100>; 748 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 749 #io-channel-cells = <1>; 750 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 751 clock-names = "saradc", "apb_pclk"; 752 resets = <&cru SRST_SARADC_P>; 753 reset-names = "saradc-apb"; 754 status = "disabled"; 755 }; 756 757 otp: nvmem@ff290000 { 758 compatible = "rockchip,px30-otp"; 759 reg = <0x0 0xff290000 0x0 0x4000>; 760 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, 761 <&cru PCLK_OTP_PHY>; 762 clock-names = "otp", "apb_pclk", "phy"; 763 resets = <&cru SRST_OTP_PHY>; 764 reset-names = "phy"; 765 #address-cells = <1>; 766 #size-cells = <1>; 767 768 /* Data cells */ 769 cpu_id: id@7 { 770 reg = <0x07 0x10>; 771 }; 772 cpu_leakage: cpu-leakage@17 { 773 reg = <0x17 0x1>; 774 }; 775 performance: performance@1e { 776 reg = <0x1e 0x1>; 777 bits = <4 3>; 778 }; 779 }; 780 781 cru: clock-controller@ff2b0000 { 782 compatible = "rockchip,px30-cru"; 783 reg = <0x0 0xff2b0000 0x0 0x1000>; 784 clocks = <&xin24m>, <&pmucru PLL_GPLL>; 785 clock-names = "xin24m", "gpll"; 786 rockchip,grf = <&grf>; 787 #clock-cells = <1>; 788 #reset-cells = <1>; 789 790 assigned-clocks = <&cru PLL_NPLL>, 791 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 792 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, 793 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; 794 795 assigned-clock-rates = <1188000000>, 796 <200000000>, <200000000>, 797 <150000000>, <150000000>, 798 <100000000>, <200000000>; 799 }; 800 801 pmucru: clock-controller@ff2bc000 { 802 compatible = "rockchip,px30-pmucru"; 803 reg = <0x0 0xff2bc000 0x0 0x1000>; 804 clocks = <&xin24m>; 805 clock-names = "xin24m"; 806 rockchip,grf = <&grf>; 807 #clock-cells = <1>; 808 #reset-cells = <1>; 809 810 assigned-clocks = 811 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, 812 <&pmucru SCLK_WIFI_PMU>; 813 assigned-clock-rates = 814 <1200000000>, <100000000>, 815 <26000000>; 816 }; 817 818 usb2phy_grf: syscon@ff2c0000 { 819 compatible = "rockchip,px30-usb2phy-grf", "syscon", 820 "simple-mfd"; 821 reg = <0x0 0xff2c0000 0x0 0x10000>; 822 #address-cells = <1>; 823 #size-cells = <1>; 824 825 u2phy: usb2phy@100 { 826 compatible = "rockchip,px30-usb2phy"; 827 reg = <0x100 0x20>; 828 clocks = <&pmucru SCLK_USBPHY_REF>; 829 clock-names = "phyclk"; 830 #clock-cells = <0>; 831 assigned-clocks = <&cru USB480M>; 832 assigned-clock-parents = <&u2phy>; 833 clock-output-names = "usb480m_phy"; 834 status = "disabled"; 835 836 u2phy_host: host-port { 837 #phy-cells = <0>; 838 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 839 interrupt-names = "linestate"; 840 status = "disabled"; 841 }; 842 843 u2phy_otg: otg-port { 844 #phy-cells = <0>; 845 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 846 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 847 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 848 interrupt-names = "otg-bvalid", "otg-id", 849 "linestate"; 850 status = "disabled"; 851 }; 852 }; 853 }; 854 855 dsi_dphy: phy@ff2e0000 { 856 compatible = "rockchip,px30-dsi-dphy"; 857 reg = <0x0 0xff2e0000 0x0 0x10000>; 858 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; 859 clock-names = "ref", "pclk"; 860 resets = <&cru SRST_MIPIDSIPHY_P>; 861 reset-names = "apb"; 862 #phy-cells = <0>; 863 power-domains = <&power PX30_PD_VO>; 864 status = "disabled"; 865 }; 866 867 csi_dphy: phy@ff2f0000 { 868 compatible = "rockchip,px30-csi-dphy"; 869 reg = <0x0 0xff2f0000 0x0 0x4000>; 870 clocks = <&cru PCLK_MIPICSIPHY>; 871 clock-names = "pclk"; 872 #phy-cells = <0>; 873 power-domains = <&power PX30_PD_VI>; 874 resets = <&cru SRST_MIPICSIPHY_P>; 875 reset-names = "apb"; 876 rockchip,grf = <&grf>; 877 status = "disabled"; 878 }; 879 880 usb20_otg: usb@ff300000 { 881 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", 882 "snps,dwc2"; 883 reg = <0x0 0xff300000 0x0 0x40000>; 884 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 885 clocks = <&cru HCLK_OTG>; 886 clock-names = "otg"; 887 dr_mode = "otg"; 888 g-np-tx-fifo-size = <16>; 889 g-rx-fifo-size = <280>; 890 g-tx-fifo-size = <256 128 128 64 32 16>; 891 phys = <&u2phy_otg>; 892 phy-names = "usb2-phy"; 893 power-domains = <&power PX30_PD_USB>; 894 status = "disabled"; 895 }; 896 897 usb_host0_ehci: usb@ff340000 { 898 compatible = "generic-ehci"; 899 reg = <0x0 0xff340000 0x0 0x10000>; 900 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 901 clocks = <&cru HCLK_HOST>; 902 phys = <&u2phy_host>; 903 phy-names = "usb"; 904 power-domains = <&power PX30_PD_USB>; 905 status = "disabled"; 906 }; 907 908 usb_host0_ohci: usb@ff350000 { 909 compatible = "generic-ohci"; 910 reg = <0x0 0xff350000 0x0 0x10000>; 911 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 912 clocks = <&cru HCLK_HOST>; 913 phys = <&u2phy_host>; 914 phy-names = "usb"; 915 power-domains = <&power PX30_PD_USB>; 916 status = "disabled"; 917 }; 918 919 gmac: ethernet@ff360000 { 920 compatible = "rockchip,px30-gmac"; 921 reg = <0x0 0xff360000 0x0 0x10000>; 922 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 923 interrupt-names = "macirq"; 924 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 925 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>, 926 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 927 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>; 928 clock-names = "stmmaceth", "mac_clk_rx", 929 "mac_clk_tx", "clk_mac_ref", 930 "clk_mac_refout", "aclk_mac", 931 "pclk_mac", "clk_mac_speed"; 932 rockchip,grf = <&grf>; 933 phy-mode = "rmii"; 934 pinctrl-names = "default"; 935 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 936 power-domains = <&power PX30_PD_GMAC>; 937 resets = <&cru SRST_GMAC_A>; 938 reset-names = "stmmaceth"; 939 status = "disabled"; 940 }; 941 942 sdmmc: mmc@ff370000 { 943 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 944 reg = <0x0 0xff370000 0x0 0x4000>; 945 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 946 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 947 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 948 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 949 bus-width = <4>; 950 fifo-depth = <0x100>; 951 max-frequency = <150000000>; 952 pinctrl-names = "default"; 953 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 954 power-domains = <&power PX30_PD_SDCARD>; 955 status = "disabled"; 956 }; 957 958 sdio: mmc@ff380000 { 959 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 960 reg = <0x0 0xff380000 0x0 0x4000>; 961 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 962 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 963 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 964 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 965 bus-width = <4>; 966 fifo-depth = <0x100>; 967 max-frequency = <150000000>; 968 pinctrl-names = "default"; 969 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 970 power-domains = <&power PX30_PD_MMC_NAND>; 971 status = "disabled"; 972 }; 973 974 emmc: mmc@ff390000 { 975 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 976 reg = <0x0 0xff390000 0x0 0x4000>; 977 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 978 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 979 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 980 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 981 bus-width = <8>; 982 fifo-depth = <0x100>; 983 max-frequency = <150000000>; 984 pinctrl-names = "default"; 985 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 986 power-domains = <&power PX30_PD_MMC_NAND>; 987 status = "disabled"; 988 }; 989 990 sfc: spi@ff3a0000 { 991 compatible = "rockchip,sfc"; 992 reg = <0x0 0xff3a0000 0x0 0x4000>; 993 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 994 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 995 clock-names = "clk_sfc", "hclk_sfc"; 996 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; 997 pinctrl-names = "default"; 998 power-domains = <&power PX30_PD_MMC_NAND>; 999 status = "disabled"; 1000 }; 1001 1002 nfc: nand-controller@ff3b0000 { 1003 compatible = "rockchip,px30-nfc"; 1004 reg = <0x0 0xff3b0000 0x0 0x4000>; 1005 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1006 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 1007 clock-names = "ahb", "nfc"; 1008 assigned-clocks = <&cru SCLK_NANDC>; 1009 assigned-clock-rates = <150000000>; 1010 pinctrl-names = "default"; 1011 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 1012 &flash_rdn &flash_rdy &flash_wrn &flash_dqs>; 1013 power-domains = <&power PX30_PD_MMC_NAND>; 1014 status = "disabled"; 1015 }; 1016 1017 gpu_opp_table: opp-table-1 { 1018 compatible = "operating-points-v2"; 1019 1020 opp-200000000 { 1021 opp-hz = /bits/ 64 <200000000>; 1022 opp-microvolt = <950000>; 1023 }; 1024 opp-300000000 { 1025 opp-hz = /bits/ 64 <300000000>; 1026 opp-microvolt = <975000>; 1027 }; 1028 opp-400000000 { 1029 opp-hz = /bits/ 64 <400000000>; 1030 opp-microvolt = <1050000>; 1031 }; 1032 opp-480000000 { 1033 opp-hz = /bits/ 64 <480000000>; 1034 opp-microvolt = <1125000>; 1035 }; 1036 }; 1037 1038 gpu: gpu@ff400000 { 1039 compatible = "rockchip,px30-mali", "arm,mali-bifrost"; 1040 reg = <0x0 0xff400000 0x0 0x4000>; 1041 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 1042 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1043 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1044 interrupt-names = "job", "mmu", "gpu"; 1045 clocks = <&cru SCLK_GPU>; 1046 #cooling-cells = <2>; 1047 power-domains = <&power PX30_PD_GPU>; 1048 operating-points-v2 = <&gpu_opp_table>; 1049 status = "disabled"; 1050 }; 1051 1052 vpu: video-codec@ff442000 { 1053 compatible = "rockchip,px30-vpu"; 1054 reg = <0x0 0xff442000 0x0 0x800>; 1055 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 1056 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1057 interrupt-names = "vepu", "vdpu"; 1058 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1059 clock-names = "aclk", "hclk"; 1060 iommus = <&vpu_mmu>; 1061 power-domains = <&power PX30_PD_VPU>; 1062 }; 1063 1064 vpu_mmu: iommu@ff442800 { 1065 compatible = "rockchip,iommu"; 1066 reg = <0x0 0xff442800 0x0 0x100>; 1067 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1068 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1069 clock-names = "aclk", "iface"; 1070 #iommu-cells = <0>; 1071 power-domains = <&power PX30_PD_VPU>; 1072 }; 1073 1074 dsi: dsi@ff450000 { 1075 compatible = "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"; 1076 reg = <0x0 0xff450000 0x0 0x10000>; 1077 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1078 clocks = <&cru PCLK_MIPI_DSI>; 1079 clock-names = "pclk"; 1080 phys = <&dsi_dphy>; 1081 phy-names = "dphy"; 1082 power-domains = <&power PX30_PD_VO>; 1083 resets = <&cru SRST_MIPIDSI_HOST_P>; 1084 reset-names = "apb"; 1085 rockchip,grf = <&grf>; 1086 #address-cells = <1>; 1087 #size-cells = <0>; 1088 status = "disabled"; 1089 1090 ports { 1091 #address-cells = <1>; 1092 #size-cells = <0>; 1093 1094 port@0 { 1095 reg = <0>; 1096 #address-cells = <1>; 1097 #size-cells = <0>; 1098 1099 dsi_in_vopb: endpoint@0 { 1100 reg = <0>; 1101 remote-endpoint = <&vopb_out_dsi>; 1102 }; 1103 1104 dsi_in_vopl: endpoint@1 { 1105 reg = <1>; 1106 remote-endpoint = <&vopl_out_dsi>; 1107 }; 1108 }; 1109 }; 1110 }; 1111 1112 vopb: vop@ff460000 { 1113 compatible = "rockchip,px30-vop-big"; 1114 reg = <0x0 0xff460000 0x0 0xefc>; 1115 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1116 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>, 1117 <&cru HCLK_VOPB>; 1118 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1119 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>; 1120 reset-names = "axi", "ahb", "dclk"; 1121 iommus = <&vopb_mmu>; 1122 power-domains = <&power PX30_PD_VO>; 1123 status = "disabled"; 1124 1125 vopb_out: port { 1126 #address-cells = <1>; 1127 #size-cells = <0>; 1128 1129 vopb_out_dsi: endpoint@0 { 1130 reg = <0>; 1131 remote-endpoint = <&dsi_in_vopb>; 1132 }; 1133 1134 vopb_out_lvds: endpoint@1 { 1135 reg = <1>; 1136 remote-endpoint = <&lvds_vopb_in>; 1137 }; 1138 }; 1139 }; 1140 1141 vopb_mmu: iommu@ff460f00 { 1142 compatible = "rockchip,iommu"; 1143 reg = <0x0 0xff460f00 0x0 0x100>; 1144 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1145 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; 1146 clock-names = "aclk", "iface"; 1147 power-domains = <&power PX30_PD_VO>; 1148 #iommu-cells = <0>; 1149 status = "disabled"; 1150 }; 1151 1152 vopl: vop@ff470000 { 1153 compatible = "rockchip,px30-vop-lit"; 1154 reg = <0x0 0xff470000 0x0 0xefc>; 1155 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1156 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>, 1157 <&cru HCLK_VOPL>; 1158 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1159 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>; 1160 reset-names = "axi", "ahb", "dclk"; 1161 iommus = <&vopl_mmu>; 1162 power-domains = <&power PX30_PD_VO>; 1163 status = "disabled"; 1164 1165 vopl_out: port { 1166 #address-cells = <1>; 1167 #size-cells = <0>; 1168 1169 vopl_out_dsi: endpoint@0 { 1170 reg = <0>; 1171 remote-endpoint = <&dsi_in_vopl>; 1172 }; 1173 1174 vopl_out_lvds: endpoint@1 { 1175 reg = <1>; 1176 remote-endpoint = <&lvds_vopl_in>; 1177 }; 1178 }; 1179 }; 1180 1181 vopl_mmu: iommu@ff470f00 { 1182 compatible = "rockchip,iommu"; 1183 reg = <0x0 0xff470f00 0x0 0x100>; 1184 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1185 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; 1186 clock-names = "aclk", "iface"; 1187 power-domains = <&power PX30_PD_VO>; 1188 #iommu-cells = <0>; 1189 status = "disabled"; 1190 }; 1191 1192 isp: isp@ff4a0000 { 1193 compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/ 1194 reg = <0x0 0xff4a0000 0x0 0x8000>; 1195 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1198 interrupt-names = "isp", "mi", "mipi"; 1199 clocks = <&cru SCLK_ISP>, 1200 <&cru ACLK_ISP>, 1201 <&cru HCLK_ISP>, 1202 <&cru PCLK_ISP>; 1203 clock-names = "isp", "aclk", "hclk", "pclk"; 1204 iommus = <&isp_mmu>; 1205 phys = <&csi_dphy>; 1206 phy-names = "dphy"; 1207 power-domains = <&power PX30_PD_VI>; 1208 status = "disabled"; 1209 1210 ports { 1211 #address-cells = <1>; 1212 #size-cells = <0>; 1213 1214 port@0 { 1215 reg = <0>; 1216 #address-cells = <1>; 1217 #size-cells = <0>; 1218 }; 1219 }; 1220 }; 1221 1222 isp_mmu: iommu@ff4a8000 { 1223 compatible = "rockchip,iommu"; 1224 reg = <0x0 0xff4a8000 0x0 0x100>; 1225 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1226 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1227 clock-names = "aclk", "iface"; 1228 power-domains = <&power PX30_PD_VI>; 1229 rockchip,disable-mmu-reset; 1230 #iommu-cells = <0>; 1231 }; 1232 1233 qos_gmac: qos@ff518000 { 1234 compatible = "rockchip,px30-qos", "syscon"; 1235 reg = <0x0 0xff518000 0x0 0x20>; 1236 }; 1237 1238 qos_gpu: qos@ff520000 { 1239 compatible = "rockchip,px30-qos", "syscon"; 1240 reg = <0x0 0xff520000 0x0 0x20>; 1241 }; 1242 1243 qos_sdmmc: qos@ff52c000 { 1244 compatible = "rockchip,px30-qos", "syscon"; 1245 reg = <0x0 0xff52c000 0x0 0x20>; 1246 }; 1247 1248 qos_emmc: qos@ff538000 { 1249 compatible = "rockchip,px30-qos", "syscon"; 1250 reg = <0x0 0xff538000 0x0 0x20>; 1251 }; 1252 1253 qos_nand: qos@ff538080 { 1254 compatible = "rockchip,px30-qos", "syscon"; 1255 reg = <0x0 0xff538080 0x0 0x20>; 1256 }; 1257 1258 qos_sdio: qos@ff538100 { 1259 compatible = "rockchip,px30-qos", "syscon"; 1260 reg = <0x0 0xff538100 0x0 0x20>; 1261 }; 1262 1263 qos_sfc: qos@ff538180 { 1264 compatible = "rockchip,px30-qos", "syscon"; 1265 reg = <0x0 0xff538180 0x0 0x20>; 1266 }; 1267 1268 qos_usb_host: qos@ff540000 { 1269 compatible = "rockchip,px30-qos", "syscon"; 1270 reg = <0x0 0xff540000 0x0 0x20>; 1271 }; 1272 1273 qos_usb_otg: qos@ff540080 { 1274 compatible = "rockchip,px30-qos", "syscon"; 1275 reg = <0x0 0xff540080 0x0 0x20>; 1276 }; 1277 1278 qos_isp_128: qos@ff548000 { 1279 compatible = "rockchip,px30-qos", "syscon"; 1280 reg = <0x0 0xff548000 0x0 0x20>; 1281 }; 1282 1283 qos_isp_rd: qos@ff548080 { 1284 compatible = "rockchip,px30-qos", "syscon"; 1285 reg = <0x0 0xff548080 0x0 0x20>; 1286 }; 1287 1288 qos_isp_wr: qos@ff548100 { 1289 compatible = "rockchip,px30-qos", "syscon"; 1290 reg = <0x0 0xff548100 0x0 0x20>; 1291 }; 1292 1293 qos_isp_m1: qos@ff548180 { 1294 compatible = "rockchip,px30-qos", "syscon"; 1295 reg = <0x0 0xff548180 0x0 0x20>; 1296 }; 1297 1298 qos_vip: qos@ff548200 { 1299 compatible = "rockchip,px30-qos", "syscon"; 1300 reg = <0x0 0xff548200 0x0 0x20>; 1301 }; 1302 1303 qos_rga_rd: qos@ff550000 { 1304 compatible = "rockchip,px30-qos", "syscon"; 1305 reg = <0x0 0xff550000 0x0 0x20>; 1306 }; 1307 1308 qos_rga_wr: qos@ff550080 { 1309 compatible = "rockchip,px30-qos", "syscon"; 1310 reg = <0x0 0xff550080 0x0 0x20>; 1311 }; 1312 1313 qos_vop_m0: qos@ff550100 { 1314 compatible = "rockchip,px30-qos", "syscon"; 1315 reg = <0x0 0xff550100 0x0 0x20>; 1316 }; 1317 1318 qos_vop_m1: qos@ff550180 { 1319 compatible = "rockchip,px30-qos", "syscon"; 1320 reg = <0x0 0xff550180 0x0 0x20>; 1321 }; 1322 1323 qos_vpu: qos@ff558000 { 1324 compatible = "rockchip,px30-qos", "syscon"; 1325 reg = <0x0 0xff558000 0x0 0x20>; 1326 }; 1327 1328 qos_vpu_r128: qos@ff558080 { 1329 compatible = "rockchip,px30-qos", "syscon"; 1330 reg = <0x0 0xff558080 0x0 0x20>; 1331 }; 1332 1333 pinctrl: pinctrl { 1334 compatible = "rockchip,px30-pinctrl"; 1335 rockchip,grf = <&grf>; 1336 rockchip,pmu = <&pmugrf>; 1337 #address-cells = <2>; 1338 #size-cells = <2>; 1339 ranges; 1340 1341 gpio0: gpio@ff040000 { 1342 compatible = "rockchip,gpio-bank"; 1343 reg = <0x0 0xff040000 0x0 0x100>; 1344 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1345 clocks = <&pmucru PCLK_GPIO0_PMU>; 1346 gpio-controller; 1347 #gpio-cells = <2>; 1348 1349 interrupt-controller; 1350 #interrupt-cells = <2>; 1351 }; 1352 1353 gpio1: gpio@ff250000 { 1354 compatible = "rockchip,gpio-bank"; 1355 reg = <0x0 0xff250000 0x0 0x100>; 1356 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1357 clocks = <&cru PCLK_GPIO1>; 1358 gpio-controller; 1359 #gpio-cells = <2>; 1360 1361 interrupt-controller; 1362 #interrupt-cells = <2>; 1363 }; 1364 1365 gpio2: gpio@ff260000 { 1366 compatible = "rockchip,gpio-bank"; 1367 reg = <0x0 0xff260000 0x0 0x100>; 1368 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1369 clocks = <&cru PCLK_GPIO2>; 1370 gpio-controller; 1371 #gpio-cells = <2>; 1372 1373 interrupt-controller; 1374 #interrupt-cells = <2>; 1375 }; 1376 1377 gpio3: gpio@ff270000 { 1378 compatible = "rockchip,gpio-bank"; 1379 reg = <0x0 0xff270000 0x0 0x100>; 1380 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1381 clocks = <&cru PCLK_GPIO3>; 1382 gpio-controller; 1383 #gpio-cells = <2>; 1384 1385 interrupt-controller; 1386 #interrupt-cells = <2>; 1387 }; 1388 1389 pcfg_pull_up: pcfg-pull-up { 1390 bias-pull-up; 1391 }; 1392 1393 pcfg_pull_down: pcfg-pull-down { 1394 bias-pull-down; 1395 }; 1396 1397 pcfg_pull_none: pcfg-pull-none { 1398 bias-disable; 1399 }; 1400 1401 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1402 bias-disable; 1403 drive-strength = <2>; 1404 }; 1405 1406 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1407 bias-pull-up; 1408 drive-strength = <2>; 1409 }; 1410 1411 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1412 bias-pull-up; 1413 drive-strength = <4>; 1414 }; 1415 1416 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1417 bias-disable; 1418 drive-strength = <4>; 1419 }; 1420 1421 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1422 bias-pull-down; 1423 drive-strength = <4>; 1424 }; 1425 1426 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1427 bias-disable; 1428 drive-strength = <8>; 1429 }; 1430 1431 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1432 bias-pull-up; 1433 drive-strength = <8>; 1434 }; 1435 1436 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1437 bias-disable; 1438 drive-strength = <12>; 1439 }; 1440 1441 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1442 bias-pull-up; 1443 drive-strength = <12>; 1444 }; 1445 1446 pcfg_pull_none_smt: pcfg-pull-none-smt { 1447 bias-disable; 1448 input-schmitt-enable; 1449 }; 1450 1451 pcfg_output_high: pcfg-output-high { 1452 output-high; 1453 }; 1454 1455 pcfg_output_low: pcfg-output-low { 1456 output-low; 1457 }; 1458 1459 pcfg_input_high: pcfg-input-high { 1460 bias-pull-up; 1461 input-enable; 1462 }; 1463 1464 pcfg_input: pcfg-input { 1465 input-enable; 1466 }; 1467 1468 i2c0 { 1469 i2c0_xfer: i2c0-xfer { 1470 rockchip,pins = 1471 <0 RK_PB0 1 &pcfg_pull_none_smt>, 1472 <0 RK_PB1 1 &pcfg_pull_none_smt>; 1473 }; 1474 }; 1475 1476 i2c1 { 1477 i2c1_xfer: i2c1-xfer { 1478 rockchip,pins = 1479 <0 RK_PC2 1 &pcfg_pull_none_smt>, 1480 <0 RK_PC3 1 &pcfg_pull_none_smt>; 1481 }; 1482 }; 1483 1484 i2c2 { 1485 i2c2_xfer: i2c2-xfer { 1486 rockchip,pins = 1487 <2 RK_PB7 2 &pcfg_pull_none_smt>, 1488 <2 RK_PC0 2 &pcfg_pull_none_smt>; 1489 }; 1490 }; 1491 1492 i2c3 { 1493 i2c3_xfer: i2c3-xfer { 1494 rockchip,pins = 1495 <1 RK_PB4 4 &pcfg_pull_none_smt>, 1496 <1 RK_PB5 4 &pcfg_pull_none_smt>; 1497 }; 1498 }; 1499 1500 tsadc { 1501 tsadc_otp_pin: tsadc-otp-pin { 1502 rockchip,pins = 1503 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1504 }; 1505 1506 tsadc_otp_out: tsadc-otp-out { 1507 rockchip,pins = 1508 <0 RK_PA6 1 &pcfg_pull_none>; 1509 }; 1510 }; 1511 1512 uart0 { 1513 uart0_xfer: uart0-xfer { 1514 rockchip,pins = 1515 <0 RK_PB2 1 &pcfg_pull_up>, 1516 <0 RK_PB3 1 &pcfg_pull_up>; 1517 }; 1518 1519 uart0_cts: uart0-cts { 1520 rockchip,pins = 1521 <0 RK_PB4 1 &pcfg_pull_none>; 1522 }; 1523 1524 uart0_rts: uart0-rts { 1525 rockchip,pins = 1526 <0 RK_PB5 1 &pcfg_pull_none>; 1527 }; 1528 }; 1529 1530 uart1 { 1531 uart1_xfer: uart1-xfer { 1532 rockchip,pins = 1533 <1 RK_PC1 1 &pcfg_pull_up>, 1534 <1 RK_PC0 1 &pcfg_pull_up>; 1535 }; 1536 1537 uart1_cts: uart1-cts { 1538 rockchip,pins = 1539 <1 RK_PC2 1 &pcfg_pull_none>; 1540 }; 1541 1542 uart1_rts: uart1-rts { 1543 rockchip,pins = 1544 <1 RK_PC3 1 &pcfg_pull_none>; 1545 }; 1546 }; 1547 1548 uart2-m0 { 1549 uart2m0_xfer: uart2m0-xfer { 1550 rockchip,pins = 1551 <1 RK_PD2 2 &pcfg_pull_up>, 1552 <1 RK_PD3 2 &pcfg_pull_up>; 1553 }; 1554 }; 1555 1556 uart2-m1 { 1557 uart2m1_xfer: uart2m1-xfer { 1558 rockchip,pins = 1559 <2 RK_PB4 2 &pcfg_pull_up>, 1560 <2 RK_PB6 2 &pcfg_pull_up>; 1561 }; 1562 }; 1563 1564 uart3-m0 { 1565 uart3m0_xfer: uart3m0-xfer { 1566 rockchip,pins = 1567 <0 RK_PC0 2 &pcfg_pull_up>, 1568 <0 RK_PC1 2 &pcfg_pull_up>; 1569 }; 1570 1571 uart3m0_cts: uart3m0-cts { 1572 rockchip,pins = 1573 <0 RK_PC2 2 &pcfg_pull_none>; 1574 }; 1575 1576 uart3m0_rts: uart3m0-rts { 1577 rockchip,pins = 1578 <0 RK_PC3 2 &pcfg_pull_none>; 1579 }; 1580 }; 1581 1582 uart3-m1 { 1583 uart3m1_xfer: uart3m1-xfer { 1584 rockchip,pins = 1585 <1 RK_PB6 2 &pcfg_pull_up>, 1586 <1 RK_PB7 2 &pcfg_pull_up>; 1587 }; 1588 1589 uart3m1_cts: uart3m1-cts { 1590 rockchip,pins = 1591 <1 RK_PB4 2 &pcfg_pull_none>; 1592 }; 1593 1594 uart3m1_rts: uart3m1-rts { 1595 rockchip,pins = 1596 <1 RK_PB5 2 &pcfg_pull_none>; 1597 }; 1598 }; 1599 1600 uart4 { 1601 uart4_xfer: uart4-xfer { 1602 rockchip,pins = 1603 <1 RK_PD4 2 &pcfg_pull_up>, 1604 <1 RK_PD5 2 &pcfg_pull_up>; 1605 }; 1606 1607 uart4_cts: uart4-cts { 1608 rockchip,pins = 1609 <1 RK_PD6 2 &pcfg_pull_none>; 1610 }; 1611 1612 uart4_rts: uart4-rts { 1613 rockchip,pins = 1614 <1 RK_PD7 2 &pcfg_pull_none>; 1615 }; 1616 }; 1617 1618 uart5 { 1619 uart5_xfer: uart5-xfer { 1620 rockchip,pins = 1621 <3 RK_PA2 4 &pcfg_pull_up>, 1622 <3 RK_PA1 4 &pcfg_pull_up>; 1623 }; 1624 1625 uart5_cts: uart5-cts { 1626 rockchip,pins = 1627 <3 RK_PA3 4 &pcfg_pull_none>; 1628 }; 1629 1630 uart5_rts: uart5-rts { 1631 rockchip,pins = 1632 <3 RK_PA5 4 &pcfg_pull_none>; 1633 }; 1634 }; 1635 1636 spi0 { 1637 spi0_clk: spi0-clk { 1638 rockchip,pins = 1639 <1 RK_PB7 3 &pcfg_pull_up_4ma>; 1640 }; 1641 1642 spi0_csn: spi0-csn { 1643 rockchip,pins = 1644 <1 RK_PB6 3 &pcfg_pull_up_4ma>; 1645 }; 1646 1647 spi0_miso: spi0-miso { 1648 rockchip,pins = 1649 <1 RK_PB5 3 &pcfg_pull_up_4ma>; 1650 }; 1651 1652 spi0_mosi: spi0-mosi { 1653 rockchip,pins = 1654 <1 RK_PB4 3 &pcfg_pull_up_4ma>; 1655 }; 1656 1657 spi0_clk_hs: spi0-clk-hs { 1658 rockchip,pins = 1659 <1 RK_PB7 3 &pcfg_pull_up_8ma>; 1660 }; 1661 1662 spi0_miso_hs: spi0-miso-hs { 1663 rockchip,pins = 1664 <1 RK_PB5 3 &pcfg_pull_up_8ma>; 1665 }; 1666 1667 spi0_mosi_hs: spi0-mosi-hs { 1668 rockchip,pins = 1669 <1 RK_PB4 3 &pcfg_pull_up_8ma>; 1670 }; 1671 }; 1672 1673 spi1 { 1674 spi1_clk: spi1-clk { 1675 rockchip,pins = 1676 <3 RK_PB7 4 &pcfg_pull_up_4ma>; 1677 }; 1678 1679 spi1_csn0: spi1-csn0 { 1680 rockchip,pins = 1681 <3 RK_PB1 4 &pcfg_pull_up_4ma>; 1682 }; 1683 1684 spi1_csn1: spi1-csn1 { 1685 rockchip,pins = 1686 <3 RK_PB2 2 &pcfg_pull_up_4ma>; 1687 }; 1688 1689 spi1_miso: spi1-miso { 1690 rockchip,pins = 1691 <3 RK_PB6 4 &pcfg_pull_up_4ma>; 1692 }; 1693 1694 spi1_mosi: spi1-mosi { 1695 rockchip,pins = 1696 <3 RK_PB4 4 &pcfg_pull_up_4ma>; 1697 }; 1698 1699 spi1_clk_hs: spi1-clk-hs { 1700 rockchip,pins = 1701 <3 RK_PB7 4 &pcfg_pull_up_8ma>; 1702 }; 1703 1704 spi1_miso_hs: spi1-miso-hs { 1705 rockchip,pins = 1706 <3 RK_PB6 4 &pcfg_pull_up_8ma>; 1707 }; 1708 1709 spi1_mosi_hs: spi1-mosi-hs { 1710 rockchip,pins = 1711 <3 RK_PB4 4 &pcfg_pull_up_8ma>; 1712 }; 1713 }; 1714 1715 pdm { 1716 pdm_clk0m0: pdm-clk0m0 { 1717 rockchip,pins = 1718 <3 RK_PC6 2 &pcfg_pull_none>; 1719 }; 1720 1721 pdm_clk0m1: pdm-clk0m1 { 1722 rockchip,pins = 1723 <2 RK_PC6 1 &pcfg_pull_none>; 1724 }; 1725 1726 pdm_clk1: pdm-clk1 { 1727 rockchip,pins = 1728 <3 RK_PC7 2 &pcfg_pull_none>; 1729 }; 1730 1731 pdm_sdi0m0: pdm-sdi0m0 { 1732 rockchip,pins = 1733 <3 RK_PD3 2 &pcfg_pull_none>; 1734 }; 1735 1736 pdm_sdi0m1: pdm-sdi0m1 { 1737 rockchip,pins = 1738 <2 RK_PC5 2 &pcfg_pull_none>; 1739 }; 1740 1741 pdm_sdi1: pdm-sdi1 { 1742 rockchip,pins = 1743 <3 RK_PD0 2 &pcfg_pull_none>; 1744 }; 1745 1746 pdm_sdi2: pdm-sdi2 { 1747 rockchip,pins = 1748 <3 RK_PD1 2 &pcfg_pull_none>; 1749 }; 1750 1751 pdm_sdi3: pdm-sdi3 { 1752 rockchip,pins = 1753 <3 RK_PD2 2 &pcfg_pull_none>; 1754 }; 1755 1756 pdm_clk0m0_sleep: pdm-clk0m0-sleep { 1757 rockchip,pins = 1758 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1759 }; 1760 1761 pdm_clk0m_sleep1: pdm-clk0m1-sleep { 1762 rockchip,pins = 1763 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1764 }; 1765 1766 pdm_clk1_sleep: pdm-clk1-sleep { 1767 rockchip,pins = 1768 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1769 }; 1770 1771 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep { 1772 rockchip,pins = 1773 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>; 1774 }; 1775 1776 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep { 1777 rockchip,pins = 1778 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1779 }; 1780 1781 pdm_sdi1_sleep: pdm-sdi1-sleep { 1782 rockchip,pins = 1783 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>; 1784 }; 1785 1786 pdm_sdi2_sleep: pdm-sdi2-sleep { 1787 rockchip,pins = 1788 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1789 }; 1790 1791 pdm_sdi3_sleep: pdm-sdi3-sleep { 1792 rockchip,pins = 1793 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>; 1794 }; 1795 }; 1796 1797 i2s0 { 1798 i2s0_8ch_mclk: i2s0-8ch-mclk { 1799 rockchip,pins = 1800 <3 RK_PC1 2 &pcfg_pull_none>; 1801 }; 1802 1803 i2s0_8ch_sclktx: i2s0-8ch-sclktx { 1804 rockchip,pins = 1805 <3 RK_PC3 2 &pcfg_pull_none>; 1806 }; 1807 1808 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 1809 rockchip,pins = 1810 <3 RK_PB4 2 &pcfg_pull_none>; 1811 }; 1812 1813 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 1814 rockchip,pins = 1815 <3 RK_PC2 2 &pcfg_pull_none>; 1816 }; 1817 1818 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 1819 rockchip,pins = 1820 <3 RK_PB5 2 &pcfg_pull_none>; 1821 }; 1822 1823 i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 1824 rockchip,pins = 1825 <3 RK_PC4 2 &pcfg_pull_none>; 1826 }; 1827 1828 i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 1829 rockchip,pins = 1830 <3 RK_PC0 2 &pcfg_pull_none>; 1831 }; 1832 1833 i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 1834 rockchip,pins = 1835 <3 RK_PB7 2 &pcfg_pull_none>; 1836 }; 1837 1838 i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 1839 rockchip,pins = 1840 <3 RK_PB6 2 &pcfg_pull_none>; 1841 }; 1842 1843 i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 1844 rockchip,pins = 1845 <3 RK_PC5 2 &pcfg_pull_none>; 1846 }; 1847 1848 i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 1849 rockchip,pins = 1850 <3 RK_PB3 2 &pcfg_pull_none>; 1851 }; 1852 1853 i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 1854 rockchip,pins = 1855 <3 RK_PB1 2 &pcfg_pull_none>; 1856 }; 1857 1858 i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 1859 rockchip,pins = 1860 <3 RK_PB0 2 &pcfg_pull_none>; 1861 }; 1862 }; 1863 1864 i2s1 { 1865 i2s1_2ch_mclk: i2s1-2ch-mclk { 1866 rockchip,pins = 1867 <2 RK_PC3 1 &pcfg_pull_none>; 1868 }; 1869 1870 i2s1_2ch_sclk: i2s1-2ch-sclk { 1871 rockchip,pins = 1872 <2 RK_PC2 1 &pcfg_pull_none>; 1873 }; 1874 1875 i2s1_2ch_lrck: i2s1-2ch-lrck { 1876 rockchip,pins = 1877 <2 RK_PC1 1 &pcfg_pull_none>; 1878 }; 1879 1880 i2s1_2ch_sdi: i2s1-2ch-sdi { 1881 rockchip,pins = 1882 <2 RK_PC5 1 &pcfg_pull_none>; 1883 }; 1884 1885 i2s1_2ch_sdo: i2s1-2ch-sdo { 1886 rockchip,pins = 1887 <2 RK_PC4 1 &pcfg_pull_none>; 1888 }; 1889 }; 1890 1891 i2s2 { 1892 i2s2_2ch_mclk: i2s2-2ch-mclk { 1893 rockchip,pins = 1894 <3 RK_PA1 2 &pcfg_pull_none>; 1895 }; 1896 1897 i2s2_2ch_sclk: i2s2-2ch-sclk { 1898 rockchip,pins = 1899 <3 RK_PA2 2 &pcfg_pull_none>; 1900 }; 1901 1902 i2s2_2ch_lrck: i2s2-2ch-lrck { 1903 rockchip,pins = 1904 <3 RK_PA3 2 &pcfg_pull_none>; 1905 }; 1906 1907 i2s2_2ch_sdi: i2s2-2ch-sdi { 1908 rockchip,pins = 1909 <3 RK_PA5 2 &pcfg_pull_none>; 1910 }; 1911 1912 i2s2_2ch_sdo: i2s2-2ch-sdo { 1913 rockchip,pins = 1914 <3 RK_PA7 2 &pcfg_pull_none>; 1915 }; 1916 }; 1917 1918 sdmmc { 1919 sdmmc_clk: sdmmc-clk { 1920 rockchip,pins = 1921 <1 RK_PD6 1 &pcfg_pull_none_8ma>; 1922 }; 1923 1924 sdmmc_cmd: sdmmc-cmd { 1925 rockchip,pins = 1926 <1 RK_PD7 1 &pcfg_pull_up_8ma>; 1927 }; 1928 1929 sdmmc_det: sdmmc-det { 1930 rockchip,pins = 1931 <0 RK_PA3 1 &pcfg_pull_up_8ma>; 1932 }; 1933 1934 sdmmc_bus1: sdmmc-bus1 { 1935 rockchip,pins = 1936 <1 RK_PD2 1 &pcfg_pull_up_8ma>; 1937 }; 1938 1939 sdmmc_bus4: sdmmc-bus4 { 1940 rockchip,pins = 1941 <1 RK_PD2 1 &pcfg_pull_up_8ma>, 1942 <1 RK_PD3 1 &pcfg_pull_up_8ma>, 1943 <1 RK_PD4 1 &pcfg_pull_up_8ma>, 1944 <1 RK_PD5 1 &pcfg_pull_up_8ma>; 1945 }; 1946 }; 1947 1948 sdio { 1949 sdio_clk: sdio-clk { 1950 rockchip,pins = 1951 <1 RK_PC5 1 &pcfg_pull_none>; 1952 }; 1953 1954 sdio_cmd: sdio-cmd { 1955 rockchip,pins = 1956 <1 RK_PC4 1 &pcfg_pull_up>; 1957 }; 1958 1959 sdio_bus4: sdio-bus4 { 1960 rockchip,pins = 1961 <1 RK_PC6 1 &pcfg_pull_up>, 1962 <1 RK_PC7 1 &pcfg_pull_up>, 1963 <1 RK_PD0 1 &pcfg_pull_up>, 1964 <1 RK_PD1 1 &pcfg_pull_up>; 1965 }; 1966 }; 1967 1968 emmc { 1969 emmc_clk: emmc-clk { 1970 rockchip,pins = 1971 <1 RK_PB1 2 &pcfg_pull_none_8ma>; 1972 }; 1973 1974 emmc_cmd: emmc-cmd { 1975 rockchip,pins = 1976 <1 RK_PB2 2 &pcfg_pull_up_8ma>; 1977 }; 1978 1979 emmc_rstnout: emmc-rstnout { 1980 rockchip,pins = 1981 <1 RK_PB3 2 &pcfg_pull_none>; 1982 }; 1983 1984 emmc_bus1: emmc-bus1 { 1985 rockchip,pins = 1986 <1 RK_PA0 2 &pcfg_pull_up_8ma>; 1987 }; 1988 1989 emmc_bus4: emmc-bus4 { 1990 rockchip,pins = 1991 <1 RK_PA0 2 &pcfg_pull_up_8ma>, 1992 <1 RK_PA1 2 &pcfg_pull_up_8ma>, 1993 <1 RK_PA2 2 &pcfg_pull_up_8ma>, 1994 <1 RK_PA3 2 &pcfg_pull_up_8ma>; 1995 }; 1996 1997 emmc_bus8: emmc-bus8 { 1998 rockchip,pins = 1999 <1 RK_PA0 2 &pcfg_pull_up_8ma>, 2000 <1 RK_PA1 2 &pcfg_pull_up_8ma>, 2001 <1 RK_PA2 2 &pcfg_pull_up_8ma>, 2002 <1 RK_PA3 2 &pcfg_pull_up_8ma>, 2003 <1 RK_PA4 2 &pcfg_pull_up_8ma>, 2004 <1 RK_PA5 2 &pcfg_pull_up_8ma>, 2005 <1 RK_PA6 2 &pcfg_pull_up_8ma>, 2006 <1 RK_PA7 2 &pcfg_pull_up_8ma>; 2007 }; 2008 }; 2009 2010 flash { 2011 flash_cs0: flash-cs0 { 2012 rockchip,pins = 2013 <1 RK_PB0 1 &pcfg_pull_none>; 2014 }; 2015 2016 flash_rdy: flash-rdy { 2017 rockchip,pins = 2018 <1 RK_PB1 1 &pcfg_pull_none>; 2019 }; 2020 2021 flash_dqs: flash-dqs { 2022 rockchip,pins = 2023 <1 RK_PB2 1 &pcfg_pull_none>; 2024 }; 2025 2026 flash_ale: flash-ale { 2027 rockchip,pins = 2028 <1 RK_PB3 1 &pcfg_pull_none>; 2029 }; 2030 2031 flash_cle: flash-cle { 2032 rockchip,pins = 2033 <1 RK_PB4 1 &pcfg_pull_none>; 2034 }; 2035 2036 flash_wrn: flash-wrn { 2037 rockchip,pins = 2038 <1 RK_PB5 1 &pcfg_pull_none>; 2039 }; 2040 2041 flash_csl: flash-csl { 2042 rockchip,pins = 2043 <1 RK_PB6 1 &pcfg_pull_none>; 2044 }; 2045 2046 flash_rdn: flash-rdn { 2047 rockchip,pins = 2048 <1 RK_PB7 1 &pcfg_pull_none>; 2049 }; 2050 2051 flash_bus8: flash-bus8 { 2052 rockchip,pins = 2053 <1 RK_PA0 1 &pcfg_pull_up_12ma>, 2054 <1 RK_PA1 1 &pcfg_pull_up_12ma>, 2055 <1 RK_PA2 1 &pcfg_pull_up_12ma>, 2056 <1 RK_PA3 1 &pcfg_pull_up_12ma>, 2057 <1 RK_PA4 1 &pcfg_pull_up_12ma>, 2058 <1 RK_PA5 1 &pcfg_pull_up_12ma>, 2059 <1 RK_PA6 1 &pcfg_pull_up_12ma>, 2060 <1 RK_PA7 1 &pcfg_pull_up_12ma>; 2061 }; 2062 }; 2063 2064 sfc { 2065 sfc_bus4: sfc-bus4 { 2066 rockchip,pins = 2067 <1 RK_PA0 3 &pcfg_pull_none>, 2068 <1 RK_PA1 3 &pcfg_pull_none>, 2069 <1 RK_PA2 3 &pcfg_pull_none>, 2070 <1 RK_PA3 3 &pcfg_pull_none>; 2071 }; 2072 2073 sfc_bus2: sfc-bus2 { 2074 rockchip,pins = 2075 <1 RK_PA0 3 &pcfg_pull_none>, 2076 <1 RK_PA1 3 &pcfg_pull_none>; 2077 }; 2078 2079 sfc_cs0: sfc-cs0 { 2080 rockchip,pins = 2081 <1 RK_PA4 3 &pcfg_pull_none>; 2082 }; 2083 2084 sfc_clk: sfc-clk { 2085 rockchip,pins = 2086 <1 RK_PB1 3 &pcfg_pull_none>; 2087 }; 2088 }; 2089 2090 lcdc { 2091 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { 2092 rockchip,pins = 2093 <3 RK_PA0 1 &pcfg_pull_none_12ma>; 2094 }; 2095 2096 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { 2097 rockchip,pins = 2098 <3 RK_PA1 1 &pcfg_pull_none_12ma>; 2099 }; 2100 2101 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { 2102 rockchip,pins = 2103 <3 RK_PA2 1 &pcfg_pull_none_12ma>; 2104 }; 2105 2106 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin { 2107 rockchip,pins = 2108 <3 RK_PA3 1 &pcfg_pull_none_12ma>; 2109 }; 2110 2111 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins { 2112 rockchip,pins = 2113 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 2114 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2115 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 2116 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2117 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2118 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2119 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 2120 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 2121 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 2122 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 2123 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2124 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 2125 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2126 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2127 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2128 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2129 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ 2130 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ 2131 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2132 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ 2133 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ 2134 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ 2135 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ 2136 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ 2137 }; 2138 2139 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins { 2140 rockchip,pins = 2141 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 2142 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2143 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 2144 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2145 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2146 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2147 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 2148 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 2149 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 2150 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 2151 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2152 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 2153 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2154 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2155 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2156 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2157 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2158 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ 2159 }; 2160 2161 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins { 2162 rockchip,pins = 2163 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 2164 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2165 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 2166 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2167 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2168 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2169 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 2170 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 2171 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 2172 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 2173 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2174 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 2175 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2176 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2177 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2178 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ 2179 }; 2180 2181 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins { 2182 rockchip,pins = 2183 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2184 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2185 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2186 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2187 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2188 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2189 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2190 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2191 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2192 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ 2193 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ 2194 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2195 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ 2196 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ 2197 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ 2198 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ 2199 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ 2200 }; 2201 2202 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins { 2203 rockchip,pins = 2204 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2205 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2206 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2207 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2208 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2209 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2210 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2211 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2212 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2213 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2214 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ 2215 }; 2216 2217 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins { 2218 rockchip,pins = 2219 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2220 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2221 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2222 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2223 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2224 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2225 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2226 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2227 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ 2228 }; 2229 }; 2230 2231 pwm0 { 2232 pwm0_pin: pwm0-pin { 2233 rockchip,pins = 2234 <0 RK_PB7 1 &pcfg_pull_none>; 2235 }; 2236 }; 2237 2238 pwm1 { 2239 pwm1_pin: pwm1-pin { 2240 rockchip,pins = 2241 <0 RK_PC0 1 &pcfg_pull_none>; 2242 }; 2243 }; 2244 2245 pwm2 { 2246 pwm2_pin: pwm2-pin { 2247 rockchip,pins = 2248 <2 RK_PB5 1 &pcfg_pull_none>; 2249 }; 2250 }; 2251 2252 pwm3 { 2253 pwm3_pin: pwm3-pin { 2254 rockchip,pins = 2255 <0 RK_PC1 1 &pcfg_pull_none>; 2256 }; 2257 }; 2258 2259 pwm4 { 2260 pwm4_pin: pwm4-pin { 2261 rockchip,pins = 2262 <3 RK_PC2 3 &pcfg_pull_none>; 2263 }; 2264 }; 2265 2266 pwm5 { 2267 pwm5_pin: pwm5-pin { 2268 rockchip,pins = 2269 <3 RK_PC3 3 &pcfg_pull_none>; 2270 }; 2271 }; 2272 2273 pwm6 { 2274 pwm6_pin: pwm6-pin { 2275 rockchip,pins = 2276 <3 RK_PC4 3 &pcfg_pull_none>; 2277 }; 2278 }; 2279 2280 pwm7 { 2281 pwm7_pin: pwm7-pin { 2282 rockchip,pins = 2283 <3 RK_PC5 3 &pcfg_pull_none>; 2284 }; 2285 }; 2286 2287 gmac { 2288 rmii_pins: rmii-pins { 2289 rockchip,pins = 2290 <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */ 2291 <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */ 2292 <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */ 2293 <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */ 2294 <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */ 2295 <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */ 2296 <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */ 2297 <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */ 2298 <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */ 2299 }; 2300 2301 mac_refclk_12ma: mac-refclk-12ma { 2302 rockchip,pins = 2303 <2 RK_PB2 2 &pcfg_pull_none_12ma>; 2304 }; 2305 2306 mac_refclk: mac-refclk { 2307 rockchip,pins = 2308 <2 RK_PB2 2 &pcfg_pull_none>; 2309 }; 2310 }; 2311 2312 cif-m0 { 2313 cif_clkout_m0: cif-clkout-m0 { 2314 rockchip,pins = 2315 <2 RK_PB3 1 &pcfg_pull_none>; 2316 }; 2317 2318 dvp_d2d9_m0: dvp-d2d9-m0 { 2319 rockchip,pins = 2320 <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */ 2321 <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */ 2322 <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */ 2323 <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */ 2324 <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */ 2325 <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */ 2326 <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */ 2327 <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */ 2328 <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */ 2329 <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */ 2330 <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */ 2331 <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */ 2332 }; 2333 2334 dvp_d0d1_m0: dvp-d0d1-m0 { 2335 rockchip,pins = 2336 <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */ 2337 <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */ 2338 }; 2339 2340 dvp_d10d11_m0:d10-d11-m0 { 2341 rockchip,pins = 2342 <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */ 2343 <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */ 2344 }; 2345 }; 2346 2347 cif-m1 { 2348 cif_clkout_m1: cif-clkout-m1 { 2349 rockchip,pins = 2350 <3 RK_PD0 3 &pcfg_pull_none>; 2351 }; 2352 2353 dvp_d2d9_m1: dvp-d2d9-m1 { 2354 rockchip,pins = 2355 <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */ 2356 <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */ 2357 <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */ 2358 <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */ 2359 <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */ 2360 <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */ 2361 <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */ 2362 <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */ 2363 <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */ 2364 <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */ 2365 <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */ 2366 <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */ 2367 }; 2368 2369 dvp_d0d1_m1: dvp-d0d1-m1 { 2370 rockchip,pins = 2371 <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */ 2372 <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */ 2373 }; 2374 2375 dvp_d10d11_m1:d10-d11-m1 { 2376 rockchip,pins = 2377 <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */ 2378 <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */ 2379 }; 2380 }; 2381 2382 isp { 2383 isp_prelight: isp-prelight { 2384 rockchip,pins = 2385 <3 RK_PD1 4 &pcfg_pull_none>; 2386 }; 2387 }; 2388 }; 2389};