rk3328.dtsi (48170B)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3328-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3328-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,rk3328"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 serial0 = &uart0; 24 serial1 = &uart1; 25 serial2 = &uart2; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 ethernet0 = &gmac2io; 31 ethernet1 = &gmac2phy; 32 }; 33 34 cpus { 35 #address-cells = <2>; 36 #size-cells = <0>; 37 38 cpu0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a53"; 41 reg = <0x0 0x0>; 42 clocks = <&cru ARMCLK>; 43 #cooling-cells = <2>; 44 cpu-idle-states = <&CPU_SLEEP>; 45 dynamic-power-coefficient = <120>; 46 enable-method = "psci"; 47 next-level-cache = <&l2>; 48 operating-points-v2 = <&cpu0_opp_table>; 49 }; 50 51 cpu1: cpu@1 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 reg = <0x0 0x1>; 55 clocks = <&cru ARMCLK>; 56 #cooling-cells = <2>; 57 cpu-idle-states = <&CPU_SLEEP>; 58 dynamic-power-coefficient = <120>; 59 enable-method = "psci"; 60 next-level-cache = <&l2>; 61 operating-points-v2 = <&cpu0_opp_table>; 62 }; 63 64 cpu2: cpu@2 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a53"; 67 reg = <0x0 0x2>; 68 clocks = <&cru ARMCLK>; 69 #cooling-cells = <2>; 70 cpu-idle-states = <&CPU_SLEEP>; 71 dynamic-power-coefficient = <120>; 72 enable-method = "psci"; 73 next-level-cache = <&l2>; 74 operating-points-v2 = <&cpu0_opp_table>; 75 }; 76 77 cpu3: cpu@3 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a53"; 80 reg = <0x0 0x3>; 81 clocks = <&cru ARMCLK>; 82 #cooling-cells = <2>; 83 cpu-idle-states = <&CPU_SLEEP>; 84 dynamic-power-coefficient = <120>; 85 enable-method = "psci"; 86 next-level-cache = <&l2>; 87 operating-points-v2 = <&cpu0_opp_table>; 88 }; 89 90 idle-states { 91 entry-method = "psci"; 92 93 CPU_SLEEP: cpu-sleep { 94 compatible = "arm,idle-state"; 95 local-timer-stop; 96 arm,psci-suspend-param = <0x0010000>; 97 entry-latency-us = <120>; 98 exit-latency-us = <250>; 99 min-residency-us = <900>; 100 }; 101 }; 102 103 l2: l2-cache0 { 104 compatible = "cache"; 105 }; 106 }; 107 108 cpu0_opp_table: opp-table-0 { 109 compatible = "operating-points-v2"; 110 opp-shared; 111 112 opp-408000000 { 113 opp-hz = /bits/ 64 <408000000>; 114 opp-microvolt = <950000>; 115 clock-latency-ns = <40000>; 116 opp-suspend; 117 }; 118 opp-600000000 { 119 opp-hz = /bits/ 64 <600000000>; 120 opp-microvolt = <950000>; 121 clock-latency-ns = <40000>; 122 }; 123 opp-816000000 { 124 opp-hz = /bits/ 64 <816000000>; 125 opp-microvolt = <1000000>; 126 clock-latency-ns = <40000>; 127 }; 128 opp-1008000000 { 129 opp-hz = /bits/ 64 <1008000000>; 130 opp-microvolt = <1100000>; 131 clock-latency-ns = <40000>; 132 }; 133 opp-1200000000 { 134 opp-hz = /bits/ 64 <1200000000>; 135 opp-microvolt = <1225000>; 136 clock-latency-ns = <40000>; 137 }; 138 opp-1296000000 { 139 opp-hz = /bits/ 64 <1296000000>; 140 opp-microvolt = <1300000>; 141 clock-latency-ns = <40000>; 142 }; 143 }; 144 145 analog_sound: analog-sound { 146 compatible = "simple-audio-card"; 147 simple-audio-card,format = "i2s"; 148 simple-audio-card,mclk-fs = <256>; 149 simple-audio-card,name = "Analog"; 150 status = "disabled"; 151 152 simple-audio-card,cpu { 153 sound-dai = <&i2s1>; 154 }; 155 156 simple-audio-card,codec { 157 sound-dai = <&codec>; 158 }; 159 }; 160 161 arm-pmu { 162 compatible = "arm,cortex-a53-pmu"; 163 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 167 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 168 }; 169 170 display_subsystem: display-subsystem { 171 compatible = "rockchip,display-subsystem"; 172 ports = <&vop_out>; 173 }; 174 175 hdmi_sound: hdmi-sound { 176 compatible = "simple-audio-card"; 177 simple-audio-card,format = "i2s"; 178 simple-audio-card,mclk-fs = <128>; 179 simple-audio-card,name = "HDMI"; 180 status = "disabled"; 181 182 simple-audio-card,cpu { 183 sound-dai = <&i2s0>; 184 }; 185 186 simple-audio-card,codec { 187 sound-dai = <&hdmi>; 188 }; 189 }; 190 191 psci { 192 compatible = "arm,psci-1.0", "arm,psci-0.2"; 193 method = "smc"; 194 }; 195 196 timer { 197 compatible = "arm,armv8-timer"; 198 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 199 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 200 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 201 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 202 }; 203 204 xin24m: xin24m { 205 compatible = "fixed-clock"; 206 #clock-cells = <0>; 207 clock-frequency = <24000000>; 208 clock-output-names = "xin24m"; 209 }; 210 211 i2s0: i2s@ff000000 { 212 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 213 reg = <0x0 0xff000000 0x0 0x1000>; 214 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; 216 clock-names = "i2s_clk", "i2s_hclk"; 217 dmas = <&dmac 11>, <&dmac 12>; 218 dma-names = "tx", "rx"; 219 #sound-dai-cells = <0>; 220 status = "disabled"; 221 }; 222 223 i2s1: i2s@ff010000 { 224 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 225 reg = <0x0 0xff010000 0x0 0x1000>; 226 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 227 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; 228 clock-names = "i2s_clk", "i2s_hclk"; 229 dmas = <&dmac 14>, <&dmac 15>; 230 dma-names = "tx", "rx"; 231 #sound-dai-cells = <0>; 232 status = "disabled"; 233 }; 234 235 i2s2: i2s@ff020000 { 236 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; 237 reg = <0x0 0xff020000 0x0 0x1000>; 238 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; 240 clock-names = "i2s_clk", "i2s_hclk"; 241 dmas = <&dmac 0>, <&dmac 1>; 242 dma-names = "tx", "rx"; 243 #sound-dai-cells = <0>; 244 status = "disabled"; 245 }; 246 247 spdif: spdif@ff030000 { 248 compatible = "rockchip,rk3328-spdif"; 249 reg = <0x0 0xff030000 0x0 0x1000>; 250 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; 252 clock-names = "mclk", "hclk"; 253 dmas = <&dmac 10>; 254 dma-names = "tx"; 255 pinctrl-names = "default"; 256 pinctrl-0 = <&spdifm2_tx>; 257 #sound-dai-cells = <0>; 258 status = "disabled"; 259 }; 260 261 pdm: pdm@ff040000 { 262 compatible = "rockchip,pdm"; 263 reg = <0x0 0xff040000 0x0 0x1000>; 264 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; 265 clock-names = "pdm_clk", "pdm_hclk"; 266 dmas = <&dmac 16>; 267 dma-names = "rx"; 268 pinctrl-names = "default", "sleep"; 269 pinctrl-0 = <&pdmm0_clk 270 &pdmm0_sdi0 271 &pdmm0_sdi1 272 &pdmm0_sdi2 273 &pdmm0_sdi3>; 274 pinctrl-1 = <&pdmm0_clk_sleep 275 &pdmm0_sdi0_sleep 276 &pdmm0_sdi1_sleep 277 &pdmm0_sdi2_sleep 278 &pdmm0_sdi3_sleep>; 279 status = "disabled"; 280 }; 281 282 grf: syscon@ff100000 { 283 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 284 reg = <0x0 0xff100000 0x0 0x1000>; 285 286 io_domains: io-domains { 287 compatible = "rockchip,rk3328-io-voltage-domain"; 288 status = "disabled"; 289 }; 290 291 grf_gpio: gpio { 292 compatible = "rockchip,rk3328-grf-gpio"; 293 gpio-controller; 294 #gpio-cells = <2>; 295 }; 296 297 power: power-controller { 298 compatible = "rockchip,rk3328-power-controller"; 299 #power-domain-cells = <1>; 300 #address-cells = <1>; 301 #size-cells = <0>; 302 303 power-domain@RK3328_PD_HEVC { 304 reg = <RK3328_PD_HEVC>; 305 #power-domain-cells = <0>; 306 }; 307 power-domain@RK3328_PD_VIDEO { 308 reg = <RK3328_PD_VIDEO>; 309 clocks = <&cru ACLK_RKVDEC>, 310 <&cru HCLK_RKVDEC>, 311 <&cru SCLK_VDEC_CABAC>, 312 <&cru SCLK_VDEC_CORE>; 313 #power-domain-cells = <0>; 314 }; 315 power-domain@RK3328_PD_VPU { 316 reg = <RK3328_PD_VPU>; 317 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 318 #power-domain-cells = <0>; 319 }; 320 }; 321 322 reboot-mode { 323 compatible = "syscon-reboot-mode"; 324 offset = <0x5c8>; 325 mode-normal = <BOOT_NORMAL>; 326 mode-recovery = <BOOT_RECOVERY>; 327 mode-bootloader = <BOOT_FASTBOOT>; 328 mode-loader = <BOOT_BL_DOWNLOAD>; 329 }; 330 }; 331 332 uart0: serial@ff110000 { 333 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 334 reg = <0x0 0xff110000 0x0 0x100>; 335 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 337 clock-names = "baudclk", "apb_pclk"; 338 dmas = <&dmac 2>, <&dmac 3>; 339 dma-names = "tx", "rx"; 340 pinctrl-names = "default"; 341 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 342 reg-io-width = <4>; 343 reg-shift = <2>; 344 status = "disabled"; 345 }; 346 347 uart1: serial@ff120000 { 348 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 349 reg = <0x0 0xff120000 0x0 0x100>; 350 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 352 clock-names = "baudclk", "apb_pclk"; 353 dmas = <&dmac 4>, <&dmac 5>; 354 dma-names = "tx", "rx"; 355 pinctrl-names = "default"; 356 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 357 reg-io-width = <4>; 358 reg-shift = <2>; 359 status = "disabled"; 360 }; 361 362 uart2: serial@ff130000 { 363 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; 364 reg = <0x0 0xff130000 0x0 0x100>; 365 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 367 clock-names = "baudclk", "apb_pclk"; 368 dmas = <&dmac 6>, <&dmac 7>; 369 dma-names = "tx", "rx"; 370 pinctrl-names = "default"; 371 pinctrl-0 = <&uart2m1_xfer>; 372 reg-io-width = <4>; 373 reg-shift = <2>; 374 status = "disabled"; 375 }; 376 377 i2c0: i2c@ff150000 { 378 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 379 reg = <0x0 0xff150000 0x0 0x1000>; 380 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 381 #address-cells = <1>; 382 #size-cells = <0>; 383 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 384 clock-names = "i2c", "pclk"; 385 pinctrl-names = "default"; 386 pinctrl-0 = <&i2c0_xfer>; 387 status = "disabled"; 388 }; 389 390 i2c1: i2c@ff160000 { 391 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 392 reg = <0x0 0xff160000 0x0 0x1000>; 393 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 397 clock-names = "i2c", "pclk"; 398 pinctrl-names = "default"; 399 pinctrl-0 = <&i2c1_xfer>; 400 status = "disabled"; 401 }; 402 403 i2c2: i2c@ff170000 { 404 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 405 reg = <0x0 0xff170000 0x0 0x1000>; 406 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 407 #address-cells = <1>; 408 #size-cells = <0>; 409 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 410 clock-names = "i2c", "pclk"; 411 pinctrl-names = "default"; 412 pinctrl-0 = <&i2c2_xfer>; 413 status = "disabled"; 414 }; 415 416 i2c3: i2c@ff180000 { 417 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; 418 reg = <0x0 0xff180000 0x0 0x1000>; 419 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 420 #address-cells = <1>; 421 #size-cells = <0>; 422 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 423 clock-names = "i2c", "pclk"; 424 pinctrl-names = "default"; 425 pinctrl-0 = <&i2c3_xfer>; 426 status = "disabled"; 427 }; 428 429 spi0: spi@ff190000 { 430 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; 431 reg = <0x0 0xff190000 0x0 0x1000>; 432 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 433 #address-cells = <1>; 434 #size-cells = <0>; 435 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 436 clock-names = "spiclk", "apb_pclk"; 437 dmas = <&dmac 8>, <&dmac 9>; 438 dma-names = "tx", "rx"; 439 pinctrl-names = "default"; 440 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; 441 status = "disabled"; 442 }; 443 444 wdt: watchdog@ff1a0000 { 445 compatible = "rockchip,rk3328-wdt", "snps,dw-wdt"; 446 reg = <0x0 0xff1a0000 0x0 0x100>; 447 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&cru PCLK_WDT>; 449 }; 450 451 pwm0: pwm@ff1b0000 { 452 compatible = "rockchip,rk3328-pwm"; 453 reg = <0x0 0xff1b0000 0x0 0x10>; 454 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 455 clock-names = "pwm", "pclk"; 456 pinctrl-names = "default"; 457 pinctrl-0 = <&pwm0_pin>; 458 #pwm-cells = <3>; 459 status = "disabled"; 460 }; 461 462 pwm1: pwm@ff1b0010 { 463 compatible = "rockchip,rk3328-pwm"; 464 reg = <0x0 0xff1b0010 0x0 0x10>; 465 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 466 clock-names = "pwm", "pclk"; 467 pinctrl-names = "default"; 468 pinctrl-0 = <&pwm1_pin>; 469 #pwm-cells = <3>; 470 status = "disabled"; 471 }; 472 473 pwm2: pwm@ff1b0020 { 474 compatible = "rockchip,rk3328-pwm"; 475 reg = <0x0 0xff1b0020 0x0 0x10>; 476 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 477 clock-names = "pwm", "pclk"; 478 pinctrl-names = "default"; 479 pinctrl-0 = <&pwm2_pin>; 480 #pwm-cells = <3>; 481 status = "disabled"; 482 }; 483 484 pwm3: pwm@ff1b0030 { 485 compatible = "rockchip,rk3328-pwm"; 486 reg = <0x0 0xff1b0030 0x0 0x10>; 487 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 488 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 489 clock-names = "pwm", "pclk"; 490 pinctrl-names = "default"; 491 pinctrl-0 = <&pwmir_pin>; 492 #pwm-cells = <3>; 493 status = "disabled"; 494 }; 495 496 dmac: dma-controller@ff1f0000 { 497 compatible = "arm,pl330", "arm,primecell"; 498 reg = <0x0 0xff1f0000 0x0 0x4000>; 499 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 501 arm,pl330-periph-burst; 502 clocks = <&cru ACLK_DMAC>; 503 clock-names = "apb_pclk"; 504 #dma-cells = <1>; 505 }; 506 507 thermal-zones { 508 soc_thermal: soc-thermal { 509 polling-delay-passive = <20>; 510 polling-delay = <1000>; 511 sustainable-power = <1000>; 512 513 thermal-sensors = <&tsadc 0>; 514 515 trips { 516 threshold: trip-point0 { 517 temperature = <70000>; 518 hysteresis = <2000>; 519 type = "passive"; 520 }; 521 target: trip-point1 { 522 temperature = <85000>; 523 hysteresis = <2000>; 524 type = "passive"; 525 }; 526 soc_crit: soc-crit { 527 temperature = <95000>; 528 hysteresis = <2000>; 529 type = "critical"; 530 }; 531 }; 532 533 cooling-maps { 534 map0 { 535 trip = <&target>; 536 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 537 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 538 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 539 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 540 contribution = <4096>; 541 }; 542 }; 543 }; 544 545 }; 546 547 tsadc: tsadc@ff250000 { 548 compatible = "rockchip,rk3328-tsadc"; 549 reg = <0x0 0xff250000 0x0 0x100>; 550 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 551 assigned-clocks = <&cru SCLK_TSADC>; 552 assigned-clock-rates = <50000>; 553 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 554 clock-names = "tsadc", "apb_pclk"; 555 pinctrl-names = "init", "default", "sleep"; 556 pinctrl-0 = <&otp_pin>; 557 pinctrl-1 = <&otp_out>; 558 pinctrl-2 = <&otp_pin>; 559 resets = <&cru SRST_TSADC>; 560 reset-names = "tsadc-apb"; 561 rockchip,grf = <&grf>; 562 rockchip,hw-tshut-temp = <100000>; 563 #thermal-sensor-cells = <1>; 564 status = "disabled"; 565 }; 566 567 efuse: efuse@ff260000 { 568 compatible = "rockchip,rk3328-efuse"; 569 reg = <0x0 0xff260000 0x0 0x50>; 570 #address-cells = <1>; 571 #size-cells = <1>; 572 clocks = <&cru SCLK_EFUSE>; 573 clock-names = "pclk_efuse"; 574 rockchip,efuse-size = <0x20>; 575 576 /* Data cells */ 577 efuse_id: id@7 { 578 reg = <0x07 0x10>; 579 }; 580 cpu_leakage: cpu-leakage@17 { 581 reg = <0x17 0x1>; 582 }; 583 logic_leakage: logic-leakage@19 { 584 reg = <0x19 0x1>; 585 }; 586 efuse_cpu_version: cpu-version@1a { 587 reg = <0x1a 0x1>; 588 bits = <3 3>; 589 }; 590 }; 591 592 saradc: adc@ff280000 { 593 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; 594 reg = <0x0 0xff280000 0x0 0x100>; 595 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 596 #io-channel-cells = <1>; 597 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 598 clock-names = "saradc", "apb_pclk"; 599 resets = <&cru SRST_SARADC_P>; 600 reset-names = "saradc-apb"; 601 status = "disabled"; 602 }; 603 604 gpu: gpu@ff300000 { 605 compatible = "rockchip,rk3328-mali", "arm,mali-450"; 606 reg = <0x0 0xff300000 0x0 0x30000>; 607 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 614 interrupt-names = "gp", 615 "gpmmu", 616 "pp", 617 "pp0", 618 "ppmmu0", 619 "pp1", 620 "ppmmu1"; 621 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; 622 clock-names = "bus", "core"; 623 resets = <&cru SRST_GPU_A>; 624 }; 625 626 h265e_mmu: iommu@ff330200 { 627 compatible = "rockchip,iommu"; 628 reg = <0x0 0xff330200 0 0x100>; 629 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 630 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>; 631 clock-names = "aclk", "iface"; 632 #iommu-cells = <0>; 633 status = "disabled"; 634 }; 635 636 vepu_mmu: iommu@ff340800 { 637 compatible = "rockchip,iommu"; 638 reg = <0x0 0xff340800 0x0 0x40>; 639 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 640 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 641 clock-names = "aclk", "iface"; 642 #iommu-cells = <0>; 643 status = "disabled"; 644 }; 645 646 vpu: video-codec@ff350000 { 647 compatible = "rockchip,rk3328-vpu"; 648 reg = <0x0 0xff350000 0x0 0x800>; 649 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 650 interrupt-names = "vdpu"; 651 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 652 clock-names = "aclk", "hclk"; 653 iommus = <&vpu_mmu>; 654 power-domains = <&power RK3328_PD_VPU>; 655 }; 656 657 vpu_mmu: iommu@ff350800 { 658 compatible = "rockchip,iommu"; 659 reg = <0x0 0xff350800 0x0 0x40>; 660 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 661 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 662 clock-names = "aclk", "iface"; 663 #iommu-cells = <0>; 664 power-domains = <&power RK3328_PD_VPU>; 665 }; 666 667 vdec: video-codec@ff360000 { 668 compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec"; 669 reg = <0x0 0xff360000 0x0 0x400>; 670 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 671 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, 672 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; 673 clock-names = "axi", "ahb", "cabac", "core"; 674 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>, 675 <&cru SCLK_VDEC_CORE>; 676 assigned-clock-rates = <400000000>, <400000000>, <300000000>; 677 iommus = <&vdec_mmu>; 678 power-domains = <&power RK3328_PD_VIDEO>; 679 }; 680 681 vdec_mmu: iommu@ff360480 { 682 compatible = "rockchip,iommu"; 683 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; 684 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 685 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; 686 clock-names = "aclk", "iface"; 687 #iommu-cells = <0>; 688 power-domains = <&power RK3328_PD_VIDEO>; 689 }; 690 691 vop: vop@ff370000 { 692 compatible = "rockchip,rk3328-vop"; 693 reg = <0x0 0xff370000 0x0 0x3efc>; 694 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 695 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>; 696 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 697 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; 698 reset-names = "axi", "ahb", "dclk"; 699 iommus = <&vop_mmu>; 700 status = "disabled"; 701 702 vop_out: port { 703 #address-cells = <1>; 704 #size-cells = <0>; 705 706 vop_out_hdmi: endpoint@0 { 707 reg = <0>; 708 remote-endpoint = <&hdmi_in_vop>; 709 }; 710 }; 711 }; 712 713 vop_mmu: iommu@ff373f00 { 714 compatible = "rockchip,iommu"; 715 reg = <0x0 0xff373f00 0x0 0x100>; 716 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 718 clock-names = "aclk", "iface"; 719 #iommu-cells = <0>; 720 status = "disabled"; 721 }; 722 723 hdmi: hdmi@ff3c0000 { 724 compatible = "rockchip,rk3328-dw-hdmi"; 725 reg = <0x0 0xff3c0000 0x0 0x20000>; 726 reg-io-width = <4>; 727 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 729 clocks = <&cru PCLK_HDMI>, 730 <&cru SCLK_HDMI_SFC>, 731 <&cru SCLK_RTC32K>; 732 clock-names = "iahb", 733 "isfr", 734 "cec"; 735 phys = <&hdmiphy>; 736 phy-names = "hdmi"; 737 pinctrl-names = "default"; 738 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>; 739 rockchip,grf = <&grf>; 740 #sound-dai-cells = <0>; 741 status = "disabled"; 742 743 ports { 744 hdmi_in: port { 745 hdmi_in_vop: endpoint { 746 remote-endpoint = <&vop_out_hdmi>; 747 }; 748 }; 749 }; 750 }; 751 752 codec: codec@ff410000 { 753 compatible = "rockchip,rk3328-codec"; 754 reg = <0x0 0xff410000 0x0 0x1000>; 755 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; 756 clock-names = "pclk", "mclk"; 757 rockchip,grf = <&grf>; 758 #sound-dai-cells = <0>; 759 status = "disabled"; 760 }; 761 762 hdmiphy: phy@ff430000 { 763 compatible = "rockchip,rk3328-hdmi-phy"; 764 reg = <0x0 0xff430000 0x0 0x10000>; 765 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 766 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>; 767 clock-names = "sysclk", "refoclk", "refpclk"; 768 clock-output-names = "hdmi_phy"; 769 #clock-cells = <0>; 770 nvmem-cells = <&efuse_cpu_version>; 771 nvmem-cell-names = "cpu-version"; 772 #phy-cells = <0>; 773 status = "disabled"; 774 }; 775 776 cru: clock-controller@ff440000 { 777 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; 778 reg = <0x0 0xff440000 0x0 0x1000>; 779 rockchip,grf = <&grf>; 780 #clock-cells = <1>; 781 #reset-cells = <1>; 782 assigned-clocks = 783 /* 784 * CPLL should run at 1200, but that is to high for 785 * the initial dividers of most of its children. 786 * We need set cpll child clk div first, 787 * and then set the cpll frequency. 788 */ 789 <&cru DCLK_LCDC>, <&cru SCLK_PDM>, 790 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, 791 <&cru SCLK_UART1>, <&cru SCLK_UART2>, 792 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 793 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, 794 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, 795 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, 796 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, 797 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, 798 <&cru SCLK_SDIO>, <&cru SCLK_TSP>, 799 <&cru SCLK_WIFI>, <&cru ARMCLK>, 800 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 801 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, 802 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 803 <&cru HCLK_PERI>, <&cru PCLK_PERI>, 804 <&cru SCLK_RTC32K>; 805 assigned-clock-parents = 806 <&cru HDMIPHY>, <&cru PLL_APLL>, 807 <&cru PLL_GPLL>, <&xin24m>, 808 <&xin24m>, <&xin24m>; 809 assigned-clock-rates = 810 <0>, <61440000>, 811 <0>, <24000000>, 812 <24000000>, <24000000>, 813 <15000000>, <15000000>, 814 <100000000>, <100000000>, 815 <100000000>, <100000000>, 816 <50000000>, <100000000>, 817 <100000000>, <100000000>, 818 <50000000>, <50000000>, 819 <50000000>, <50000000>, 820 <24000000>, <600000000>, 821 <491520000>, <1200000000>, 822 <150000000>, <75000000>, 823 <75000000>, <150000000>, 824 <75000000>, <75000000>, 825 <32768>; 826 }; 827 828 usb2phy_grf: syscon@ff450000 { 829 compatible = "rockchip,rk3328-usb2phy-grf", "syscon", 830 "simple-mfd"; 831 reg = <0x0 0xff450000 0x0 0x10000>; 832 #address-cells = <1>; 833 #size-cells = <1>; 834 835 u2phy: usb2phy@100 { 836 compatible = "rockchip,rk3328-usb2phy"; 837 reg = <0x100 0x10>; 838 clocks = <&xin24m>; 839 clock-names = "phyclk"; 840 clock-output-names = "usb480m_phy"; 841 #clock-cells = <0>; 842 assigned-clocks = <&cru USB480M>; 843 assigned-clock-parents = <&u2phy>; 844 status = "disabled"; 845 846 u2phy_otg: otg-port { 847 #phy-cells = <0>; 848 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 849 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 850 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 851 interrupt-names = "otg-bvalid", "otg-id", 852 "linestate"; 853 status = "disabled"; 854 }; 855 856 u2phy_host: host-port { 857 #phy-cells = <0>; 858 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 859 interrupt-names = "linestate"; 860 status = "disabled"; 861 }; 862 }; 863 }; 864 865 sdmmc: mmc@ff500000 { 866 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 867 reg = <0x0 0xff500000 0x0 0x4000>; 868 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 869 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 870 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 871 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 872 fifo-depth = <0x100>; 873 max-frequency = <150000000>; 874 status = "disabled"; 875 }; 876 877 sdio: mmc@ff510000 { 878 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 879 reg = <0x0 0xff510000 0x0 0x4000>; 880 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 881 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 882 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 883 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 884 fifo-depth = <0x100>; 885 max-frequency = <150000000>; 886 status = "disabled"; 887 }; 888 889 emmc: mmc@ff520000 { 890 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; 891 reg = <0x0 0xff520000 0x0 0x4000>; 892 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 893 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 894 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 895 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 896 fifo-depth = <0x100>; 897 max-frequency = <150000000>; 898 status = "disabled"; 899 }; 900 901 gmac2io: ethernet@ff540000 { 902 compatible = "rockchip,rk3328-gmac"; 903 reg = <0x0 0xff540000 0x0 0x10000>; 904 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 905 interrupt-names = "macirq"; 906 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, 907 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, 908 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, 909 <&cru PCLK_MAC2IO>; 910 clock-names = "stmmaceth", "mac_clk_rx", 911 "mac_clk_tx", "clk_mac_ref", 912 "clk_mac_refout", "aclk_mac", 913 "pclk_mac"; 914 resets = <&cru SRST_GMAC2IO_A>; 915 reset-names = "stmmaceth"; 916 rockchip,grf = <&grf>; 917 snps,txpbl = <0x4>; 918 status = "disabled"; 919 }; 920 921 gmac2phy: ethernet@ff550000 { 922 compatible = "rockchip,rk3328-gmac"; 923 reg = <0x0 0xff550000 0x0 0x10000>; 924 rockchip,grf = <&grf>; 925 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 926 interrupt-names = "macirq"; 927 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, 928 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, 929 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, 930 <&cru SCLK_MAC2PHY_OUT>; 931 clock-names = "stmmaceth", "mac_clk_rx", 932 "mac_clk_tx", "clk_mac_ref", 933 "aclk_mac", "pclk_mac", 934 "clk_macphy"; 935 resets = <&cru SRST_GMAC2PHY_A>; 936 reset-names = "stmmaceth"; 937 phy-mode = "rmii"; 938 phy-handle = <&phy>; 939 snps,txpbl = <0x4>; 940 clock_in_out = "output"; 941 status = "disabled"; 942 943 mdio { 944 compatible = "snps,dwmac-mdio"; 945 #address-cells = <1>; 946 #size-cells = <0>; 947 948 phy: ethernet-phy@0 { 949 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; 950 reg = <0>; 951 clocks = <&cru SCLK_MAC2PHY_OUT>; 952 resets = <&cru SRST_MACPHY>; 953 pinctrl-names = "default"; 954 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; 955 phy-is-integrated; 956 }; 957 }; 958 }; 959 960 usb20_otg: usb@ff580000 { 961 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", 962 "snps,dwc2"; 963 reg = <0x0 0xff580000 0x0 0x40000>; 964 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 965 clocks = <&cru HCLK_OTG>; 966 clock-names = "otg"; 967 dr_mode = "otg"; 968 g-np-tx-fifo-size = <16>; 969 g-rx-fifo-size = <280>; 970 g-tx-fifo-size = <256 128 128 64 32 16>; 971 phys = <&u2phy_otg>; 972 phy-names = "usb2-phy"; 973 status = "disabled"; 974 }; 975 976 usb_host0_ehci: usb@ff5c0000 { 977 compatible = "generic-ehci"; 978 reg = <0x0 0xff5c0000 0x0 0x10000>; 979 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 980 clocks = <&cru HCLK_HOST0>, <&u2phy>; 981 phys = <&u2phy_host>; 982 phy-names = "usb"; 983 status = "disabled"; 984 }; 985 986 usb_host0_ohci: usb@ff5d0000 { 987 compatible = "generic-ohci"; 988 reg = <0x0 0xff5d0000 0x0 0x10000>; 989 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 990 clocks = <&cru HCLK_HOST0>, <&u2phy>; 991 phys = <&u2phy_host>; 992 phy-names = "usb"; 993 status = "disabled"; 994 }; 995 996 usbdrd3: usb@ff600000 { 997 compatible = "rockchip,rk3328-dwc3", "snps,dwc3"; 998 reg = <0x0 0xff600000 0x0 0x100000>; 999 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1000 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>, 1001 <&cru ACLK_USB3OTG>; 1002 clock-names = "ref_clk", "suspend_clk", 1003 "bus_clk"; 1004 dr_mode = "otg"; 1005 phy_type = "utmi_wide"; 1006 snps,dis-del-phy-power-chg-quirk; 1007 snps,dis_enblslpm_quirk; 1008 snps,dis-tx-ipgap-linecheck-quirk; 1009 snps,dis-u2-freeclk-exists-quirk; 1010 snps,dis_u2_susphy_quirk; 1011 snps,dis_u3_susphy_quirk; 1012 status = "disabled"; 1013 }; 1014 1015 gic: interrupt-controller@ff811000 { 1016 compatible = "arm,gic-400"; 1017 #interrupt-cells = <3>; 1018 #address-cells = <0>; 1019 interrupt-controller; 1020 reg = <0x0 0xff811000 0 0x1000>, 1021 <0x0 0xff812000 0 0x2000>, 1022 <0x0 0xff814000 0 0x2000>, 1023 <0x0 0xff816000 0 0x2000>; 1024 interrupts = <GIC_PPI 9 1025 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1026 }; 1027 1028 pinctrl: pinctrl { 1029 compatible = "rockchip,rk3328-pinctrl"; 1030 rockchip,grf = <&grf>; 1031 #address-cells = <2>; 1032 #size-cells = <2>; 1033 ranges; 1034 1035 gpio0: gpio@ff210000 { 1036 compatible = "rockchip,gpio-bank"; 1037 reg = <0x0 0xff210000 0x0 0x100>; 1038 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1039 clocks = <&cru PCLK_GPIO0>; 1040 1041 gpio-controller; 1042 #gpio-cells = <2>; 1043 1044 interrupt-controller; 1045 #interrupt-cells = <2>; 1046 }; 1047 1048 gpio1: gpio@ff220000 { 1049 compatible = "rockchip,gpio-bank"; 1050 reg = <0x0 0xff220000 0x0 0x100>; 1051 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1052 clocks = <&cru PCLK_GPIO1>; 1053 1054 gpio-controller; 1055 #gpio-cells = <2>; 1056 1057 interrupt-controller; 1058 #interrupt-cells = <2>; 1059 }; 1060 1061 gpio2: gpio@ff230000 { 1062 compatible = "rockchip,gpio-bank"; 1063 reg = <0x0 0xff230000 0x0 0x100>; 1064 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1065 clocks = <&cru PCLK_GPIO2>; 1066 1067 gpio-controller; 1068 #gpio-cells = <2>; 1069 1070 interrupt-controller; 1071 #interrupt-cells = <2>; 1072 }; 1073 1074 gpio3: gpio@ff240000 { 1075 compatible = "rockchip,gpio-bank"; 1076 reg = <0x0 0xff240000 0x0 0x100>; 1077 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1078 clocks = <&cru PCLK_GPIO3>; 1079 1080 gpio-controller; 1081 #gpio-cells = <2>; 1082 1083 interrupt-controller; 1084 #interrupt-cells = <2>; 1085 }; 1086 1087 pcfg_pull_up: pcfg-pull-up { 1088 bias-pull-up; 1089 }; 1090 1091 pcfg_pull_down: pcfg-pull-down { 1092 bias-pull-down; 1093 }; 1094 1095 pcfg_pull_none: pcfg-pull-none { 1096 bias-disable; 1097 }; 1098 1099 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1100 bias-disable; 1101 drive-strength = <2>; 1102 }; 1103 1104 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1105 bias-pull-up; 1106 drive-strength = <2>; 1107 }; 1108 1109 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1110 bias-pull-up; 1111 drive-strength = <4>; 1112 }; 1113 1114 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1115 bias-disable; 1116 drive-strength = <4>; 1117 }; 1118 1119 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1120 bias-pull-down; 1121 drive-strength = <4>; 1122 }; 1123 1124 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1125 bias-disable; 1126 drive-strength = <8>; 1127 }; 1128 1129 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1130 bias-pull-up; 1131 drive-strength = <8>; 1132 }; 1133 1134 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1135 bias-disable; 1136 drive-strength = <12>; 1137 }; 1138 1139 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1140 bias-pull-up; 1141 drive-strength = <12>; 1142 }; 1143 1144 pcfg_output_high: pcfg-output-high { 1145 output-high; 1146 }; 1147 1148 pcfg_output_low: pcfg-output-low { 1149 output-low; 1150 }; 1151 1152 pcfg_input_high: pcfg-input-high { 1153 bias-pull-up; 1154 input-enable; 1155 }; 1156 1157 pcfg_input: pcfg-input { 1158 input-enable; 1159 }; 1160 1161 i2c0 { 1162 i2c0_xfer: i2c0-xfer { 1163 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>, 1164 <2 RK_PD1 1 &pcfg_pull_none>; 1165 }; 1166 }; 1167 1168 i2c1 { 1169 i2c1_xfer: i2c1-xfer { 1170 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>, 1171 <2 RK_PA5 2 &pcfg_pull_none>; 1172 }; 1173 }; 1174 1175 i2c2 { 1176 i2c2_xfer: i2c2-xfer { 1177 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>, 1178 <2 RK_PB6 1 &pcfg_pull_none>; 1179 }; 1180 }; 1181 1182 i2c3 { 1183 i2c3_xfer: i2c3-xfer { 1184 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>, 1185 <0 RK_PA6 2 &pcfg_pull_none>; 1186 }; 1187 i2c3_pins: i2c3-pins { 1188 rockchip,pins = 1189 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, 1190 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1191 }; 1192 }; 1193 1194 hdmi_i2c { 1195 hdmii2c_xfer: hdmii2c-xfer { 1196 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>, 1197 <0 RK_PA6 1 &pcfg_pull_none>; 1198 }; 1199 }; 1200 1201 pdm-0 { 1202 pdmm0_clk: pdmm0-clk { 1203 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; 1204 }; 1205 1206 pdmm0_fsync: pdmm0-fsync { 1207 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>; 1208 }; 1209 1210 pdmm0_sdi0: pdmm0-sdi0 { 1211 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; 1212 }; 1213 1214 pdmm0_sdi1: pdmm0-sdi1 { 1215 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>; 1216 }; 1217 1218 pdmm0_sdi2: pdmm0-sdi2 { 1219 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>; 1220 }; 1221 1222 pdmm0_sdi3: pdmm0-sdi3 { 1223 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>; 1224 }; 1225 1226 pdmm0_clk_sleep: pdmm0-clk-sleep { 1227 rockchip,pins = 1228 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>; 1229 }; 1230 1231 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep { 1232 rockchip,pins = 1233 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>; 1234 }; 1235 1236 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep { 1237 rockchip,pins = 1238 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>; 1239 }; 1240 1241 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep { 1242 rockchip,pins = 1243 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1244 }; 1245 1246 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep { 1247 rockchip,pins = 1248 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1249 }; 1250 1251 pdmm0_fsync_sleep: pdmm0-fsync-sleep { 1252 rockchip,pins = 1253 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1254 }; 1255 }; 1256 1257 tsadc { 1258 otp_pin: otp-pin { 1259 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1260 }; 1261 1262 otp_out: otp-out { 1263 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>; 1264 }; 1265 }; 1266 1267 uart0 { 1268 uart0_xfer: uart0-xfer { 1269 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, 1270 <1 RK_PB0 1 &pcfg_pull_up>; 1271 }; 1272 1273 uart0_cts: uart0-cts { 1274 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; 1275 }; 1276 1277 uart0_rts: uart0-rts { 1278 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>; 1279 }; 1280 1281 uart0_rts_pin: uart0-rts-pin { 1282 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 1283 }; 1284 }; 1285 1286 uart1 { 1287 uart1_xfer: uart1-xfer { 1288 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_none>, 1289 <3 RK_PA6 4 &pcfg_pull_up>; 1290 }; 1291 1292 uart1_cts: uart1-cts { 1293 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>; 1294 }; 1295 1296 uart1_rts: uart1-rts { 1297 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>; 1298 }; 1299 1300 uart1_rts_pin: uart1-rts-pin { 1301 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 1302 }; 1303 }; 1304 1305 uart2-0 { 1306 uart2m0_xfer: uart2m0-xfer { 1307 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>, 1308 <1 RK_PA1 2 &pcfg_pull_up>; 1309 }; 1310 }; 1311 1312 uart2-1 { 1313 uart2m1_xfer: uart2m1-xfer { 1314 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, 1315 <2 RK_PA1 1 &pcfg_pull_up>; 1316 }; 1317 }; 1318 1319 spi0-0 { 1320 spi0m0_clk: spi0m0-clk { 1321 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>; 1322 }; 1323 1324 spi0m0_cs0: spi0m0-cs0 { 1325 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; 1326 }; 1327 1328 spi0m0_tx: spi0m0-tx { 1329 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>; 1330 }; 1331 1332 spi0m0_rx: spi0m0-rx { 1333 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; 1334 }; 1335 1336 spi0m0_cs1: spi0m0-cs1 { 1337 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>; 1338 }; 1339 }; 1340 1341 spi0-1 { 1342 spi0m1_clk: spi0m1-clk { 1343 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>; 1344 }; 1345 1346 spi0m1_cs0: spi0m1-cs0 { 1347 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>; 1348 }; 1349 1350 spi0m1_tx: spi0m1-tx { 1351 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>; 1352 }; 1353 1354 spi0m1_rx: spi0m1-rx { 1355 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>; 1356 }; 1357 1358 spi0m1_cs1: spi0m1-cs1 { 1359 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>; 1360 }; 1361 }; 1362 1363 spi0-2 { 1364 spi0m2_clk: spi0m2-clk { 1365 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>; 1366 }; 1367 1368 spi0m2_cs0: spi0m2-cs0 { 1369 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>; 1370 }; 1371 1372 spi0m2_tx: spi0m2-tx { 1373 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>; 1374 }; 1375 1376 spi0m2_rx: spi0m2-rx { 1377 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>; 1378 }; 1379 }; 1380 1381 i2s1 { 1382 i2s1_mclk: i2s1-mclk { 1383 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>; 1384 }; 1385 1386 i2s1_sclk: i2s1-sclk { 1387 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>; 1388 }; 1389 1390 i2s1_lrckrx: i2s1-lrckrx { 1391 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>; 1392 }; 1393 1394 i2s1_lrcktx: i2s1-lrcktx { 1395 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>; 1396 }; 1397 1398 i2s1_sdi: i2s1-sdi { 1399 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>; 1400 }; 1401 1402 i2s1_sdo: i2s1-sdo { 1403 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; 1404 }; 1405 1406 i2s1_sdio1: i2s1-sdio1 { 1407 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>; 1408 }; 1409 1410 i2s1_sdio2: i2s1-sdio2 { 1411 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>; 1412 }; 1413 1414 i2s1_sdio3: i2s1-sdio3 { 1415 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; 1416 }; 1417 1418 i2s1_sleep: i2s1-sleep { 1419 rockchip,pins = 1420 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>, 1421 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>, 1422 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>, 1423 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>, 1424 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>, 1425 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>, 1426 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1427 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1428 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1429 }; 1430 }; 1431 1432 i2s2-0 { 1433 i2s2m0_mclk: i2s2m0-mclk { 1434 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1435 }; 1436 1437 i2s2m0_sclk: i2s2m0-sclk { 1438 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>; 1439 }; 1440 1441 i2s2m0_lrckrx: i2s2m0-lrckrx { 1442 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>; 1443 }; 1444 1445 i2s2m0_lrcktx: i2s2m0-lrcktx { 1446 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>; 1447 }; 1448 1449 i2s2m0_sdi: i2s2m0-sdi { 1450 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; 1451 }; 1452 1453 i2s2m0_sdo: i2s2m0-sdo { 1454 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; 1455 }; 1456 1457 i2s2m0_sleep: i2s2m0-sleep { 1458 rockchip,pins = 1459 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1460 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, 1461 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>, 1462 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>, 1463 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>, 1464 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1465 }; 1466 }; 1467 1468 i2s2-1 { 1469 i2s2m1_mclk: i2s2m1-mclk { 1470 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; 1471 }; 1472 1473 i2s2m1_sclk: i2s2m1-sclk { 1474 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>; 1475 }; 1476 1477 i2s2m1_lrckrx: i2sm1-lrckrx { 1478 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>; 1479 }; 1480 1481 i2s2m1_lrcktx: i2s2m1-lrcktx { 1482 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>; 1483 }; 1484 1485 i2s2m1_sdi: i2s2m1-sdi { 1486 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>; 1487 }; 1488 1489 i2s2m1_sdo: i2s2m1-sdo { 1490 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>; 1491 }; 1492 1493 i2s2m1_sleep: i2s2m1-sleep { 1494 rockchip,pins = 1495 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, 1496 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>, 1497 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>, 1498 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>, 1499 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>; 1500 }; 1501 }; 1502 1503 spdif-0 { 1504 spdifm0_tx: spdifm0-tx { 1505 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; 1506 }; 1507 }; 1508 1509 spdif-1 { 1510 spdifm1_tx: spdifm1-tx { 1511 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>; 1512 }; 1513 }; 1514 1515 spdif-2 { 1516 spdifm2_tx: spdifm2-tx { 1517 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; 1518 }; 1519 }; 1520 1521 sdmmc0-0 { 1522 sdmmc0m0_pwren: sdmmc0m0-pwren { 1523 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>; 1524 }; 1525 1526 sdmmc0m0_pin: sdmmc0m0-pin { 1527 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1528 }; 1529 }; 1530 1531 sdmmc0-1 { 1532 sdmmc0m1_pwren: sdmmc0m1-pwren { 1533 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; 1534 }; 1535 1536 sdmmc0m1_pin: sdmmc0m1-pin { 1537 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1538 }; 1539 }; 1540 1541 sdmmc0 { 1542 sdmmc0_clk: sdmmc0-clk { 1543 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>; 1544 }; 1545 1546 sdmmc0_cmd: sdmmc0-cmd { 1547 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>; 1548 }; 1549 1550 sdmmc0_dectn: sdmmc0-dectn { 1551 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; 1552 }; 1553 1554 sdmmc0_wrprt: sdmmc0-wrprt { 1555 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>; 1556 }; 1557 1558 sdmmc0_bus1: sdmmc0-bus1 { 1559 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>; 1560 }; 1561 1562 sdmmc0_bus4: sdmmc0-bus4 { 1563 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>, 1564 <1 RK_PA1 1 &pcfg_pull_up_8ma>, 1565 <1 RK_PA2 1 &pcfg_pull_up_8ma>, 1566 <1 RK_PA3 1 &pcfg_pull_up_8ma>; 1567 }; 1568 1569 sdmmc0_pins: sdmmc0-pins { 1570 rockchip,pins = 1571 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1572 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1573 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1574 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1575 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1576 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1577 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1578 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1579 }; 1580 }; 1581 1582 sdmmc0ext { 1583 sdmmc0ext_clk: sdmmc0ext-clk { 1584 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>; 1585 }; 1586 1587 sdmmc0ext_cmd: sdmmc0ext-cmd { 1588 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>; 1589 }; 1590 1591 sdmmc0ext_wrprt: sdmmc0ext-wrprt { 1592 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>; 1593 }; 1594 1595 sdmmc0ext_dectn: sdmmc0ext-dectn { 1596 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>; 1597 }; 1598 1599 sdmmc0ext_bus1: sdmmc0ext-bus1 { 1600 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>; 1601 }; 1602 1603 sdmmc0ext_bus4: sdmmc0ext-bus4 { 1604 rockchip,pins = 1605 <3 RK_PA4 3 &pcfg_pull_up_4ma>, 1606 <3 RK_PA5 3 &pcfg_pull_up_4ma>, 1607 <3 RK_PA6 3 &pcfg_pull_up_4ma>, 1608 <3 RK_PA7 3 &pcfg_pull_up_4ma>; 1609 }; 1610 1611 sdmmc0ext_pins: sdmmc0ext-pins { 1612 rockchip,pins = 1613 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1614 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1615 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1616 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1617 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1618 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1619 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1620 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1621 }; 1622 }; 1623 1624 sdmmc1 { 1625 sdmmc1_clk: sdmmc1-clk { 1626 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>; 1627 }; 1628 1629 sdmmc1_cmd: sdmmc1-cmd { 1630 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>; 1631 }; 1632 1633 sdmmc1_pwren: sdmmc1-pwren { 1634 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>; 1635 }; 1636 1637 sdmmc1_wrprt: sdmmc1-wrprt { 1638 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>; 1639 }; 1640 1641 sdmmc1_dectn: sdmmc1-dectn { 1642 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>; 1643 }; 1644 1645 sdmmc1_bus1: sdmmc1-bus1 { 1646 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>; 1647 }; 1648 1649 sdmmc1_bus4: sdmmc1-bus4 { 1650 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>, 1651 <1 RK_PB7 1 &pcfg_pull_up_8ma>, 1652 <1 RK_PC0 1 &pcfg_pull_up_8ma>, 1653 <1 RK_PC1 1 &pcfg_pull_up_8ma>; 1654 }; 1655 1656 sdmmc1_pins: sdmmc1-pins { 1657 rockchip,pins = 1658 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1659 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1660 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1661 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1662 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1663 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1664 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1665 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, 1666 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>; 1667 }; 1668 }; 1669 1670 emmc { 1671 emmc_clk: emmc-clk { 1672 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>; 1673 }; 1674 1675 emmc_cmd: emmc-cmd { 1676 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>; 1677 }; 1678 1679 emmc_pwren: emmc-pwren { 1680 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>; 1681 }; 1682 1683 emmc_rstnout: emmc-rstnout { 1684 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; 1685 }; 1686 1687 emmc_bus1: emmc-bus1 { 1688 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>; 1689 }; 1690 1691 emmc_bus4: emmc-bus4 { 1692 rockchip,pins = 1693 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1694 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1695 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1696 <2 RK_PD6 2 &pcfg_pull_up_12ma>; 1697 }; 1698 1699 emmc_bus8: emmc-bus8 { 1700 rockchip,pins = 1701 <0 RK_PA7 2 &pcfg_pull_up_12ma>, 1702 <2 RK_PD4 2 &pcfg_pull_up_12ma>, 1703 <2 RK_PD5 2 &pcfg_pull_up_12ma>, 1704 <2 RK_PD6 2 &pcfg_pull_up_12ma>, 1705 <2 RK_PD7 2 &pcfg_pull_up_12ma>, 1706 <3 RK_PC0 2 &pcfg_pull_up_12ma>, 1707 <3 RK_PC1 2 &pcfg_pull_up_12ma>, 1708 <3 RK_PC2 2 &pcfg_pull_up_12ma>; 1709 }; 1710 }; 1711 1712 pwm0 { 1713 pwm0_pin: pwm0-pin { 1714 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; 1715 }; 1716 }; 1717 1718 pwm1 { 1719 pwm1_pin: pwm1-pin { 1720 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>; 1721 }; 1722 }; 1723 1724 pwm2 { 1725 pwm2_pin: pwm2-pin { 1726 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; 1727 }; 1728 }; 1729 1730 pwmir { 1731 pwmir_pin: pwmir-pin { 1732 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; 1733 }; 1734 }; 1735 1736 gmac-1 { 1737 rgmiim1_pins: rgmiim1-pins { 1738 rockchip,pins = 1739 /* mac_txclk */ 1740 <1 RK_PB4 2 &pcfg_pull_none_8ma>, 1741 /* mac_rxclk */ 1742 <1 RK_PB5 2 &pcfg_pull_none_4ma>, 1743 /* mac_mdio */ 1744 <1 RK_PC3 2 &pcfg_pull_none_4ma>, 1745 /* mac_txen */ 1746 <1 RK_PD1 2 &pcfg_pull_none_8ma>, 1747 /* mac_clk */ 1748 <1 RK_PC5 2 &pcfg_pull_none_4ma>, 1749 /* mac_rxdv */ 1750 <1 RK_PC6 2 &pcfg_pull_none_4ma>, 1751 /* mac_mdc */ 1752 <1 RK_PC7 2 &pcfg_pull_none_4ma>, 1753 /* mac_rxd1 */ 1754 <1 RK_PB2 2 &pcfg_pull_none_4ma>, 1755 /* mac_rxd0 */ 1756 <1 RK_PB3 2 &pcfg_pull_none_4ma>, 1757 /* mac_txd1 */ 1758 <1 RK_PB0 2 &pcfg_pull_none_8ma>, 1759 /* mac_txd0 */ 1760 <1 RK_PB1 2 &pcfg_pull_none_8ma>, 1761 /* mac_rxd3 */ 1762 <1 RK_PB6 2 &pcfg_pull_none_4ma>, 1763 /* mac_rxd2 */ 1764 <1 RK_PB7 2 &pcfg_pull_none_4ma>, 1765 /* mac_txd3 */ 1766 <1 RK_PC0 2 &pcfg_pull_none_8ma>, 1767 /* mac_txd2 */ 1768 <1 RK_PC1 2 &pcfg_pull_none_8ma>, 1769 1770 /* mac_txclk */ 1771 <0 RK_PB0 1 &pcfg_pull_none_8ma>, 1772 /* mac_txen */ 1773 <0 RK_PB4 1 &pcfg_pull_none_8ma>, 1774 /* mac_clk */ 1775 <0 RK_PD0 1 &pcfg_pull_none_4ma>, 1776 /* mac_txd1 */ 1777 <0 RK_PC0 1 &pcfg_pull_none_8ma>, 1778 /* mac_txd0 */ 1779 <0 RK_PC1 1 &pcfg_pull_none_8ma>, 1780 /* mac_txd3 */ 1781 <0 RK_PC7 1 &pcfg_pull_none_8ma>, 1782 /* mac_txd2 */ 1783 <0 RK_PC6 1 &pcfg_pull_none_8ma>; 1784 }; 1785 1786 rmiim1_pins: rmiim1-pins { 1787 rockchip,pins = 1788 /* mac_mdio */ 1789 <1 RK_PC3 2 &pcfg_pull_none_2ma>, 1790 /* mac_txen */ 1791 <1 RK_PD1 2 &pcfg_pull_none_12ma>, 1792 /* mac_clk */ 1793 <1 RK_PC5 2 &pcfg_pull_none_2ma>, 1794 /* mac_rxer */ 1795 <1 RK_PD0 2 &pcfg_pull_none_2ma>, 1796 /* mac_rxdv */ 1797 <1 RK_PC6 2 &pcfg_pull_none_2ma>, 1798 /* mac_mdc */ 1799 <1 RK_PC7 2 &pcfg_pull_none_2ma>, 1800 /* mac_rxd1 */ 1801 <1 RK_PB2 2 &pcfg_pull_none_2ma>, 1802 /* mac_rxd0 */ 1803 <1 RK_PB3 2 &pcfg_pull_none_2ma>, 1804 /* mac_txd1 */ 1805 <1 RK_PB0 2 &pcfg_pull_none_12ma>, 1806 /* mac_txd0 */ 1807 <1 RK_PB1 2 &pcfg_pull_none_12ma>, 1808 1809 /* mac_mdio */ 1810 <0 RK_PB3 1 &pcfg_pull_none>, 1811 /* mac_txen */ 1812 <0 RK_PB4 1 &pcfg_pull_none>, 1813 /* mac_clk */ 1814 <0 RK_PD0 1 &pcfg_pull_none>, 1815 /* mac_mdc */ 1816 <0 RK_PC3 1 &pcfg_pull_none>, 1817 /* mac_txd1 */ 1818 <0 RK_PC0 1 &pcfg_pull_none>, 1819 /* mac_txd0 */ 1820 <0 RK_PC1 1 &pcfg_pull_none>; 1821 }; 1822 }; 1823 1824 gmac2phy { 1825 fephyled_speed10: fephyled-speed10 { 1826 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; 1827 }; 1828 1829 fephyled_duplex: fephyled-duplex { 1830 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; 1831 }; 1832 1833 fephyled_rxm1: fephyled-rxm1 { 1834 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>; 1835 }; 1836 1837 fephyled_txm1: fephyled-txm1 { 1838 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>; 1839 }; 1840 1841 fephyled_linkm1: fephyled-linkm1 { 1842 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>; 1843 }; 1844 }; 1845 1846 tsadc_pin { 1847 tsadc_int: tsadc-int { 1848 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; 1849 }; 1850 tsadc_pin: tsadc-pin { 1851 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 1852 }; 1853 }; 1854 1855 hdmi_pin { 1856 hdmi_cec: hdmi-cec { 1857 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 1858 }; 1859 1860 hdmi_hpd: hdmi-hpd { 1861 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>; 1862 }; 1863 }; 1864 1865 cif-0 { 1866 dvp_d2d9_m0:dvp-d2d9-m0 { 1867 rockchip,pins = 1868 /* cif_d0 */ 1869 <3 RK_PA4 2 &pcfg_pull_none>, 1870 /* cif_d1 */ 1871 <3 RK_PA5 2 &pcfg_pull_none>, 1872 /* cif_d2 */ 1873 <3 RK_PA6 2 &pcfg_pull_none>, 1874 /* cif_d3 */ 1875 <3 RK_PA7 2 &pcfg_pull_none>, 1876 /* cif_d4 */ 1877 <3 RK_PB0 2 &pcfg_pull_none>, 1878 /* cif_d5m0 */ 1879 <3 RK_PB1 2 &pcfg_pull_none>, 1880 /* cif_d6m0 */ 1881 <3 RK_PB2 2 &pcfg_pull_none>, 1882 /* cif_d7m0 */ 1883 <3 RK_PB3 2 &pcfg_pull_none>, 1884 /* cif_href */ 1885 <3 RK_PA1 2 &pcfg_pull_none>, 1886 /* cif_vsync */ 1887 <3 RK_PA0 2 &pcfg_pull_none>, 1888 /* cif_clkoutm0 */ 1889 <3 RK_PA3 2 &pcfg_pull_none>, 1890 /* cif_clkin */ 1891 <3 RK_PA2 2 &pcfg_pull_none>; 1892 }; 1893 }; 1894 1895 cif-1 { 1896 dvp_d2d9_m1:dvp-d2d9-m1 { 1897 rockchip,pins = 1898 /* cif_d0 */ 1899 <3 RK_PA4 2 &pcfg_pull_none>, 1900 /* cif_d1 */ 1901 <3 RK_PA5 2 &pcfg_pull_none>, 1902 /* cif_d2 */ 1903 <3 RK_PA6 2 &pcfg_pull_none>, 1904 /* cif_d3 */ 1905 <3 RK_PA7 2 &pcfg_pull_none>, 1906 /* cif_d4 */ 1907 <3 RK_PB0 2 &pcfg_pull_none>, 1908 /* cif_d5m1 */ 1909 <2 RK_PC0 4 &pcfg_pull_none>, 1910 /* cif_d6m1 */ 1911 <2 RK_PC1 4 &pcfg_pull_none>, 1912 /* cif_d7m1 */ 1913 <2 RK_PC2 4 &pcfg_pull_none>, 1914 /* cif_href */ 1915 <3 RK_PA1 2 &pcfg_pull_none>, 1916 /* cif_vsync */ 1917 <3 RK_PA0 2 &pcfg_pull_none>, 1918 /* cif_clkoutm1 */ 1919 <2 RK_PB7 4 &pcfg_pull_none>, 1920 /* cif_clkin */ 1921 <3 RK_PA2 2 &pcfg_pull_none>; 1922 }; 1923 }; 1924 }; 1925};