cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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rk3399-op1-opp.dtsi (3008B)

      1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      2/*
      3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
      4 */
      5
      6/ {
      7	cluster0_opp: opp-table-0 {
      8		compatible = "operating-points-v2";
      9		opp-shared;
     10
     11		opp00 {
     12			opp-hz = /bits/ 64 <408000000>;
     13			opp-microvolt = <800000>;
     14			clock-latency-ns = <40000>;
     15		};
     16		opp01 {
     17			opp-hz = /bits/ 64 <600000000>;
     18			opp-microvolt = <825000>;
     19		};
     20		opp02 {
     21			opp-hz = /bits/ 64 <816000000>;
     22			opp-microvolt = <850000>;
     23		};
     24		opp03 {
     25			opp-hz = /bits/ 64 <1008000000>;
     26			opp-microvolt = <900000>;
     27		};
     28		opp04 {
     29			opp-hz = /bits/ 64 <1200000000>;
     30			opp-microvolt = <975000>;
     31		};
     32		opp05 {
     33			opp-hz = /bits/ 64 <1416000000>;
     34			opp-microvolt = <1100000>;
     35		};
     36		opp06 {
     37			opp-hz = /bits/ 64 <1512000000>;
     38			opp-microvolt = <1150000>;
     39		};
     40	};
     41
     42	cluster1_opp: opp-table-1 {
     43		compatible = "operating-points-v2";
     44		opp-shared;
     45
     46		opp00 {
     47			opp-hz = /bits/ 64 <408000000>;
     48			opp-microvolt = <800000>;
     49			clock-latency-ns = <40000>;
     50		};
     51		opp01 {
     52			opp-hz = /bits/ 64 <600000000>;
     53			opp-microvolt = <800000>;
     54		};
     55		opp02 {
     56			opp-hz = /bits/ 64 <816000000>;
     57			opp-microvolt = <825000>;
     58		};
     59		opp03 {
     60			opp-hz = /bits/ 64 <1008000000>;
     61			opp-microvolt = <850000>;
     62		};
     63		opp04 {
     64			opp-hz = /bits/ 64 <1200000000>;
     65			opp-microvolt = <900000>;
     66		};
     67		opp05 {
     68			opp-hz = /bits/ 64 <1416000000>;
     69			opp-microvolt = <975000>;
     70		};
     71		opp06 {
     72			opp-hz = /bits/ 64 <1608000000>;
     73			opp-microvolt = <1050000>;
     74		};
     75		opp07 {
     76			opp-hz = /bits/ 64 <1800000000>;
     77			opp-microvolt = <1150000>;
     78		};
     79		opp08 {
     80			opp-hz = /bits/ 64 <2016000000>;
     81			opp-microvolt = <1250000>;
     82		};
     83	};
     84
     85	gpu_opp_table: opp-table-2 {
     86		compatible = "operating-points-v2";
     87
     88		opp00 {
     89			opp-hz = /bits/ 64 <200000000>;
     90			opp-microvolt = <800000>;
     91		};
     92		opp01 {
     93			opp-hz = /bits/ 64 <297000000>;
     94			opp-microvolt = <800000>;
     95		};
     96		opp02 {
     97			opp-hz = /bits/ 64 <400000000>;
     98			opp-microvolt = <825000>;
     99		};
    100		opp03 {
    101			opp-hz = /bits/ 64 <500000000>;
    102			opp-microvolt = <850000>;
    103		};
    104		opp04 {
    105			opp-hz = /bits/ 64 <600000000>;
    106			opp-microvolt = <925000>;
    107		};
    108		opp05 {
    109			opp-hz = /bits/ 64 <800000000>;
    110			opp-microvolt = <1075000>;
    111		};
    112	};
    113
    114	dmc_opp_table: dmc_opp_table {
    115		compatible = "operating-points-v2";
    116
    117		opp00 {
    118			opp-hz = /bits/ 64 <400000000>;
    119			opp-microvolt = <900000>;
    120		};
    121		opp01 {
    122			opp-hz = /bits/ 64 <666000000>;
    123			opp-microvolt = <900000>;
    124		};
    125		opp02 {
    126			opp-hz = /bits/ 64 <800000000>;
    127			opp-microvolt = <900000>;
    128		};
    129		opp03 {
    130			opp-hz = /bits/ 64 <928000000>;
    131			opp-microvolt = <925000>;
    132		};
    133	};
    134};
    135
    136&cpu_l0 {
    137	operating-points-v2 = <&cluster0_opp>;
    138};
    139
    140&cpu_l1 {
    141	operating-points-v2 = <&cluster0_opp>;
    142};
    143
    144&cpu_l2 {
    145	operating-points-v2 = <&cluster0_opp>;
    146};
    147
    148&cpu_l3 {
    149	operating-points-v2 = <&cluster0_opp>;
    150};
    151
    152&cpu_b0 {
    153	operating-points-v2 = <&cluster1_opp>;
    154};
    155
    156&cpu_b1 {
    157	operating-points-v2 = <&cluster1_opp>;
    158};
    159
    160&dmc {
    161	operating-points-v2 = <&dmc_opp_table>;
    162};
    163
    164&gpu {
    165	operating-points-v2 = <&gpu_opp_table>;
    166};