rk356x.dtsi (41277B)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3568-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3568-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 gpio0 = &gpio0; 22 gpio1 = &gpio1; 23 gpio2 = &gpio2; 24 gpio3 = &gpio3; 25 gpio4 = &gpio4; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 i2c4 = &i2c4; 31 i2c5 = &i2c5; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 serial5 = &uart5; 38 serial6 = &uart6; 39 serial7 = &uart7; 40 serial8 = &uart8; 41 serial9 = &uart9; 42 spi0 = &spi0; 43 spi1 = &spi1; 44 spi2 = &spi2; 45 spi3 = &spi3; 46 }; 47 48 cpus { 49 #address-cells = <2>; 50 #size-cells = <0>; 51 52 cpu0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a55"; 55 reg = <0x0 0x0>; 56 clocks = <&scmi_clk 0>; 57 #cooling-cells = <2>; 58 enable-method = "psci"; 59 operating-points-v2 = <&cpu0_opp_table>; 60 }; 61 62 cpu1: cpu@100 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a55"; 65 reg = <0x0 0x100>; 66 #cooling-cells = <2>; 67 enable-method = "psci"; 68 operating-points-v2 = <&cpu0_opp_table>; 69 }; 70 71 cpu2: cpu@200 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a55"; 74 reg = <0x0 0x200>; 75 #cooling-cells = <2>; 76 enable-method = "psci"; 77 operating-points-v2 = <&cpu0_opp_table>; 78 }; 79 80 cpu3: cpu@300 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a55"; 83 reg = <0x0 0x300>; 84 #cooling-cells = <2>; 85 enable-method = "psci"; 86 operating-points-v2 = <&cpu0_opp_table>; 87 }; 88 }; 89 90 cpu0_opp_table: opp-table-0 { 91 compatible = "operating-points-v2"; 92 opp-shared; 93 94 opp-408000000 { 95 opp-hz = /bits/ 64 <408000000>; 96 opp-microvolt = <900000 900000 1150000>; 97 clock-latency-ns = <40000>; 98 }; 99 100 opp-600000000 { 101 opp-hz = /bits/ 64 <600000000>; 102 opp-microvolt = <900000 900000 1150000>; 103 }; 104 105 opp-816000000 { 106 opp-hz = /bits/ 64 <816000000>; 107 opp-microvolt = <900000 900000 1150000>; 108 opp-suspend; 109 }; 110 111 opp-1104000000 { 112 opp-hz = /bits/ 64 <1104000000>; 113 opp-microvolt = <900000 900000 1150000>; 114 }; 115 116 opp-1416000000 { 117 opp-hz = /bits/ 64 <1416000000>; 118 opp-microvolt = <900000 900000 1150000>; 119 }; 120 121 opp-1608000000 { 122 opp-hz = /bits/ 64 <1608000000>; 123 opp-microvolt = <975000 975000 1150000>; 124 }; 125 126 opp-1800000000 { 127 opp-hz = /bits/ 64 <1800000000>; 128 opp-microvolt = <1050000 1050000 1150000>; 129 }; 130 }; 131 132 firmware { 133 scmi: scmi { 134 compatible = "arm,scmi-smc"; 135 arm,smc-id = <0x82000010>; 136 shmem = <&scmi_shmem>; 137 #address-cells = <1>; 138 #size-cells = <0>; 139 140 scmi_clk: protocol@14 { 141 reg = <0x14>; 142 #clock-cells = <1>; 143 }; 144 }; 145 }; 146 147 gpu_opp_table: opp-table-1 { 148 compatible = "operating-points-v2"; 149 150 opp-200000000 { 151 opp-hz = /bits/ 64 <200000000>; 152 opp-microvolt = <825000>; 153 }; 154 155 opp-300000000 { 156 opp-hz = /bits/ 64 <300000000>; 157 opp-microvolt = <825000>; 158 }; 159 160 opp-400000000 { 161 opp-hz = /bits/ 64 <400000000>; 162 opp-microvolt = <825000>; 163 }; 164 165 opp-600000000 { 166 opp-hz = /bits/ 64 <600000000>; 167 opp-microvolt = <825000>; 168 }; 169 170 opp-700000000 { 171 opp-hz = /bits/ 64 <700000000>; 172 opp-microvolt = <900000>; 173 }; 174 175 opp-800000000 { 176 opp-hz = /bits/ 64 <800000000>; 177 opp-microvolt = <1000000>; 178 }; 179 }; 180 181 pmu { 182 compatible = "arm,cortex-a55-pmu"; 183 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 187 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 188 }; 189 190 psci { 191 compatible = "arm,psci-1.0"; 192 method = "smc"; 193 }; 194 195 timer { 196 compatible = "arm,armv8-timer"; 197 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 201 arm,no-tick-in-suspend; 202 }; 203 204 xin24m: xin24m { 205 compatible = "fixed-clock"; 206 clock-frequency = <24000000>; 207 clock-output-names = "xin24m"; 208 #clock-cells = <0>; 209 }; 210 211 xin32k: xin32k { 212 compatible = "fixed-clock"; 213 clock-frequency = <32768>; 214 clock-output-names = "xin32k"; 215 pinctrl-0 = <&clk32k_out0>; 216 pinctrl-names = "default"; 217 #clock-cells = <0>; 218 }; 219 220 sram@10f000 { 221 compatible = "mmio-sram"; 222 reg = <0x0 0x0010f000 0x0 0x100>; 223 #address-cells = <1>; 224 #size-cells = <1>; 225 ranges = <0 0x0 0x0010f000 0x100>; 226 227 scmi_shmem: sram@0 { 228 compatible = "arm,scmi-shmem"; 229 reg = <0x0 0x100>; 230 }; 231 }; 232 233 sata1: sata@fc400000 { 234 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; 235 reg = <0 0xfc400000 0 0x1000>; 236 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, 237 <&cru CLK_SATA1_RXOOB>; 238 clock-names = "sata", "pmalive", "rxoob"; 239 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 240 phys = <&combphy1 PHY_TYPE_SATA>; 241 phy-names = "sata-phy"; 242 ports-implemented = <0x1>; 243 power-domains = <&power RK3568_PD_PIPE>; 244 status = "disabled"; 245 }; 246 247 sata2: sata@fc800000 { 248 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; 249 reg = <0 0xfc800000 0 0x1000>; 250 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, 251 <&cru CLK_SATA2_RXOOB>; 252 clock-names = "sata", "pmalive", "rxoob"; 253 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 254 phys = <&combphy2 PHY_TYPE_SATA>; 255 phy-names = "sata-phy"; 256 ports-implemented = <0x1>; 257 power-domains = <&power RK3568_PD_PIPE>; 258 status = "disabled"; 259 }; 260 261 usb_host0_xhci: usb@fcc00000 { 262 compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; 263 reg = <0x0 0xfcc00000 0x0 0x400000>; 264 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 265 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, 266 <&cru ACLK_USB3OTG0>; 267 clock-names = "ref_clk", "suspend_clk", 268 "bus_clk"; 269 dr_mode = "otg"; 270 phy_type = "utmi_wide"; 271 power-domains = <&power RK3568_PD_PIPE>; 272 resets = <&cru SRST_USB3OTG0>; 273 snps,dis_u2_susphy_quirk; 274 status = "disabled"; 275 }; 276 277 usb_host1_xhci: usb@fd000000 { 278 compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; 279 reg = <0x0 0xfd000000 0x0 0x400000>; 280 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, 282 <&cru ACLK_USB3OTG1>; 283 clock-names = "ref_clk", "suspend_clk", 284 "bus_clk"; 285 dr_mode = "host"; 286 phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>; 287 phy-names = "usb2-phy", "usb3-phy"; 288 phy_type = "utmi_wide"; 289 power-domains = <&power RK3568_PD_PIPE>; 290 resets = <&cru SRST_USB3OTG1>; 291 snps,dis_u2_susphy_quirk; 292 status = "disabled"; 293 }; 294 295 gic: interrupt-controller@fd400000 { 296 compatible = "arm,gic-v3"; 297 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ 298 <0x0 0xfd460000 0 0x80000>; /* GICR */ 299 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 300 interrupt-controller; 301 #interrupt-cells = <3>; 302 mbi-alias = <0x0 0xfd410000>; 303 mbi-ranges = <296 24>; 304 msi-controller; 305 }; 306 307 usb_host0_ehci: usb@fd800000 { 308 compatible = "generic-ehci"; 309 reg = <0x0 0xfd800000 0x0 0x40000>; 310 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, 312 <&cru PCLK_USB>; 313 phys = <&usb2phy1_otg>; 314 phy-names = "usb"; 315 status = "disabled"; 316 }; 317 318 usb_host0_ohci: usb@fd840000 { 319 compatible = "generic-ohci"; 320 reg = <0x0 0xfd840000 0x0 0x40000>; 321 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, 323 <&cru PCLK_USB>; 324 phys = <&usb2phy1_otg>; 325 phy-names = "usb"; 326 status = "disabled"; 327 }; 328 329 usb_host1_ehci: usb@fd880000 { 330 compatible = "generic-ehci"; 331 reg = <0x0 0xfd880000 0x0 0x40000>; 332 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, 334 <&cru PCLK_USB>; 335 phys = <&usb2phy1_host>; 336 phy-names = "usb"; 337 status = "disabled"; 338 }; 339 340 usb_host1_ohci: usb@fd8c0000 { 341 compatible = "generic-ohci"; 342 reg = <0x0 0xfd8c0000 0x0 0x40000>; 343 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, 345 <&cru PCLK_USB>; 346 phys = <&usb2phy1_host>; 347 phy-names = "usb"; 348 status = "disabled"; 349 }; 350 351 pmugrf: syscon@fdc20000 { 352 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; 353 reg = <0x0 0xfdc20000 0x0 0x10000>; 354 355 pmu_io_domains: io-domains { 356 compatible = "rockchip,rk3568-pmu-io-voltage-domain"; 357 status = "disabled"; 358 }; 359 }; 360 361 pipegrf: syscon@fdc50000 { 362 reg = <0x0 0xfdc50000 0x0 0x1000>; 363 }; 364 365 grf: syscon@fdc60000 { 366 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; 367 reg = <0x0 0xfdc60000 0x0 0x10000>; 368 }; 369 370 pipe_phy_grf1: syscon@fdc80000 { 371 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; 372 reg = <0x0 0xfdc80000 0x0 0x1000>; 373 }; 374 375 pipe_phy_grf2: syscon@fdc90000 { 376 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; 377 reg = <0x0 0xfdc90000 0x0 0x1000>; 378 }; 379 380 usb2phy0_grf: syscon@fdca0000 { 381 compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; 382 reg = <0x0 0xfdca0000 0x0 0x8000>; 383 }; 384 385 usb2phy1_grf: syscon@fdca8000 { 386 compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; 387 reg = <0x0 0xfdca8000 0x0 0x8000>; 388 }; 389 390 pmucru: clock-controller@fdd00000 { 391 compatible = "rockchip,rk3568-pmucru"; 392 reg = <0x0 0xfdd00000 0x0 0x1000>; 393 #clock-cells = <1>; 394 #reset-cells = <1>; 395 }; 396 397 cru: clock-controller@fdd20000 { 398 compatible = "rockchip,rk3568-cru"; 399 reg = <0x0 0xfdd20000 0x0 0x1000>; 400 clocks = <&xin24m>; 401 clock-names = "xin24m"; 402 #clock-cells = <1>; 403 #reset-cells = <1>; 404 assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; 405 assigned-clock-rates = <1200000000>, <200000000>; 406 rockchip,grf = <&grf>; 407 }; 408 409 i2c0: i2c@fdd40000 { 410 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 411 reg = <0x0 0xfdd40000 0x0 0x1000>; 412 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 413 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 414 clock-names = "i2c", "pclk"; 415 pinctrl-0 = <&i2c0_xfer>; 416 pinctrl-names = "default"; 417 #address-cells = <1>; 418 #size-cells = <0>; 419 status = "disabled"; 420 }; 421 422 uart0: serial@fdd50000 { 423 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 424 reg = <0x0 0xfdd50000 0x0 0x100>; 425 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 426 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; 427 clock-names = "baudclk", "apb_pclk"; 428 dmas = <&dmac0 0>, <&dmac0 1>; 429 pinctrl-0 = <&uart0_xfer>; 430 pinctrl-names = "default"; 431 reg-io-width = <4>; 432 reg-shift = <2>; 433 status = "disabled"; 434 }; 435 436 pwm0: pwm@fdd70000 { 437 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 438 reg = <0x0 0xfdd70000 0x0 0x10>; 439 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 440 clock-names = "pwm", "pclk"; 441 pinctrl-0 = <&pwm0m0_pins>; 442 pinctrl-names = "default"; 443 #pwm-cells = <3>; 444 status = "disabled"; 445 }; 446 447 pwm1: pwm@fdd70010 { 448 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 449 reg = <0x0 0xfdd70010 0x0 0x10>; 450 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 451 clock-names = "pwm", "pclk"; 452 pinctrl-0 = <&pwm1m0_pins>; 453 pinctrl-names = "default"; 454 #pwm-cells = <3>; 455 status = "disabled"; 456 }; 457 458 pwm2: pwm@fdd70020 { 459 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 460 reg = <0x0 0xfdd70020 0x0 0x10>; 461 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 462 clock-names = "pwm", "pclk"; 463 pinctrl-0 = <&pwm2m0_pins>; 464 pinctrl-names = "default"; 465 #pwm-cells = <3>; 466 status = "disabled"; 467 }; 468 469 pwm3: pwm@fdd70030 { 470 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 471 reg = <0x0 0xfdd70030 0x0 0x10>; 472 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 473 clock-names = "pwm", "pclk"; 474 pinctrl-0 = <&pwm3_pins>; 475 pinctrl-names = "default"; 476 #pwm-cells = <3>; 477 status = "disabled"; 478 }; 479 480 pmu: power-management@fdd90000 { 481 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; 482 reg = <0x0 0xfdd90000 0x0 0x1000>; 483 484 power: power-controller { 485 compatible = "rockchip,rk3568-power-controller"; 486 #power-domain-cells = <1>; 487 #address-cells = <1>; 488 #size-cells = <0>; 489 490 /* These power domains are grouped by VD_GPU */ 491 power-domain@RK3568_PD_GPU { 492 reg = <RK3568_PD_GPU>; 493 clocks = <&cru ACLK_GPU_PRE>, 494 <&cru PCLK_GPU_PRE>; 495 pm_qos = <&qos_gpu>; 496 #power-domain-cells = <0>; 497 }; 498 499 /* These power domains are grouped by VD_LOGIC */ 500 power-domain@RK3568_PD_VI { 501 reg = <RK3568_PD_VI>; 502 clocks = <&cru HCLK_VI>, 503 <&cru PCLK_VI>; 504 pm_qos = <&qos_isp>, 505 <&qos_vicap0>, 506 <&qos_vicap1>; 507 #power-domain-cells = <0>; 508 }; 509 510 power-domain@RK3568_PD_VO { 511 reg = <RK3568_PD_VO>; 512 clocks = <&cru HCLK_VO>, 513 <&cru PCLK_VO>, 514 <&cru ACLK_VOP_PRE>; 515 pm_qos = <&qos_hdcp>, 516 <&qos_vop_m0>, 517 <&qos_vop_m1>; 518 #power-domain-cells = <0>; 519 }; 520 521 power-domain@RK3568_PD_RGA { 522 reg = <RK3568_PD_RGA>; 523 clocks = <&cru HCLK_RGA_PRE>, 524 <&cru PCLK_RGA_PRE>; 525 pm_qos = <&qos_ebc>, 526 <&qos_iep>, 527 <&qos_jpeg_dec>, 528 <&qos_jpeg_enc>, 529 <&qos_rga_rd>, 530 <&qos_rga_wr>; 531 #power-domain-cells = <0>; 532 }; 533 534 power-domain@RK3568_PD_VPU { 535 reg = <RK3568_PD_VPU>; 536 clocks = <&cru HCLK_VPU_PRE>; 537 pm_qos = <&qos_vpu>; 538 #power-domain-cells = <0>; 539 }; 540 541 power-domain@RK3568_PD_RKVDEC { 542 clocks = <&cru HCLK_RKVDEC_PRE>; 543 reg = <RK3568_PD_RKVDEC>; 544 pm_qos = <&qos_rkvdec>; 545 #power-domain-cells = <0>; 546 }; 547 548 power-domain@RK3568_PD_RKVENC { 549 reg = <RK3568_PD_RKVENC>; 550 clocks = <&cru HCLK_RKVENC_PRE>; 551 pm_qos = <&qos_rkvenc_rd_m0>, 552 <&qos_rkvenc_rd_m1>, 553 <&qos_rkvenc_wr_m0>; 554 #power-domain-cells = <0>; 555 }; 556 }; 557 }; 558 559 gpu: gpu@fde60000 { 560 compatible = "rockchip,rk3568-mali", "arm,mali-bifrost"; 561 reg = <0x0 0xfde60000 0x0 0x4000>; 562 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 565 interrupt-names = "job", "mmu", "gpu"; 566 clocks = <&scmi_clk 1>, <&cru CLK_GPU>; 567 clock-names = "gpu", "bus"; 568 #cooling-cells = <2>; 569 operating-points-v2 = <&gpu_opp_table>; 570 power-domains = <&power RK3568_PD_GPU>; 571 status = "disabled"; 572 }; 573 574 sdmmc2: mmc@fe000000 { 575 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 576 reg = <0x0 0xfe000000 0x0 0x4000>; 577 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, 579 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; 580 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 581 fifo-depth = <0x100>; 582 max-frequency = <150000000>; 583 resets = <&cru SRST_SDMMC2>; 584 reset-names = "reset"; 585 status = "disabled"; 586 }; 587 588 gmac1: ethernet@fe010000 { 589 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; 590 reg = <0x0 0xfe010000 0x0 0x10000>; 591 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 593 interrupt-names = "macirq", "eth_wake_irq"; 594 clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, 595 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, 596 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, 597 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>; 598 clock-names = "stmmaceth", "mac_clk_rx", 599 "mac_clk_tx", "clk_mac_refout", 600 "aclk_mac", "pclk_mac", 601 "clk_mac_speed", "ptp_ref"; 602 resets = <&cru SRST_A_GMAC1>; 603 reset-names = "stmmaceth"; 604 rockchip,grf = <&grf>; 605 snps,axi-config = <&gmac1_stmmac_axi_setup>; 606 snps,mixed-burst; 607 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 608 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 609 snps,tso; 610 status = "disabled"; 611 612 mdio1: mdio { 613 compatible = "snps,dwmac-mdio"; 614 #address-cells = <0x1>; 615 #size-cells = <0x0>; 616 }; 617 618 gmac1_stmmac_axi_setup: stmmac-axi-config { 619 snps,blen = <0 0 0 0 16 8 4>; 620 snps,rd_osr_lmt = <8>; 621 snps,wr_osr_lmt = <4>; 622 }; 623 624 gmac1_mtl_rx_setup: rx-queues-config { 625 snps,rx-queues-to-use = <1>; 626 queue0 {}; 627 }; 628 629 gmac1_mtl_tx_setup: tx-queues-config { 630 snps,tx-queues-to-use = <1>; 631 queue0 {}; 632 }; 633 }; 634 635 qos_gpu: qos@fe128000 { 636 compatible = "rockchip,rk3568-qos", "syscon"; 637 reg = <0x0 0xfe128000 0x0 0x20>; 638 }; 639 640 qos_rkvenc_rd_m0: qos@fe138080 { 641 compatible = "rockchip,rk3568-qos", "syscon"; 642 reg = <0x0 0xfe138080 0x0 0x20>; 643 }; 644 645 qos_rkvenc_rd_m1: qos@fe138100 { 646 compatible = "rockchip,rk3568-qos", "syscon"; 647 reg = <0x0 0xfe138100 0x0 0x20>; 648 }; 649 650 qos_rkvenc_wr_m0: qos@fe138180 { 651 compatible = "rockchip,rk3568-qos", "syscon"; 652 reg = <0x0 0xfe138180 0x0 0x20>; 653 }; 654 655 qos_isp: qos@fe148000 { 656 compatible = "rockchip,rk3568-qos", "syscon"; 657 reg = <0x0 0xfe148000 0x0 0x20>; 658 }; 659 660 qos_vicap0: qos@fe148080 { 661 compatible = "rockchip,rk3568-qos", "syscon"; 662 reg = <0x0 0xfe148080 0x0 0x20>; 663 }; 664 665 qos_vicap1: qos@fe148100 { 666 compatible = "rockchip,rk3568-qos", "syscon"; 667 reg = <0x0 0xfe148100 0x0 0x20>; 668 }; 669 670 qos_vpu: qos@fe150000 { 671 compatible = "rockchip,rk3568-qos", "syscon"; 672 reg = <0x0 0xfe150000 0x0 0x20>; 673 }; 674 675 qos_ebc: qos@fe158000 { 676 compatible = "rockchip,rk3568-qos", "syscon"; 677 reg = <0x0 0xfe158000 0x0 0x20>; 678 }; 679 680 qos_iep: qos@fe158100 { 681 compatible = "rockchip,rk3568-qos", "syscon"; 682 reg = <0x0 0xfe158100 0x0 0x20>; 683 }; 684 685 qos_jpeg_dec: qos@fe158180 { 686 compatible = "rockchip,rk3568-qos", "syscon"; 687 reg = <0x0 0xfe158180 0x0 0x20>; 688 }; 689 690 qos_jpeg_enc: qos@fe158200 { 691 compatible = "rockchip,rk3568-qos", "syscon"; 692 reg = <0x0 0xfe158200 0x0 0x20>; 693 }; 694 695 qos_rga_rd: qos@fe158280 { 696 compatible = "rockchip,rk3568-qos", "syscon"; 697 reg = <0x0 0xfe158280 0x0 0x20>; 698 }; 699 700 qos_rga_wr: qos@fe158300 { 701 compatible = "rockchip,rk3568-qos", "syscon"; 702 reg = <0x0 0xfe158300 0x0 0x20>; 703 }; 704 705 qos_npu: qos@fe180000 { 706 compatible = "rockchip,rk3568-qos", "syscon"; 707 reg = <0x0 0xfe180000 0x0 0x20>; 708 }; 709 710 qos_pcie2x1: qos@fe190000 { 711 compatible = "rockchip,rk3568-qos", "syscon"; 712 reg = <0x0 0xfe190000 0x0 0x20>; 713 }; 714 715 qos_sata1: qos@fe190280 { 716 compatible = "rockchip,rk3568-qos", "syscon"; 717 reg = <0x0 0xfe190280 0x0 0x20>; 718 }; 719 720 qos_sata2: qos@fe190300 { 721 compatible = "rockchip,rk3568-qos", "syscon"; 722 reg = <0x0 0xfe190300 0x0 0x20>; 723 }; 724 725 qos_usb3_0: qos@fe190380 { 726 compatible = "rockchip,rk3568-qos", "syscon"; 727 reg = <0x0 0xfe190380 0x0 0x20>; 728 }; 729 730 qos_usb3_1: qos@fe190400 { 731 compatible = "rockchip,rk3568-qos", "syscon"; 732 reg = <0x0 0xfe190400 0x0 0x20>; 733 }; 734 735 qos_rkvdec: qos@fe198000 { 736 compatible = "rockchip,rk3568-qos", "syscon"; 737 reg = <0x0 0xfe198000 0x0 0x20>; 738 }; 739 740 qos_hdcp: qos@fe1a8000 { 741 compatible = "rockchip,rk3568-qos", "syscon"; 742 reg = <0x0 0xfe1a8000 0x0 0x20>; 743 }; 744 745 qos_vop_m0: qos@fe1a8080 { 746 compatible = "rockchip,rk3568-qos", "syscon"; 747 reg = <0x0 0xfe1a8080 0x0 0x20>; 748 }; 749 750 qos_vop_m1: qos@fe1a8100 { 751 compatible = "rockchip,rk3568-qos", "syscon"; 752 reg = <0x0 0xfe1a8100 0x0 0x20>; 753 }; 754 755 sdmmc0: mmc@fe2b0000 { 756 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 757 reg = <0x0 0xfe2b0000 0x0 0x4000>; 758 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 759 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, 760 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; 761 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 762 fifo-depth = <0x100>; 763 max-frequency = <150000000>; 764 resets = <&cru SRST_SDMMC0>; 765 reset-names = "reset"; 766 status = "disabled"; 767 }; 768 769 sdmmc1: mmc@fe2c0000 { 770 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 771 reg = <0x0 0xfe2c0000 0x0 0x4000>; 772 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 773 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, 774 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; 775 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 776 fifo-depth = <0x100>; 777 max-frequency = <150000000>; 778 resets = <&cru SRST_SDMMC1>; 779 reset-names = "reset"; 780 status = "disabled"; 781 }; 782 783 sfc: spi@fe300000 { 784 compatible = "rockchip,sfc"; 785 reg = <0x0 0xfe300000 0x0 0x4000>; 786 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 787 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 788 clock-names = "clk_sfc", "hclk_sfc"; 789 pinctrl-0 = <&fspi_pins>; 790 pinctrl-names = "default"; 791 status = "disabled"; 792 }; 793 794 sdhci: mmc@fe310000 { 795 compatible = "rockchip,rk3568-dwcmshc"; 796 reg = <0x0 0xfe310000 0x0 0x10000>; 797 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 798 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; 799 assigned-clock-rates = <200000000>, <24000000>; 800 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 801 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 802 <&cru TCLK_EMMC>; 803 clock-names = "core", "bus", "axi", "block", "timer"; 804 status = "disabled"; 805 }; 806 807 spdif: spdif@fe460000 { 808 compatible = "rockchip,rk3568-spdif"; 809 reg = <0x0 0xfe460000 0x0 0x1000>; 810 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 811 clock-names = "mclk", "hclk"; 812 clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; 813 dmas = <&dmac1 1>; 814 dma-names = "tx"; 815 pinctrl-names = "default"; 816 pinctrl-0 = <&spdifm0_tx>; 817 #sound-dai-cells = <0>; 818 status = "disabled"; 819 }; 820 821 i2s1_8ch: i2s@fe410000 { 822 compatible = "rockchip,rk3568-i2s-tdm"; 823 reg = <0x0 0xfe410000 0x0 0x1000>; 824 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 825 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>; 826 assigned-clock-rates = <1188000000>, <1188000000>; 827 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, 828 <&cru HCLK_I2S1_8CH>; 829 clock-names = "mclk_tx", "mclk_rx", "hclk"; 830 dmas = <&dmac1 3>, <&dmac1 2>; 831 dma-names = "rx", "tx"; 832 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 833 reset-names = "tx-m", "rx-m"; 834 rockchip,grf = <&grf>; 835 pinctrl-names = "default"; 836 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx 837 &i2s1m0_lrcktx &i2s1m0_lrckrx 838 &i2s1m0_sdi0 &i2s1m0_sdi1 839 &i2s1m0_sdi2 &i2s1m0_sdi3 840 &i2s1m0_sdo0 &i2s1m0_sdo1 841 &i2s1m0_sdo2 &i2s1m0_sdo3>; 842 #sound-dai-cells = <0>; 843 status = "disabled"; 844 }; 845 846 i2s3_2ch: i2s@fe430000 { 847 compatible = "rockchip,rk3568-i2s-tdm"; 848 reg = <0x0 0xfe430000 0x0 0x1000>; 849 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 850 clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, 851 <&cru HCLK_I2S3_2CH>; 852 clock-names = "mclk_tx", "mclk_rx", "hclk"; 853 dmas = <&dmac1 6>, <&dmac1 7>; 854 dma-names = "tx", "rx"; 855 resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>; 856 reset-names = "tx-m", "rx-m"; 857 rockchip,grf = <&grf>; 858 #sound-dai-cells = <0>; 859 status = "disabled"; 860 }; 861 862 pdm: pdm@fe440000 { 863 compatible = "rockchip,rk3568-pdm"; 864 reg = <0x0 0xfe440000 0x0 0x1000>; 865 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 866 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; 867 clock-names = "pdm_clk", "pdm_hclk"; 868 dmas = <&dmac1 9>; 869 dma-names = "rx"; 870 pinctrl-0 = <&pdmm0_clk 871 &pdmm0_clk1 872 &pdmm0_sdi0 873 &pdmm0_sdi1 874 &pdmm0_sdi2 875 &pdmm0_sdi3>; 876 pinctrl-names = "default"; 877 resets = <&cru SRST_M_PDM>; 878 reset-names = "pdm-m"; 879 #sound-dai-cells = <0>; 880 status = "disabled"; 881 }; 882 883 dmac0: dma-controller@fe530000 { 884 compatible = "arm,pl330", "arm,primecell"; 885 reg = <0x0 0xfe530000 0x0 0x4000>; 886 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 888 arm,pl330-periph-burst; 889 clocks = <&cru ACLK_BUS>; 890 clock-names = "apb_pclk"; 891 #dma-cells = <1>; 892 }; 893 894 dmac1: dma-controller@fe550000 { 895 compatible = "arm,pl330", "arm,primecell"; 896 reg = <0x0 0xfe550000 0x0 0x4000>; 897 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 899 arm,pl330-periph-burst; 900 clocks = <&cru ACLK_BUS>; 901 clock-names = "apb_pclk"; 902 #dma-cells = <1>; 903 }; 904 905 i2c1: i2c@fe5a0000 { 906 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 907 reg = <0x0 0xfe5a0000 0x0 0x1000>; 908 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 909 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 910 clock-names = "i2c", "pclk"; 911 pinctrl-0 = <&i2c1_xfer>; 912 pinctrl-names = "default"; 913 #address-cells = <1>; 914 #size-cells = <0>; 915 status = "disabled"; 916 }; 917 918 i2c2: i2c@fe5b0000 { 919 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 920 reg = <0x0 0xfe5b0000 0x0 0x1000>; 921 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 922 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 923 clock-names = "i2c", "pclk"; 924 pinctrl-0 = <&i2c2m0_xfer>; 925 pinctrl-names = "default"; 926 #address-cells = <1>; 927 #size-cells = <0>; 928 status = "disabled"; 929 }; 930 931 i2c3: i2c@fe5c0000 { 932 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 933 reg = <0x0 0xfe5c0000 0x0 0x1000>; 934 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 935 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 936 clock-names = "i2c", "pclk"; 937 pinctrl-0 = <&i2c3m0_xfer>; 938 pinctrl-names = "default"; 939 #address-cells = <1>; 940 #size-cells = <0>; 941 status = "disabled"; 942 }; 943 944 i2c4: i2c@fe5d0000 { 945 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 946 reg = <0x0 0xfe5d0000 0x0 0x1000>; 947 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 948 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 949 clock-names = "i2c", "pclk"; 950 pinctrl-0 = <&i2c4m0_xfer>; 951 pinctrl-names = "default"; 952 #address-cells = <1>; 953 #size-cells = <0>; 954 status = "disabled"; 955 }; 956 957 i2c5: i2c@fe5e0000 { 958 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 959 reg = <0x0 0xfe5e0000 0x0 0x1000>; 960 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 961 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 962 clock-names = "i2c", "pclk"; 963 pinctrl-0 = <&i2c5m0_xfer>; 964 pinctrl-names = "default"; 965 #address-cells = <1>; 966 #size-cells = <0>; 967 status = "disabled"; 968 }; 969 970 wdt: watchdog@fe600000 { 971 compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; 972 reg = <0x0 0xfe600000 0x0 0x100>; 973 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 974 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; 975 clock-names = "tclk", "pclk"; 976 }; 977 978 spi0: spi@fe610000 { 979 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 980 reg = <0x0 0xfe610000 0x0 0x1000>; 981 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 983 clock-names = "spiclk", "apb_pclk"; 984 dmas = <&dmac0 20>, <&dmac0 21>; 985 dma-names = "tx", "rx"; 986 pinctrl-names = "default"; 987 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 988 #address-cells = <1>; 989 #size-cells = <0>; 990 status = "disabled"; 991 }; 992 993 spi1: spi@fe620000 { 994 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 995 reg = <0x0 0xfe620000 0x0 0x1000>; 996 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 997 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 998 clock-names = "spiclk", "apb_pclk"; 999 dmas = <&dmac0 22>, <&dmac0 23>; 1000 dma-names = "tx", "rx"; 1001 pinctrl-names = "default"; 1002 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 status = "disabled"; 1006 }; 1007 1008 spi2: spi@fe630000 { 1009 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1010 reg = <0x0 0xfe630000 0x0 0x1000>; 1011 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1012 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 1013 clock-names = "spiclk", "apb_pclk"; 1014 dmas = <&dmac0 24>, <&dmac0 25>; 1015 dma-names = "tx", "rx"; 1016 pinctrl-names = "default"; 1017 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; 1018 #address-cells = <1>; 1019 #size-cells = <0>; 1020 status = "disabled"; 1021 }; 1022 1023 spi3: spi@fe640000 { 1024 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1025 reg = <0x0 0xfe640000 0x0 0x1000>; 1026 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1027 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 1028 clock-names = "spiclk", "apb_pclk"; 1029 dmas = <&dmac0 26>, <&dmac0 27>; 1030 dma-names = "tx", "rx"; 1031 pinctrl-names = "default"; 1032 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>; 1033 #address-cells = <1>; 1034 #size-cells = <0>; 1035 status = "disabled"; 1036 }; 1037 1038 uart1: serial@fe650000 { 1039 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1040 reg = <0x0 0xfe650000 0x0 0x100>; 1041 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1042 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1043 clock-names = "baudclk", "apb_pclk"; 1044 dmas = <&dmac0 2>, <&dmac0 3>; 1045 pinctrl-0 = <&uart1m0_xfer>; 1046 pinctrl-names = "default"; 1047 reg-io-width = <4>; 1048 reg-shift = <2>; 1049 status = "disabled"; 1050 }; 1051 1052 uart2: serial@fe660000 { 1053 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1054 reg = <0x0 0xfe660000 0x0 0x100>; 1055 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1056 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1057 clock-names = "baudclk", "apb_pclk"; 1058 dmas = <&dmac0 4>, <&dmac0 5>; 1059 pinctrl-0 = <&uart2m0_xfer>; 1060 pinctrl-names = "default"; 1061 reg-io-width = <4>; 1062 reg-shift = <2>; 1063 status = "disabled"; 1064 }; 1065 1066 uart3: serial@fe670000 { 1067 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1068 reg = <0x0 0xfe670000 0x0 0x100>; 1069 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1070 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1071 clock-names = "baudclk", "apb_pclk"; 1072 dmas = <&dmac0 6>, <&dmac0 7>; 1073 pinctrl-0 = <&uart3m0_xfer>; 1074 pinctrl-names = "default"; 1075 reg-io-width = <4>; 1076 reg-shift = <2>; 1077 status = "disabled"; 1078 }; 1079 1080 uart4: serial@fe680000 { 1081 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1082 reg = <0x0 0xfe680000 0x0 0x100>; 1083 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1084 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1085 clock-names = "baudclk", "apb_pclk"; 1086 dmas = <&dmac0 8>, <&dmac0 9>; 1087 pinctrl-0 = <&uart4m0_xfer>; 1088 pinctrl-names = "default"; 1089 reg-io-width = <4>; 1090 reg-shift = <2>; 1091 status = "disabled"; 1092 }; 1093 1094 uart5: serial@fe690000 { 1095 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1096 reg = <0x0 0xfe690000 0x0 0x100>; 1097 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1098 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1099 clock-names = "baudclk", "apb_pclk"; 1100 dmas = <&dmac0 10>, <&dmac0 11>; 1101 pinctrl-0 = <&uart5m0_xfer>; 1102 pinctrl-names = "default"; 1103 reg-io-width = <4>; 1104 reg-shift = <2>; 1105 status = "disabled"; 1106 }; 1107 1108 uart6: serial@fe6a0000 { 1109 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1110 reg = <0x0 0xfe6a0000 0x0 0x100>; 1111 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1112 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 1113 clock-names = "baudclk", "apb_pclk"; 1114 dmas = <&dmac0 12>, <&dmac0 13>; 1115 pinctrl-0 = <&uart6m0_xfer>; 1116 pinctrl-names = "default"; 1117 reg-io-width = <4>; 1118 reg-shift = <2>; 1119 status = "disabled"; 1120 }; 1121 1122 uart7: serial@fe6b0000 { 1123 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1124 reg = <0x0 0xfe6b0000 0x0 0x100>; 1125 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1126 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 1127 clock-names = "baudclk", "apb_pclk"; 1128 dmas = <&dmac0 14>, <&dmac0 15>; 1129 pinctrl-0 = <&uart7m0_xfer>; 1130 pinctrl-names = "default"; 1131 reg-io-width = <4>; 1132 reg-shift = <2>; 1133 status = "disabled"; 1134 }; 1135 1136 uart8: serial@fe6c0000 { 1137 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1138 reg = <0x0 0xfe6c0000 0x0 0x100>; 1139 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 1140 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 1141 clock-names = "baudclk", "apb_pclk"; 1142 dmas = <&dmac0 16>, <&dmac0 17>; 1143 pinctrl-0 = <&uart8m0_xfer>; 1144 pinctrl-names = "default"; 1145 reg-io-width = <4>; 1146 reg-shift = <2>; 1147 status = "disabled"; 1148 }; 1149 1150 uart9: serial@fe6d0000 { 1151 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1152 reg = <0x0 0xfe6d0000 0x0 0x100>; 1153 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1154 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 1155 clock-names = "baudclk", "apb_pclk"; 1156 dmas = <&dmac0 18>, <&dmac0 19>; 1157 pinctrl-0 = <&uart9m0_xfer>; 1158 pinctrl-names = "default"; 1159 reg-io-width = <4>; 1160 reg-shift = <2>; 1161 status = "disabled"; 1162 }; 1163 1164 thermal_zones: thermal-zones { 1165 cpu_thermal: cpu-thermal { 1166 polling-delay-passive = <100>; 1167 polling-delay = <1000>; 1168 1169 thermal-sensors = <&tsadc 0>; 1170 1171 trips { 1172 cpu_alert0: cpu_alert0 { 1173 temperature = <70000>; 1174 hysteresis = <2000>; 1175 type = "passive"; 1176 }; 1177 cpu_alert1: cpu_alert1 { 1178 temperature = <75000>; 1179 hysteresis = <2000>; 1180 type = "passive"; 1181 }; 1182 cpu_crit: cpu_crit { 1183 temperature = <95000>; 1184 hysteresis = <2000>; 1185 type = "critical"; 1186 }; 1187 }; 1188 1189 cooling-maps { 1190 map0 { 1191 trip = <&cpu_alert0>; 1192 cooling-device = 1193 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1194 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1195 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1196 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1197 }; 1198 }; 1199 }; 1200 1201 gpu_thermal: gpu-thermal { 1202 polling-delay-passive = <20>; /* milliseconds */ 1203 polling-delay = <1000>; /* milliseconds */ 1204 1205 thermal-sensors = <&tsadc 1>; 1206 1207 trips { 1208 gpu_threshold: gpu-threshold { 1209 temperature = <70000>; 1210 hysteresis = <2000>; 1211 type = "passive"; 1212 }; 1213 gpu_target: gpu-target { 1214 temperature = <75000>; 1215 hysteresis = <2000>; 1216 type = "passive"; 1217 }; 1218 gpu_crit: gpu-crit { 1219 temperature = <95000>; 1220 hysteresis = <2000>; 1221 type = "critical"; 1222 }; 1223 }; 1224 1225 cooling-maps { 1226 map0 { 1227 trip = <&gpu_target>; 1228 cooling-device = 1229 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1230 }; 1231 }; 1232 }; 1233 }; 1234 1235 tsadc: tsadc@fe710000 { 1236 compatible = "rockchip,rk3568-tsadc"; 1237 reg = <0x0 0xfe710000 0x0 0x100>; 1238 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1239 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; 1240 assigned-clock-rates = <17000000>, <700000>; 1241 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 1242 clock-names = "tsadc", "apb_pclk"; 1243 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>, 1244 <&cru SRST_TSADCPHY>; 1245 rockchip,grf = <&grf>; 1246 rockchip,hw-tshut-temp = <95000>; 1247 pinctrl-names = "init", "default", "sleep"; 1248 pinctrl-0 = <&tsadc_pin>; 1249 pinctrl-1 = <&tsadc_shutorg>; 1250 pinctrl-2 = <&tsadc_pin>; 1251 #thermal-sensor-cells = <1>; 1252 status = "disabled"; 1253 }; 1254 1255 saradc: saradc@fe720000 { 1256 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; 1257 reg = <0x0 0xfe720000 0x0 0x100>; 1258 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1259 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 1260 clock-names = "saradc", "apb_pclk"; 1261 resets = <&cru SRST_P_SARADC>; 1262 reset-names = "saradc-apb"; 1263 #io-channel-cells = <1>; 1264 status = "disabled"; 1265 }; 1266 1267 pwm4: pwm@fe6e0000 { 1268 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1269 reg = <0x0 0xfe6e0000 0x0 0x10>; 1270 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1271 clock-names = "pwm", "pclk"; 1272 pinctrl-0 = <&pwm4_pins>; 1273 pinctrl-names = "default"; 1274 #pwm-cells = <3>; 1275 status = "disabled"; 1276 }; 1277 1278 pwm5: pwm@fe6e0010 { 1279 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1280 reg = <0x0 0xfe6e0010 0x0 0x10>; 1281 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1282 clock-names = "pwm", "pclk"; 1283 pinctrl-0 = <&pwm5_pins>; 1284 pinctrl-names = "default"; 1285 #pwm-cells = <3>; 1286 status = "disabled"; 1287 }; 1288 1289 pwm6: pwm@fe6e0020 { 1290 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1291 reg = <0x0 0xfe6e0020 0x0 0x10>; 1292 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1293 clock-names = "pwm", "pclk"; 1294 pinctrl-0 = <&pwm6_pins>; 1295 pinctrl-names = "default"; 1296 #pwm-cells = <3>; 1297 status = "disabled"; 1298 }; 1299 1300 pwm7: pwm@fe6e0030 { 1301 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1302 reg = <0x0 0xfe6e0030 0x0 0x10>; 1303 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1304 clock-names = "pwm", "pclk"; 1305 pinctrl-0 = <&pwm7_pins>; 1306 pinctrl-names = "default"; 1307 #pwm-cells = <3>; 1308 status = "disabled"; 1309 }; 1310 1311 pwm8: pwm@fe6f0000 { 1312 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1313 reg = <0x0 0xfe6f0000 0x0 0x10>; 1314 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1315 clock-names = "pwm", "pclk"; 1316 pinctrl-0 = <&pwm8m0_pins>; 1317 pinctrl-names = "default"; 1318 #pwm-cells = <3>; 1319 status = "disabled"; 1320 }; 1321 1322 pwm9: pwm@fe6f0010 { 1323 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1324 reg = <0x0 0xfe6f0010 0x0 0x10>; 1325 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1326 clock-names = "pwm", "pclk"; 1327 pinctrl-0 = <&pwm9m0_pins>; 1328 pinctrl-names = "default"; 1329 #pwm-cells = <3>; 1330 status = "disabled"; 1331 }; 1332 1333 pwm10: pwm@fe6f0020 { 1334 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1335 reg = <0x0 0xfe6f0020 0x0 0x10>; 1336 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1337 clock-names = "pwm", "pclk"; 1338 pinctrl-0 = <&pwm10m0_pins>; 1339 pinctrl-names = "default"; 1340 #pwm-cells = <3>; 1341 status = "disabled"; 1342 }; 1343 1344 pwm11: pwm@fe6f0030 { 1345 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1346 reg = <0x0 0xfe6f0030 0x0 0x10>; 1347 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1348 clock-names = "pwm", "pclk"; 1349 pinctrl-0 = <&pwm11m0_pins>; 1350 pinctrl-names = "default"; 1351 #pwm-cells = <3>; 1352 status = "disabled"; 1353 }; 1354 1355 pwm12: pwm@fe700000 { 1356 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1357 reg = <0x0 0xfe700000 0x0 0x10>; 1358 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1359 clock-names = "pwm", "pclk"; 1360 pinctrl-0 = <&pwm12m0_pins>; 1361 pinctrl-names = "default"; 1362 #pwm-cells = <3>; 1363 status = "disabled"; 1364 }; 1365 1366 pwm13: pwm@fe700010 { 1367 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1368 reg = <0x0 0xfe700010 0x0 0x10>; 1369 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1370 clock-names = "pwm", "pclk"; 1371 pinctrl-0 = <&pwm13m0_pins>; 1372 pinctrl-names = "default"; 1373 #pwm-cells = <3>; 1374 status = "disabled"; 1375 }; 1376 1377 pwm14: pwm@fe700020 { 1378 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1379 reg = <0x0 0xfe700020 0x0 0x10>; 1380 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1381 clock-names = "pwm", "pclk"; 1382 pinctrl-0 = <&pwm14m0_pins>; 1383 pinctrl-names = "default"; 1384 #pwm-cells = <3>; 1385 status = "disabled"; 1386 }; 1387 1388 pwm15: pwm@fe700030 { 1389 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1390 reg = <0x0 0xfe700030 0x0 0x10>; 1391 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1392 clock-names = "pwm", "pclk"; 1393 pinctrl-0 = <&pwm15m0_pins>; 1394 pinctrl-names = "default"; 1395 #pwm-cells = <3>; 1396 status = "disabled"; 1397 }; 1398 1399 combphy1: phy@fe830000 { 1400 compatible = "rockchip,rk3568-naneng-combphy"; 1401 reg = <0x0 0xfe830000 0x0 0x100>; 1402 clocks = <&pmucru CLK_PCIEPHY1_REF>, 1403 <&cru PCLK_PIPEPHY1>, 1404 <&cru PCLK_PIPE>; 1405 clock-names = "ref", "apb", "pipe"; 1406 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; 1407 assigned-clock-rates = <100000000>; 1408 resets = <&cru SRST_PIPEPHY1>; 1409 rockchip,pipe-grf = <&pipegrf>; 1410 rockchip,pipe-phy-grf = <&pipe_phy_grf1>; 1411 #phy-cells = <1>; 1412 status = "disabled"; 1413 }; 1414 1415 combphy2: phy@fe840000 { 1416 compatible = "rockchip,rk3568-naneng-combphy"; 1417 reg = <0x0 0xfe840000 0x0 0x100>; 1418 clocks = <&pmucru CLK_PCIEPHY2_REF>, 1419 <&cru PCLK_PIPEPHY2>, 1420 <&cru PCLK_PIPE>; 1421 clock-names = "ref", "apb", "pipe"; 1422 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; 1423 assigned-clock-rates = <100000000>; 1424 resets = <&cru SRST_PIPEPHY2>; 1425 rockchip,pipe-grf = <&pipegrf>; 1426 rockchip,pipe-phy-grf = <&pipe_phy_grf2>; 1427 #phy-cells = <1>; 1428 status = "disabled"; 1429 }; 1430 1431 usb2phy0: usb2phy@fe8a0000 { 1432 compatible = "rockchip,rk3568-usb2phy"; 1433 reg = <0x0 0xfe8a0000 0x0 0x10000>; 1434 clocks = <&pmucru CLK_USBPHY0_REF>; 1435 clock-names = "phyclk"; 1436 clock-output-names = "clk_usbphy0_480m"; 1437 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 1438 rockchip,usbgrf = <&usb2phy0_grf>; 1439 #clock-cells = <0>; 1440 status = "disabled"; 1441 1442 usb2phy0_host: host-port { 1443 #phy-cells = <0>; 1444 status = "disabled"; 1445 }; 1446 1447 usb2phy0_otg: otg-port { 1448 #phy-cells = <0>; 1449 status = "disabled"; 1450 }; 1451 }; 1452 1453 usb2phy1: usb2phy@fe8b0000 { 1454 compatible = "rockchip,rk3568-usb2phy"; 1455 reg = <0x0 0xfe8b0000 0x0 0x10000>; 1456 clocks = <&pmucru CLK_USBPHY1_REF>; 1457 clock-names = "phyclk"; 1458 clock-output-names = "clk_usbphy1_480m"; 1459 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1460 rockchip,usbgrf = <&usb2phy1_grf>; 1461 #clock-cells = <0>; 1462 status = "disabled"; 1463 1464 usb2phy1_host: host-port { 1465 #phy-cells = <0>; 1466 status = "disabled"; 1467 }; 1468 1469 usb2phy1_otg: otg-port { 1470 #phy-cells = <0>; 1471 status = "disabled"; 1472 }; 1473 }; 1474 1475 pinctrl: pinctrl { 1476 compatible = "rockchip,rk3568-pinctrl"; 1477 rockchip,grf = <&grf>; 1478 rockchip,pmu = <&pmugrf>; 1479 #address-cells = <2>; 1480 #size-cells = <2>; 1481 ranges; 1482 1483 gpio0: gpio@fdd60000 { 1484 compatible = "rockchip,gpio-bank"; 1485 reg = <0x0 0xfdd60000 0x0 0x100>; 1486 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1487 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; 1488 gpio-controller; 1489 #gpio-cells = <2>; 1490 interrupt-controller; 1491 #interrupt-cells = <2>; 1492 }; 1493 1494 gpio1: gpio@fe740000 { 1495 compatible = "rockchip,gpio-bank"; 1496 reg = <0x0 0xfe740000 0x0 0x100>; 1497 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1498 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1499 gpio-controller; 1500 #gpio-cells = <2>; 1501 interrupt-controller; 1502 #interrupt-cells = <2>; 1503 }; 1504 1505 gpio2: gpio@fe750000 { 1506 compatible = "rockchip,gpio-bank"; 1507 reg = <0x0 0xfe750000 0x0 0x100>; 1508 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1509 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1510 gpio-controller; 1511 #gpio-cells = <2>; 1512 interrupt-controller; 1513 #interrupt-cells = <2>; 1514 }; 1515 1516 gpio3: gpio@fe760000 { 1517 compatible = "rockchip,gpio-bank"; 1518 reg = <0x0 0xfe760000 0x0 0x100>; 1519 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1520 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1521 gpio-controller; 1522 #gpio-cells = <2>; 1523 interrupt-controller; 1524 #interrupt-cells = <2>; 1525 }; 1526 1527 gpio4: gpio@fe770000 { 1528 compatible = "rockchip,gpio-bank"; 1529 reg = <0x0 0xfe770000 0x0 0x100>; 1530 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1531 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 1532 gpio-controller; 1533 #gpio-cells = <2>; 1534 interrupt-controller; 1535 #interrupt-cells = <2>; 1536 }; 1537 }; 1538}; 1539 1540#include "rk3568-pinctrl.dtsi"