cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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uniphier-pxs3-ref.dts (1979B)

      1// SPDX-License-Identifier: GPL-2.0+ OR MIT
      2//
      3// Device Tree Source for UniPhier PXs3 Reference Board
      4//
      5// Copyright (C) 2017 Socionext Inc.
      6//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
      7
      8/dts-v1/;
      9#include "uniphier-pxs3.dtsi"
     10#include "uniphier-support-card.dtsi"
     11
     12/ {
     13	model = "UniPhier PXs3 Reference Board";
     14	compatible = "socionext,uniphier-pxs3-ref", "socionext,uniphier-pxs3";
     15
     16	chosen {
     17		stdout-path = "serial0:115200n8";
     18	};
     19
     20	aliases {
     21		serial0 = &serial0;
     22		serial1 = &serialsc;
     23		serial2 = &serial2;
     24		serial3 = &serial3;
     25		i2c0 = &i2c0;
     26		i2c1 = &i2c1;
     27		i2c2 = &i2c2;
     28		i2c3 = &i2c3;
     29		i2c6 = &i2c6;
     30		spi0 = &spi0;
     31		spi1 = &spi1;
     32		ethernet0 = &eth0;
     33		ethernet1 = &eth1;
     34	};
     35
     36	memory@80000000 {
     37		device_type = "memory";
     38		reg = <0 0x80000000 0 0xa0000000>;
     39	};
     40};
     41
     42&ethsc {
     43	interrupts = <4 8>;
     44};
     45
     46&serialsc {
     47	interrupts = <4 8>;
     48};
     49
     50&spi0 {
     51	status = "okay";
     52};
     53
     54&spi1 {
     55	status = "okay";
     56};
     57
     58&serial0 {
     59	status = "okay";
     60};
     61
     62&serial2 {
     63	status = "okay";
     64};
     65
     66&serial3 {
     67	status = "okay";
     68};
     69
     70&gpio {
     71	xirq4 {
     72		gpio-hog;
     73		gpios = <UNIPHIER_GPIO_IRQ(4) 0>;
     74		input;
     75	};
     76};
     77
     78&i2c0 {
     79	status = "okay";
     80};
     81
     82&i2c1 {
     83	status = "okay";
     84};
     85
     86&i2c2 {
     87	status = "okay";
     88};
     89
     90&i2c3 {
     91	status = "okay";
     92};
     93
     94&sd {
     95	status = "okay";
     96};
     97
     98&eth0 {
     99	status = "okay";
    100	phy-handle = <&ethphy0>;
    101};
    102
    103&mdio0 {
    104	ethphy0: ethernet-phy@0 {
    105		reg = <0>;
    106	};
    107};
    108
    109&eth1 {
    110	status = "okay";
    111	phy-handle = <&ethphy1>;
    112};
    113
    114&mdio1 {
    115	ethphy1: ethernet-phy@0 {
    116		reg = <0>;
    117	};
    118};
    119
    120&usb0 {
    121	status = "okay";
    122};
    123
    124&usb1 {
    125	status = "okay";
    126};
    127
    128&pcie {
    129	status = "okay";
    130};
    131
    132&nand {
    133	status = "okay";
    134
    135	nand@0 {
    136		reg = <0>;
    137	};
    138};
    139
    140&pinctrl_ether_rgmii {
    141	tx {
    142		pins = "RGMII0_TXCLK", "RGMII0_TXD0", "RGMII0_TXD1",
    143		       "RGMII0_TXD2", "RGMII0_TXD3", "RGMII0_TXCTL";
    144		drive-strength = <9>;
    145	};
    146};
    147
    148&pinctrl_ether1_rgmii {
    149	tx {
    150		pins = "RGMII1_TXCLK", "RGMII1_TXD0", "RGMII1_TXD1",
    151		       "RGMII1_TXD2", "RGMII1_TXD3", "RGMII1_TXCTL";
    152		drive-strength = <9>;
    153	};
    154};