cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

sp9860g-1h10.dts (1467B)

      1/*
      2 * Spreadtrum SP9860g board
      3 *
      4 * Copyright (C) 2017, Spreadtrum Communications Inc.
      5 *
      6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
      7 */
      8
      9/dts-v1/;
     10
     11#include "sc9860.dtsi"
     12#include "sc2731.dtsi"
     13
     14/ {
     15	model = "Spreadtrum SP9860G 3GFHD Board";
     16
     17	compatible = "sprd,sp9860g-1h10", "sprd,sc9860";
     18
     19	aliases {
     20		serial0 = &uart0; /* for Bluetooth */
     21		serial1 = &uart1; /* UART console */
     22		serial2 = &uart2; /* Reserved */
     23		serial3 = &uart3; /* for GPS */
     24		spi0 = &adi_bus;
     25	};
     26
     27	memory{
     28		device_type = "memory";
     29		reg = <0x0 0x80000000 0 0x60000000>,
     30		      <0x1 0x80000000 0 0x60000000>;
     31	};
     32
     33	chosen {
     34		stdout-path = "serial1:115200n8";
     35	};
     36
     37	reserved-memory {
     38		#address-cells = <2>;
     39		#size-cells = <2>;
     40		ranges;
     41	};
     42
     43	bat: battery {
     44		compatible = "simple-battery";
     45		charge-full-design-microamp-hours = <1900000>;
     46		charge-term-current-microamp = <120000>;
     47		constant_charge_voltage_max_microvolt = <4350000>;
     48		internal-resistance-micro-ohms = <250000>;
     49		ocv-capacity-celsius = <20>;
     50		ocv-capacity-table-0 = <4185000 100>, <4113000 95>, <4066000 90>,
     51			<4022000 85>, <3983000 80>, <3949000 75>,
     52			<3917000 70>, <3889000 65>, <3864000 60>,
     53			<3835000 55>, <3805000 50>, <3787000 45>,
     54			<3777000 40>, <3773000 35>, <3770000 30>,
     55			<3765000 25>, <3752000 20>, <3724000 15>,
     56			<3680000 10>, <3605000 5>, <3400000 0>;
     57	};
     58};
     59
     60&uart0 {
     61	status = "okay";
     62};
     63
     64&uart1 {
     65	status = "okay";
     66};
     67
     68&uart2 {
     69	status = "okay";
     70};
     71
     72&uart3 {
     73	status = "okay";
     74};