cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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k3-am6528-iot2050-basic-common.dtsi (1361B)

      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * Copyright (c) Siemens AG, 2018-2021
      4 *
      5 * Authors:
      6 *   Le Jin <le.jin@siemens.com>
      7 *   Jan Kiszka <jan.kiszka@siemens.com>
      8 *
      9 * Common bits of the IOT2050 Basic variant, PG1 and PG2
     10 */
     11
     12#include "k3-am65-iot2050-common.dtsi"
     13
     14/ {
     15	memory@80000000 {
     16		device_type = "memory";
     17		/* 1G RAM */
     18		reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
     19	};
     20
     21	cpus {
     22		cpu-map {
     23			/delete-node/ cluster1;
     24		};
     25		/delete-node/ cpu@100;
     26		/delete-node/ cpu@101;
     27	};
     28
     29	/delete-node/ l2-cache1;
     30};
     31
     32/* eMMC */
     33&sdhci0 {
     34	status = "disabled";
     35};
     36
     37&main_pmx0 {
     38	main_uart0_pins_default: main-uart0-pins-default {
     39		pinctrl-single,pins = <
     40			AM65X_IOPAD(0x01e4, PIN_INPUT,  0)  /* (AF11) UART0_RXD */
     41			AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0)  /* (AE11) UART0_TXD */
     42			AM65X_IOPAD(0x01ec, PIN_INPUT,  0)  /* (AG11) UART0_CTSn */
     43			AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0)  /* (AD11) UART0_RTSn */
     44			AM65X_IOPAD(0x0188, PIN_INPUT,  1)  /* (D25) UART0_DCDn */
     45			AM65X_IOPAD(0x018c, PIN_INPUT,  1)  /* (B26) UART0_DSRn */
     46			AM65X_IOPAD(0x0190, PIN_OUTPUT, 1)  /* (A24) UART0_DTRn */
     47			AM65X_IOPAD(0x0194, PIN_INPUT,  1)  /* (E24) UART0_RIN */
     48		>;
     49	};
     50};
     51
     52&main_uart0 {
     53	pinctrl-names = "default";
     54	pinctrl-0 = <&main_uart0_pins_default>;
     55};
     56
     57&mcu_r5fss0 {
     58	/* lock-step mode not supported on Basic boards */
     59	ti,cluster-mode = <0>;
     60};