cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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k3-am654-base-board.dts (13035B)


      1// SPDX-License-Identifier: GPL-2.0
      2/*
      3 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
      4 */
      5
      6/dts-v1/;
      7
      8#include "k3-am654.dtsi"
      9#include <dt-bindings/input/input.h>
     10#include <dt-bindings/net/ti-dp83867.h>
     11
     12/ {
     13	compatible =  "ti,am654-evm", "ti,am654";
     14	model = "Texas Instruments AM654 Base Board";
     15
     16	chosen {
     17		stdout-path = "serial2:115200n8";
     18		bootargs = "earlycon=ns16550a,mmio32,0x02800000";
     19	};
     20
     21	memory@80000000 {
     22		device_type = "memory";
     23		/* 4G RAM */
     24		reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
     25		      <0x00000008 0x80000000 0x00000000 0x80000000>;
     26	};
     27
     28	reserved-memory {
     29		#address-cells = <2>;
     30		#size-cells = <2>;
     31		ranges;
     32
     33		secure_ddr: secure-ddr@9e800000 {
     34			reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
     35			alignment = <0x1000>;
     36			no-map;
     37		};
     38
     39		mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
     40			compatible = "shared-dma-pool";
     41			reg = <0 0xa0000000 0 0x100000>;
     42			no-map;
     43		};
     44
     45		mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
     46			compatible = "shared-dma-pool";
     47			reg = <0 0xa0100000 0 0xf00000>;
     48			no-map;
     49		};
     50
     51		mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
     52			compatible = "shared-dma-pool";
     53			reg = <0 0xa1000000 0 0x100000>;
     54			no-map;
     55		};
     56
     57		mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
     58			compatible = "shared-dma-pool";
     59			reg = <0 0xa1100000 0 0xf00000>;
     60			no-map;
     61		};
     62
     63		rtos_ipc_memory_region: ipc-memories@a2000000 {
     64			reg = <0x00 0xa2000000 0x00 0x00100000>;
     65			alignment = <0x1000>;
     66			no-map;
     67		};
     68	};
     69
     70	gpio-keys {
     71		compatible = "gpio-keys";
     72		autorepeat;
     73		pinctrl-names = "default";
     74		pinctrl-0 = <&push_button_pins_default>;
     75
     76		sw5 {
     77			label = "GPIO Key USER1";
     78			linux,code = <BTN_0>;
     79			gpios = <&wkup_gpio0 24 GPIO_ACTIVE_LOW>;
     80		};
     81
     82		sw6 {
     83			label = "GPIO Key USER2";
     84			linux,code = <BTN_1>;
     85			gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>;
     86		};
     87	};
     88
     89	evm_12v0: fixedregulator-evm12v0 {
     90		/* main supply */
     91		compatible = "regulator-fixed";
     92		regulator-name = "evm_12v0";
     93		regulator-min-microvolt = <12000000>;
     94		regulator-max-microvolt = <12000000>;
     95		regulator-always-on;
     96		regulator-boot-on;
     97	};
     98
     99	vcc3v3_io: fixedregulator-vcc3v3io {
    100		/* Output of TPS54334 */
    101		compatible = "regulator-fixed";
    102		regulator-name = "vcc3v3_io";
    103		regulator-min-microvolt = <3300000>;
    104		regulator-max-microvolt = <3300000>;
    105		regulator-always-on;
    106		regulator-boot-on;
    107		vin-supply = <&evm_12v0>;
    108	};
    109
    110	vdd_mmc1_sd: fixedregulator-sd {
    111		compatible = "regulator-fixed";
    112		regulator-name = "vdd_mmc1_sd";
    113		regulator-min-microvolt = <3300000>;
    114		regulator-max-microvolt = <3300000>;
    115		regulator-boot-on;
    116		enable-active-high;
    117		vin-supply = <&vcc3v3_io>;
    118		gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>;
    119	};
    120};
    121
    122&wkup_pmx0 {
    123	wkup_i2c0_pins_default: wkup-i2c0-pins-default {
    124		pinctrl-single,pins = <
    125			AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
    126			AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
    127		>;
    128	};
    129
    130	push_button_pins_default: push-button-pins-default {
    131		pinctrl-single,pins = <
    132			AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */
    133			AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */
    134		>;
    135	};
    136
    137	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
    138		pinctrl-single,pins = <
    139			AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
    140			AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0)	 /* (U2) MCU_OSPI0_DQS */
    141			AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0)  /* (U4) MCU_OSPI0_D0 */
    142			AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0)  /* (U5) MCU_OSPI0_D1 */
    143			AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0)  /* (T2) MCU_OSPI0_D2 */
    144			AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0)  /* (T3) MCU_OSPI0_D3 */
    145			AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0)  /* (T4) MCU_OSPI0_D4 */
    146			AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0)  /* (T5) MCU_OSPI0_D5 */
    147			AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0)  /* (R2) MCU_OSPI0_D6 */
    148			AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0)  /* (R3) MCU_OSPI0_D7 */
    149			AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */
    150		>;
    151	};
    152
    153	wkup_pca554_default: wkup-pca554-default {
    154		pinctrl-single,pins = <
    155			AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
    156		>;
    157	};
    158
    159	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
    160		pinctrl-single,pins = <
    161			AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
    162			AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
    163			AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
    164			AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
    165			AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
    166			AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
    167			AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
    168			AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
    169			AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
    170			AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
    171			AM65X_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* (N1) MCU_RGMII1_TXC */
    172			AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
    173		>;
    174	};
    175
    176	mcu_mdio_pins_default: mcu-mdio1-pins-default {
    177		pinctrl-single,pins = <
    178			AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
    179			AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
    180		>;
    181	};
    182};
    183
    184&main_pmx0 {
    185	main_uart0_pins_default: main-uart0-pins-default {
    186		pinctrl-single,pins = <
    187			AM65X_IOPAD(0x01e4, PIN_INPUT, 0)	/* (AF11) UART0_RXD */
    188			AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0)	/* (AE11) UART0_TXD */
    189			AM65X_IOPAD(0x01ec, PIN_INPUT, 0)	/* (AG11) UART0_CTSn */
    190			AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0)	/* (AD11) UART0_RTSn */
    191		>;
    192	};
    193
    194	main_i2c2_pins_default: main-i2c2-pins-default {
    195		pinctrl-single,pins = <
    196			AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) GPMC0_CSn3.I2C2_SCL */
    197			AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */
    198		>;
    199	};
    200
    201	main_spi0_pins_default: main-spi0-pins-default {
    202		pinctrl-single,pins = <
    203			AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */
    204			AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */
    205			AM65X_IOPAD(0x01cc, PIN_INPUT, 0) /* (AD13) SPI0_D1 */
    206			AM65X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (AG13) SPI0_CS0 */
    207		>;
    208	};
    209
    210	main_mmc0_pins_default: main-mmc0-pins-default {
    211		pinctrl-single,pins = <
    212			AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
    213			AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
    214			AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
    215			AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
    216			AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
    217			AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
    218			AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
    219			AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
    220			AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
    221			AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
    222			AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
    223			AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
    224		>;
    225	};
    226
    227	main_mmc1_pins_default: main-mmc1-pins-default {
    228		pinctrl-single,pins = <
    229			AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
    230			AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
    231			AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
    232			AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
    233			AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
    234			AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
    235			AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
    236			AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
    237		>;
    238	};
    239
    240	usb1_pins_default: usb1-pins-default {
    241		pinctrl-single,pins = <
    242			AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
    243		>;
    244	};
    245};
    246
    247&main_pmx1 {
    248	main_i2c0_pins_default: main-i2c0-pins-default {
    249		pinctrl-single,pins = <
    250			AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */
    251			AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */
    252		>;
    253	};
    254
    255	main_i2c1_pins_default: main-i2c1-pins-default {
    256		pinctrl-single,pins = <
    257			AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */
    258			AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
    259		>;
    260	};
    261
    262	ecap0_pins_default: ecap0-pins-default {
    263		pinctrl-single,pins = <
    264			AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
    265		>;
    266	};
    267};
    268
    269&wkup_uart0 {
    270	/* Wakeup UART is used by System firmware */
    271	status = "reserved";
    272};
    273
    274&main_uart0 {
    275	pinctrl-names = "default";
    276	pinctrl-0 = <&main_uart0_pins_default>;
    277	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
    278};
    279
    280&wkup_i2c0 {
    281	pinctrl-names = "default";
    282	pinctrl-0 = <&wkup_i2c0_pins_default>;
    283	clock-frequency = <400000>;
    284
    285	pca9554: gpio@39 {
    286		compatible = "nxp,pca9554";
    287		reg = <0x39>;
    288		gpio-controller;
    289		#gpio-cells = <2>;
    290		pinctrl-names = "default";
    291		pinctrl-0 = <&wkup_pca554_default>;
    292		interrupt-parent = <&wkup_gpio0>;
    293		interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
    294		interrupt-controller;
    295		#interrupt-cells = <2>;
    296	};
    297};
    298
    299&main_i2c0 {
    300	pinctrl-names = "default";
    301	pinctrl-0 = <&main_i2c0_pins_default>;
    302	clock-frequency = <400000>;
    303
    304	pca9555: gpio@21 {
    305		compatible = "nxp,pca9555";
    306		reg = <0x21>;
    307		gpio-controller;
    308		#gpio-cells = <2>;
    309	};
    310};
    311
    312&main_i2c1 {
    313	pinctrl-names = "default";
    314	pinctrl-0 = <&main_i2c1_pins_default>;
    315	clock-frequency = <400000>;
    316};
    317
    318&main_i2c2 {
    319	pinctrl-names = "default";
    320	pinctrl-0 = <&main_i2c2_pins_default>;
    321	clock-frequency = <400000>;
    322};
    323
    324&ecap0 {
    325	pinctrl-names = "default";
    326	pinctrl-0 = <&ecap0_pins_default>;
    327};
    328
    329&main_spi0 {
    330	pinctrl-names = "default";
    331	pinctrl-0 = <&main_spi0_pins_default>;
    332	#address-cells = <1>;
    333	#size-cells= <0>;
    334	ti,pindir-d0-out-d1-in;
    335
    336	flash@0 {
    337		compatible = "jedec,spi-nor";
    338		reg = <0x0>;
    339		spi-tx-bus-width = <1>;
    340		spi-rx-bus-width = <1>;
    341		spi-max-frequency = <48000000>;
    342	};
    343};
    344
    345&sdhci0 {
    346	pinctrl-names = "default";
    347	pinctrl-0 = <&main_mmc0_pins_default>;
    348	bus-width = <8>;
    349	non-removable;
    350	ti,driver-strength-ohm = <50>;
    351	disable-wp;
    352};
    353
    354/*
    355 * Because of erratas i2025 and i2026 for silicon revision 1.0, the
    356 * SD card interface might fail. Boards with sr1.0 are recommended to
    357 * disable sdhci1
    358 */
    359&sdhci1 {
    360	vmmc-supply = <&vdd_mmc1_sd>;
    361	pinctrl-names = "default";
    362	pinctrl-0 = <&main_mmc1_pins_default>;
    363	ti,driver-strength-ohm = <50>;
    364	disable-wp;
    365};
    366
    367&usb1 {
    368	pinctrl-names = "default";
    369	pinctrl-0 = <&usb1_pins_default>;
    370	dr_mode = "otg";
    371};
    372
    373&dwc3_0 {
    374	status = "disabled";
    375};
    376
    377&usb0_phy {
    378	status = "disabled";
    379};
    380
    381&tscadc0 {
    382	adc {
    383		ti,adc-channels = <0 1 2 3 4 5 6 7>;
    384	};
    385};
    386
    387&tscadc1 {
    388	adc {
    389		ti,adc-channels = <0 1 2 3 4 5 6 7>;
    390	};
    391};
    392
    393&serdes0 {
    394	status = "disabled";
    395};
    396
    397&serdes1 {
    398	status = "disabled";
    399};
    400
    401&pcie0_rc {
    402	status = "disabled";
    403};
    404
    405&pcie0_ep {
    406	status = "disabled";
    407};
    408
    409&pcie1_rc {
    410	status = "disabled";
    411};
    412
    413&pcie1_ep {
    414	status = "disabled";
    415};
    416
    417&m_can0 {
    418	status = "disabled";
    419};
    420
    421&m_can1 {
    422	status = "disabled";
    423};
    424
    425&mailbox0_cluster0 {
    426	interrupts = <436>;
    427
    428	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
    429		ti,mbox-tx = <1 0 0>;
    430		ti,mbox-rx = <0 0 0>;
    431	};
    432};
    433
    434&mailbox0_cluster1 {
    435	interrupts = <432>;
    436
    437	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
    438		ti,mbox-tx = <1 0 0>;
    439		ti,mbox-rx = <0 0 0>;
    440	};
    441};
    442
    443&mailbox0_cluster2 {
    444	status = "disabled";
    445};
    446
    447&mailbox0_cluster3 {
    448	status = "disabled";
    449};
    450
    451&mailbox0_cluster4 {
    452	status = "disabled";
    453};
    454
    455&mailbox0_cluster5 {
    456	status = "disabled";
    457};
    458
    459&mailbox0_cluster6 {
    460	status = "disabled";
    461};
    462
    463&mailbox0_cluster7 {
    464	status = "disabled";
    465};
    466
    467&mailbox0_cluster8 {
    468	status = "disabled";
    469};
    470
    471&mailbox0_cluster9 {
    472	status = "disabled";
    473};
    474
    475&mailbox0_cluster10 {
    476	status = "disabled";
    477};
    478
    479&mailbox0_cluster11 {
    480	status = "disabled";
    481};
    482
    483&mcu_r5fss0_core0 {
    484	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
    485			<&mcu_r5fss0_core0_memory_region>;
    486	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
    487};
    488
    489&mcu_r5fss0_core1 {
    490	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
    491			<&mcu_r5fss0_core1_memory_region>;
    492	mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
    493};
    494
    495&ospi0 {
    496	pinctrl-names = "default";
    497	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
    498
    499	flash@0 {
    500		compatible = "jedec,spi-nor";
    501		reg = <0x0>;
    502		spi-tx-bus-width = <8>;
    503		spi-rx-bus-width = <8>;
    504		spi-max-frequency = <25000000>;
    505		cdns,tshsl-ns = <60>;
    506		cdns,tsd2d-ns = <60>;
    507		cdns,tchsh-ns = <60>;
    508		cdns,tslch-ns = <60>;
    509		cdns,read-delay = <0>;
    510	};
    511};
    512
    513&mcu_cpsw {
    514	pinctrl-names = "default";
    515	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
    516};
    517
    518&davinci_mdio {
    519	phy0: ethernet-phy@0 {
    520		reg = <0>;
    521		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
    522		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
    523	};
    524};
    525
    526&cpsw_port1 {
    527	phy-mode = "rgmii-rxid";
    528	phy-handle = <&phy0>;
    529};
    530
    531&mcasp0 {
    532	status = "disabled";
    533};
    534
    535&mcasp1 {
    536	status = "disabled";
    537};
    538
    539&mcasp2 {
    540	status = "disabled";
    541};
    542
    543&dss {
    544	status = "disabled";
    545};
    546
    547&icssg0_mdio {
    548	status = "disabled";
    549};
    550
    551&icssg1_mdio {
    552	status = "disabled";
    553};
    554
    555&icssg2_mdio {
    556	status = "disabled";
    557};