k3-j7200-main.dtsi (22556B)
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J7200 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8/ { 9 serdes_refclk: serdes-refclk { 10 #clock-cells = <0>; 11 compatible = "fixed-clock"; 12 }; 13}; 14 15&cbass_main { 16 msmc_ram: sram@70000000 { 17 compatible = "mmio-sram"; 18 reg = <0x00 0x70000000 0x00 0x100000>; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 ranges = <0x00 0x00 0x70000000 0x100000>; 22 23 atf-sram@0 { 24 reg = <0x00 0x20000>; 25 }; 26 }; 27 28 scm_conf: scm-conf@100000 { 29 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 30 reg = <0x00 0x00100000 0x00 0x1c000>; 31 #address-cells = <1>; 32 #size-cells = <1>; 33 ranges = <0x00 0x00 0x00100000 0x1c000>; 34 35 serdes_ln_ctrl: mux-controller@4080 { 36 compatible = "mmio-mux"; 37 #mux-control-cells = <1>; 38 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ 39 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ 40 }; 41 42 usb_serdes_mux: mux-controller@4000 { 43 compatible = "mmio-mux"; 44 #mux-control-cells = <1>; 45 mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ 46 }; 47 }; 48 49 gic500: interrupt-controller@1800000 { 50 compatible = "arm,gic-v3"; 51 #address-cells = <2>; 52 #size-cells = <2>; 53 ranges; 54 #interrupt-cells = <3>; 55 interrupt-controller; 56 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 57 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 58 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 59 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 60 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 61 62 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 63 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 64 65 gic_its: msi-controller@1820000 { 66 compatible = "arm,gic-v3-its"; 67 reg = <0x00 0x01820000 0x00 0x10000>; 68 socionext,synquacer-pre-its = <0x1000000 0x400000>; 69 msi-controller; 70 #msi-cells = <1>; 71 }; 72 }; 73 74 main_gpio_intr: interrupt-controller@a00000 { 75 compatible = "ti,sci-intr"; 76 reg = <0x00 0x00a00000 0x00 0x800>; 77 ti,intr-trigger-type = <1>; 78 interrupt-controller; 79 interrupt-parent = <&gic500>; 80 #interrupt-cells = <1>; 81 ti,sci = <&dmsc>; 82 ti,sci-dev-id = <131>; 83 ti,interrupt-ranges = <8 392 56>; 84 }; 85 86 main_navss: bus@30000000 { 87 compatible = "simple-mfd"; 88 #address-cells = <2>; 89 #size-cells = <2>; 90 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 91 ti,sci-dev-id = <199>; 92 dma-coherent; 93 dma-ranges; 94 95 main_navss_intr: interrupt-controller@310e0000 { 96 compatible = "ti,sci-intr"; 97 reg = <0x00 0x310e0000 0x00 0x4000>; 98 ti,intr-trigger-type = <4>; 99 interrupt-controller; 100 interrupt-parent = <&gic500>; 101 #interrupt-cells = <1>; 102 ti,sci = <&dmsc>; 103 ti,sci-dev-id = <213>; 104 ti,interrupt-ranges = <0 64 64>, 105 <64 448 64>, 106 <128 672 64>; 107 }; 108 109 main_udmass_inta: msi-controller@33d00000 { 110 compatible = "ti,sci-inta"; 111 reg = <0x00 0x33d00000 0x00 0x100000>; 112 interrupt-controller; 113 #interrupt-cells = <0>; 114 interrupt-parent = <&main_navss_intr>; 115 msi-controller; 116 ti,sci = <&dmsc>; 117 ti,sci-dev-id = <209>; 118 ti,interrupt-ranges = <0 0 256>; 119 }; 120 121 secure_proxy_main: mailbox@32c00000 { 122 compatible = "ti,am654-secure-proxy"; 123 #mbox-cells = <1>; 124 reg-names = "target_data", "rt", "scfg"; 125 reg = <0x00 0x32c00000 0x00 0x100000>, 126 <0x00 0x32400000 0x00 0x100000>, 127 <0x00 0x32800000 0x00 0x100000>; 128 interrupt-names = "rx_011"; 129 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 130 }; 131 132 hwspinlock: spinlock@30e00000 { 133 compatible = "ti,am654-hwspinlock"; 134 reg = <0x00 0x30e00000 0x00 0x1000>; 135 #hwlock-cells = <1>; 136 }; 137 138 mailbox0_cluster0: mailbox@31f80000 { 139 compatible = "ti,am654-mailbox"; 140 reg = <0x00 0x31f80000 0x00 0x200>; 141 #mbox-cells = <1>; 142 ti,mbox-num-users = <4>; 143 ti,mbox-num-fifos = <16>; 144 interrupt-parent = <&main_navss_intr>; 145 }; 146 147 mailbox0_cluster1: mailbox@31f81000 { 148 compatible = "ti,am654-mailbox"; 149 reg = <0x00 0x31f81000 0x00 0x200>; 150 #mbox-cells = <1>; 151 ti,mbox-num-users = <4>; 152 ti,mbox-num-fifos = <16>; 153 interrupt-parent = <&main_navss_intr>; 154 }; 155 156 mailbox0_cluster2: mailbox@31f82000 { 157 compatible = "ti,am654-mailbox"; 158 reg = <0x00 0x31f82000 0x00 0x200>; 159 #mbox-cells = <1>; 160 ti,mbox-num-users = <4>; 161 ti,mbox-num-fifos = <16>; 162 interrupt-parent = <&main_navss_intr>; 163 }; 164 165 mailbox0_cluster3: mailbox@31f83000 { 166 compatible = "ti,am654-mailbox"; 167 reg = <0x00 0x31f83000 0x00 0x200>; 168 #mbox-cells = <1>; 169 ti,mbox-num-users = <4>; 170 ti,mbox-num-fifos = <16>; 171 interrupt-parent = <&main_navss_intr>; 172 }; 173 174 mailbox0_cluster4: mailbox@31f84000 { 175 compatible = "ti,am654-mailbox"; 176 reg = <0x00 0x31f84000 0x00 0x200>; 177 #mbox-cells = <1>; 178 ti,mbox-num-users = <4>; 179 ti,mbox-num-fifos = <16>; 180 interrupt-parent = <&main_navss_intr>; 181 }; 182 183 mailbox0_cluster5: mailbox@31f85000 { 184 compatible = "ti,am654-mailbox"; 185 reg = <0x00 0x31f85000 0x00 0x200>; 186 #mbox-cells = <1>; 187 ti,mbox-num-users = <4>; 188 ti,mbox-num-fifos = <16>; 189 interrupt-parent = <&main_navss_intr>; 190 }; 191 192 mailbox0_cluster6: mailbox@31f86000 { 193 compatible = "ti,am654-mailbox"; 194 reg = <0x00 0x31f86000 0x00 0x200>; 195 #mbox-cells = <1>; 196 ti,mbox-num-users = <4>; 197 ti,mbox-num-fifos = <16>; 198 interrupt-parent = <&main_navss_intr>; 199 }; 200 201 mailbox0_cluster7: mailbox@31f87000 { 202 compatible = "ti,am654-mailbox"; 203 reg = <0x00 0x31f87000 0x00 0x200>; 204 #mbox-cells = <1>; 205 ti,mbox-num-users = <4>; 206 ti,mbox-num-fifos = <16>; 207 interrupt-parent = <&main_navss_intr>; 208 }; 209 210 mailbox0_cluster8: mailbox@31f88000 { 211 compatible = "ti,am654-mailbox"; 212 reg = <0x00 0x31f88000 0x00 0x200>; 213 #mbox-cells = <1>; 214 ti,mbox-num-users = <4>; 215 ti,mbox-num-fifos = <16>; 216 interrupt-parent = <&main_navss_intr>; 217 }; 218 219 mailbox0_cluster9: mailbox@31f89000 { 220 compatible = "ti,am654-mailbox"; 221 reg = <0x00 0x31f89000 0x00 0x200>; 222 #mbox-cells = <1>; 223 ti,mbox-num-users = <4>; 224 ti,mbox-num-fifos = <16>; 225 interrupt-parent = <&main_navss_intr>; 226 }; 227 228 mailbox0_cluster10: mailbox@31f8a000 { 229 compatible = "ti,am654-mailbox"; 230 reg = <0x00 0x31f8a000 0x00 0x200>; 231 #mbox-cells = <1>; 232 ti,mbox-num-users = <4>; 233 ti,mbox-num-fifos = <16>; 234 interrupt-parent = <&main_navss_intr>; 235 }; 236 237 mailbox0_cluster11: mailbox@31f8b000 { 238 compatible = "ti,am654-mailbox"; 239 reg = <0x00 0x31f8b000 0x00 0x200>; 240 #mbox-cells = <1>; 241 ti,mbox-num-users = <4>; 242 ti,mbox-num-fifos = <16>; 243 interrupt-parent = <&main_navss_intr>; 244 }; 245 246 main_ringacc: ringacc@3c000000 { 247 compatible = "ti,am654-navss-ringacc"; 248 reg = <0x00 0x3c000000 0x00 0x400000>, 249 <0x00 0x38000000 0x00 0x400000>, 250 <0x00 0x31120000 0x00 0x100>, 251 <0x00 0x33000000 0x00 0x40000>; 252 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 253 ti,num-rings = <1024>; 254 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 255 ti,sci = <&dmsc>; 256 ti,sci-dev-id = <211>; 257 msi-parent = <&main_udmass_inta>; 258 }; 259 260 main_udmap: dma-controller@31150000 { 261 compatible = "ti,j721e-navss-main-udmap"; 262 reg = <0x00 0x31150000 0x00 0x100>, 263 <0x00 0x34000000 0x00 0x100000>, 264 <0x00 0x35000000 0x00 0x100000>; 265 reg-names = "gcfg", "rchanrt", "tchanrt"; 266 msi-parent = <&main_udmass_inta>; 267 #dma-cells = <1>; 268 269 ti,sci = <&dmsc>; 270 ti,sci-dev-id = <212>; 271 ti,ringacc = <&main_ringacc>; 272 273 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 274 <0x0f>, /* TX_HCHAN */ 275 <0x10>; /* TX_UHCHAN */ 276 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 277 <0x0b>, /* RX_HCHAN */ 278 <0x0c>; /* RX_UHCHAN */ 279 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 280 }; 281 282 cpts@310d0000 { 283 compatible = "ti,j721e-cpts"; 284 reg = <0x00 0x310d0000 0x00 0x400>; 285 reg-names = "cpts"; 286 clocks = <&k3_clks 201 1>; 287 clock-names = "cpts"; 288 interrupts-extended = <&main_navss_intr 391>; 289 interrupt-names = "cpts"; 290 ti,cpts-periodic-outputs = <6>; 291 ti,cpts-ext-ts-inputs = <8>; 292 }; 293 }; 294 295 main_pmx0: pinctrl@11c000 { 296 compatible = "pinctrl-single"; 297 /* Proxy 0 addressing */ 298 reg = <0x00 0x11c000 0x00 0x2b4>; 299 #pinctrl-cells = <1>; 300 pinctrl-single,register-width = <32>; 301 pinctrl-single,function-mask = <0xffffffff>; 302 }; 303 304 main_uart0: serial@2800000 { 305 compatible = "ti,j721e-uart", "ti,am654-uart"; 306 reg = <0x00 0x02800000 0x00 0x100>; 307 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 308 clock-frequency = <48000000>; 309 current-speed = <115200>; 310 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 311 clocks = <&k3_clks 146 2>; 312 clock-names = "fclk"; 313 }; 314 315 main_uart1: serial@2810000 { 316 compatible = "ti,j721e-uart", "ti,am654-uart"; 317 reg = <0x00 0x02810000 0x00 0x100>; 318 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 319 clock-frequency = <48000000>; 320 current-speed = <115200>; 321 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 322 clocks = <&k3_clks 278 2>; 323 clock-names = "fclk"; 324 }; 325 326 main_uart2: serial@2820000 { 327 compatible = "ti,j721e-uart", "ti,am654-uart"; 328 reg = <0x00 0x02820000 0x00 0x100>; 329 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 330 clock-frequency = <48000000>; 331 current-speed = <115200>; 332 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 333 clocks = <&k3_clks 279 2>; 334 clock-names = "fclk"; 335 }; 336 337 main_uart3: serial@2830000 { 338 compatible = "ti,j721e-uart", "ti,am654-uart"; 339 reg = <0x00 0x02830000 0x00 0x100>; 340 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 341 clock-frequency = <48000000>; 342 current-speed = <115200>; 343 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>; 344 clocks = <&k3_clks 280 2>; 345 clock-names = "fclk"; 346 }; 347 348 main_uart4: serial@2840000 { 349 compatible = "ti,j721e-uart", "ti,am654-uart"; 350 reg = <0x00 0x02840000 0x00 0x100>; 351 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 352 clock-frequency = <48000000>; 353 current-speed = <115200>; 354 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>; 355 clocks = <&k3_clks 281 2>; 356 clock-names = "fclk"; 357 }; 358 359 main_uart5: serial@2850000 { 360 compatible = "ti,j721e-uart", "ti,am654-uart"; 361 reg = <0x00 0x02850000 0x00 0x100>; 362 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 363 clock-frequency = <48000000>; 364 current-speed = <115200>; 365 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>; 366 clocks = <&k3_clks 282 2>; 367 clock-names = "fclk"; 368 }; 369 370 main_uart6: serial@2860000 { 371 compatible = "ti,j721e-uart", "ti,am654-uart"; 372 reg = <0x00 0x02860000 0x00 0x100>; 373 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 374 clock-frequency = <48000000>; 375 current-speed = <115200>; 376 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>; 377 clocks = <&k3_clks 283 2>; 378 clock-names = "fclk"; 379 }; 380 381 main_uart7: serial@2870000 { 382 compatible = "ti,j721e-uart", "ti,am654-uart"; 383 reg = <0x00 0x02870000 0x00 0x100>; 384 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 385 clock-frequency = <48000000>; 386 current-speed = <115200>; 387 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>; 388 clocks = <&k3_clks 284 2>; 389 clock-names = "fclk"; 390 }; 391 392 main_uart8: serial@2880000 { 393 compatible = "ti,j721e-uart", "ti,am654-uart"; 394 reg = <0x00 0x02880000 0x00 0x100>; 395 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 396 clock-frequency = <48000000>; 397 current-speed = <115200>; 398 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>; 399 clocks = <&k3_clks 285 2>; 400 clock-names = "fclk"; 401 }; 402 403 main_uart9: serial@2890000 { 404 compatible = "ti,j721e-uart", "ti,am654-uart"; 405 reg = <0x00 0x02890000 0x00 0x100>; 406 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 407 clock-frequency = <48000000>; 408 current-speed = <115200>; 409 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>; 410 clocks = <&k3_clks 286 2>; 411 clock-names = "fclk"; 412 }; 413 414 main_i2c0: i2c@2000000 { 415 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 416 reg = <0x00 0x2000000 0x00 0x100>; 417 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 418 #address-cells = <1>; 419 #size-cells = <0>; 420 clock-names = "fck"; 421 clocks = <&k3_clks 187 1>; 422 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>; 423 }; 424 425 main_i2c1: i2c@2010000 { 426 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 427 reg = <0x00 0x2010000 0x00 0x100>; 428 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 429 #address-cells = <1>; 430 #size-cells = <0>; 431 clock-names = "fck"; 432 clocks = <&k3_clks 188 1>; 433 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; 434 }; 435 436 main_i2c2: i2c@2020000 { 437 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 438 reg = <0x00 0x2020000 0x00 0x100>; 439 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 clock-names = "fck"; 443 clocks = <&k3_clks 189 1>; 444 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; 445 }; 446 447 main_i2c3: i2c@2030000 { 448 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 449 reg = <0x00 0x2030000 0x00 0x100>; 450 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 451 #address-cells = <1>; 452 #size-cells = <0>; 453 clock-names = "fck"; 454 clocks = <&k3_clks 190 1>; 455 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 456 }; 457 458 main_i2c4: i2c@2040000 { 459 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 460 reg = <0x00 0x2040000 0x00 0x100>; 461 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 462 #address-cells = <1>; 463 #size-cells = <0>; 464 clock-names = "fck"; 465 clocks = <&k3_clks 191 1>; 466 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 467 }; 468 469 main_i2c5: i2c@2050000 { 470 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 471 reg = <0x00 0x2050000 0x00 0x100>; 472 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 clock-names = "fck"; 476 clocks = <&k3_clks 192 1>; 477 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 478 }; 479 480 main_i2c6: i2c@2060000 { 481 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 482 reg = <0x00 0x2060000 0x00 0x100>; 483 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 484 #address-cells = <1>; 485 #size-cells = <0>; 486 clock-names = "fck"; 487 clocks = <&k3_clks 193 1>; 488 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>; 489 }; 490 491 main_sdhci0: mmc@4f80000 { 492 compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit"; 493 reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>; 494 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 495 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 496 clock-names = "clk_ahb", "clk_xin"; 497 clocks = <&k3_clks 91 0>, <&k3_clks 91 3>; 498 ti,otap-del-sel-legacy = <0x0>; 499 ti,otap-del-sel-mmc-hs = <0x0>; 500 ti,otap-del-sel-ddr52 = <0x6>; 501 ti,otap-del-sel-hs200 = <0x8>; 502 ti,otap-del-sel-hs400 = <0x5>; 503 ti,itap-del-sel-legacy = <0x10>; 504 ti,itap-del-sel-mmc-hs = <0xa>; 505 ti,strobe-sel = <0x77>; 506 ti,clkbuf-sel = <0x7>; 507 ti,trm-icp = <0x8>; 508 bus-width = <8>; 509 mmc-ddr-1_8v; 510 mmc-hs200-1_8v; 511 mmc-hs400-1_8v; 512 dma-coherent; 513 }; 514 515 main_sdhci1: mmc@4fb0000 { 516 compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit"; 517 reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>; 518 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 519 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 520 clock-names = "clk_ahb", "clk_xin"; 521 clocks = <&k3_clks 92 1>, <&k3_clks 92 2>; 522 ti,otap-del-sel-legacy = <0x0>; 523 ti,otap-del-sel-sd-hs = <0x0>; 524 ti,otap-del-sel-sdr12 = <0xf>; 525 ti,otap-del-sel-sdr25 = <0xf>; 526 ti,otap-del-sel-sdr50 = <0xc>; 527 ti,otap-del-sel-sdr104 = <0x5>; 528 ti,otap-del-sel-ddr50 = <0xc>; 529 ti,itap-del-sel-legacy = <0x0>; 530 ti,itap-del-sel-sd-hs = <0x0>; 531 ti,itap-del-sel-sdr12 = <0x0>; 532 ti,itap-del-sel-sdr25 = <0x0>; 533 ti,clkbuf-sel = <0x7>; 534 ti,trm-icp = <0x8>; 535 dma-coherent; 536 }; 537 538 serdes_wiz0: wiz@5060000 { 539 compatible = "ti,j721e-wiz-10g"; 540 #address-cells = <1>; 541 #size-cells = <1>; 542 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 543 clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>; 544 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 545 num-lanes = <4>; 546 #reset-cells = <1>; 547 ranges = <0x5060000 0x0 0x5060000 0x10000>; 548 549 assigned-clocks = <&k3_clks 292 85>; 550 assigned-clock-parents = <&k3_clks 292 89>; 551 552 wiz0_pll0_refclk: pll0-refclk { 553 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 554 clock-output-names = "wiz0_pll0_refclk"; 555 #clock-cells = <0>; 556 assigned-clocks = <&wiz0_pll0_refclk>; 557 assigned-clock-parents = <&k3_clks 292 85>; 558 }; 559 560 wiz0_pll1_refclk: pll1-refclk { 561 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 562 clock-output-names = "wiz0_pll1_refclk"; 563 #clock-cells = <0>; 564 assigned-clocks = <&wiz0_pll1_refclk>; 565 assigned-clock-parents = <&k3_clks 292 85>; 566 }; 567 568 wiz0_refclk_dig: refclk-dig { 569 clocks = <&k3_clks 292 85>, <&serdes_refclk>; 570 clock-output-names = "wiz0_refclk_dig"; 571 #clock-cells = <0>; 572 assigned-clocks = <&wiz0_refclk_dig>; 573 assigned-clock-parents = <&k3_clks 292 85>; 574 }; 575 576 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div { 577 clocks = <&wiz0_refclk_dig>; 578 #clock-cells = <0>; 579 }; 580 581 serdes0: serdes@5060000 { 582 compatible = "ti,j721e-serdes-10g"; 583 reg = <0x05060000 0x00010000>; 584 reg-names = "torrent_phy"; 585 resets = <&serdes_wiz0 0>; 586 reset-names = "torrent_reset"; 587 clocks = <&wiz0_pll0_refclk>; 588 clock-names = "refclk"; 589 #address-cells = <1>; 590 #size-cells = <0>; 591 }; 592 }; 593 594 pcie1_rc: pcie@2910000 { 595 compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host"; 596 reg = <0x00 0x02910000 0x00 0x1000>, 597 <0x00 0x02917000 0x00 0x400>, 598 <0x00 0x0d800000 0x00 0x00800000>, 599 <0x00 0x18000000 0x00 0x00001000>; 600 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 601 interrupt-names = "link_state"; 602 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 603 device_type = "pci"; 604 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 605 max-link-speed = <3>; 606 num-lanes = <4>; 607 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 608 clocks = <&k3_clks 240 6>; 609 clock-names = "fck"; 610 #address-cells = <3>; 611 #size-cells = <2>; 612 bus-range = <0x0 0xff>; 613 cdns,no-bar-match-nbits = <64>; 614 vendor-id = <0x104c>; 615 device-id = <0xb00f>; 616 msi-map = <0x0 &gic_its 0x0 0x10000>; 617 dma-coherent; 618 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, 619 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; 620 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 621 }; 622 623 pcie1_ep: pcie-ep@2910000 { 624 compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; 625 reg = <0x00 0x02910000 0x00 0x1000>, 626 <0x00 0x02917000 0x00 0x400>, 627 <0x00 0x0d800000 0x00 0x00800000>, 628 <0x00 0x18000000 0x00 0x08000000>; 629 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 630 interrupt-names = "link_state"; 631 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 632 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>; 633 max-link-speed = <3>; 634 num-lanes = <4>; 635 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>; 636 clocks = <&k3_clks 240 6>; 637 clock-names = "fck"; 638 max-functions = /bits/ 8 <6>; 639 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; 640 dma-coherent; 641 }; 642 643 usbss0: cdns-usb@4104000 { 644 compatible = "ti,j721e-usb"; 645 reg = <0x00 0x4104000 0x00 0x100>; 646 dma-coherent; 647 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; 648 clocks = <&k3_clks 288 12>, <&k3_clks 288 3>; 649 clock-names = "ref", "lpm"; 650 assigned-clocks = <&k3_clks 288 12>; /* USB2_REFCLK */ 651 assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */ 652 #address-cells = <2>; 653 #size-cells = <2>; 654 ranges; 655 656 usb0: usb@6000000 { 657 compatible = "cdns,usb3"; 658 reg = <0x00 0x6000000 0x00 0x10000>, 659 <0x00 0x6010000 0x00 0x10000>, 660 <0x00 0x6020000 0x00 0x10000>; 661 reg-names = "otg", "xhci", "dev"; 662 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 663 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 664 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 665 interrupt-names = "host", 666 "peripheral", 667 "otg"; 668 maximum-speed = "super-speed"; 669 dr_mode = "otg"; 670 cdns,phyrst-a-enable; 671 }; 672 }; 673 674 main_gpio0: gpio@600000 { 675 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 676 reg = <0x00 0x00600000 0x00 0x100>; 677 gpio-controller; 678 #gpio-cells = <2>; 679 interrupt-parent = <&main_gpio_intr>; 680 interrupts = <145>, <146>, <147>, <148>, 681 <149>; 682 interrupt-controller; 683 #interrupt-cells = <2>; 684 ti,ngpio = <69>; 685 ti,davinci-gpio-unbanked = <0>; 686 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 687 clocks = <&k3_clks 105 0>; 688 clock-names = "gpio"; 689 }; 690 691 main_gpio2: gpio@610000 { 692 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 693 reg = <0x00 0x00610000 0x00 0x100>; 694 gpio-controller; 695 #gpio-cells = <2>; 696 interrupt-parent = <&main_gpio_intr>; 697 interrupts = <154>, <155>, <156>, <157>, 698 <158>; 699 interrupt-controller; 700 #interrupt-cells = <2>; 701 ti,ngpio = <69>; 702 ti,davinci-gpio-unbanked = <0>; 703 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 704 clocks = <&k3_clks 107 0>; 705 clock-names = "gpio"; 706 }; 707 708 main_gpio4: gpio@620000 { 709 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 710 reg = <0x00 0x00620000 0x00 0x100>; 711 gpio-controller; 712 #gpio-cells = <2>; 713 interrupt-parent = <&main_gpio_intr>; 714 interrupts = <163>, <164>, <165>, <166>, 715 <167>; 716 interrupt-controller; 717 #interrupt-cells = <2>; 718 ti,ngpio = <69>; 719 ti,davinci-gpio-unbanked = <0>; 720 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 721 clocks = <&k3_clks 109 0>; 722 clock-names = "gpio"; 723 }; 724 725 main_gpio6: gpio@630000 { 726 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 727 reg = <0x00 0x00630000 0x00 0x100>; 728 gpio-controller; 729 #gpio-cells = <2>; 730 interrupt-parent = <&main_gpio_intr>; 731 interrupts = <172>, <173>, <174>, <175>, 732 <176>; 733 interrupt-controller; 734 #interrupt-cells = <2>; 735 ti,ngpio = <69>; 736 ti,davinci-gpio-unbanked = <0>; 737 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 738 clocks = <&k3_clks 111 0>; 739 clock-names = "gpio"; 740 }; 741 742 main_r5fss0: r5fss@5c00000 { 743 compatible = "ti,j7200-r5fss"; 744 ti,cluster-mode = <1>; 745 #address-cells = <1>; 746 #size-cells = <1>; 747 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 748 <0x5d00000 0x00 0x5d00000 0x20000>; 749 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; 750 751 main_r5fss0_core0: r5f@5c00000 { 752 compatible = "ti,j7200-r5f"; 753 reg = <0x5c00000 0x00010000>, 754 <0x5c10000 0x00010000>; 755 reg-names = "atcm", "btcm"; 756 ti,sci = <&dmsc>; 757 ti,sci-dev-id = <245>; 758 ti,sci-proc-ids = <0x06 0xff>; 759 resets = <&k3_reset 245 1>; 760 firmware-name = "j7200-main-r5f0_0-fw"; 761 ti,atcm-enable = <1>; 762 ti,btcm-enable = <1>; 763 ti,loczrama = <1>; 764 }; 765 766 main_r5fss0_core1: r5f@5d00000 { 767 compatible = "ti,j7200-r5f"; 768 reg = <0x5d00000 0x00008000>, 769 <0x5d10000 0x00008000>; 770 reg-names = "atcm", "btcm"; 771 ti,sci = <&dmsc>; 772 ti,sci-dev-id = <246>; 773 ti,sci-proc-ids = <0x07 0xff>; 774 resets = <&k3_reset 246 1>; 775 firmware-name = "j7200-main-r5f0_1-fw"; 776 ti,atcm-enable = <1>; 777 ti,btcm-enable = <1>; 778 ti,loczrama = <1>; 779 }; 780 }; 781};