cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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asm-uaccess.h (2391B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2#ifndef __ASM_ASM_UACCESS_H
      3#define __ASM_ASM_UACCESS_H
      4
      5#include <asm/alternative-macros.h>
      6#include <asm/asm-extable.h>
      7#include <asm/assembler.h>
      8#include <asm/kernel-pgtable.h>
      9#include <asm/mmu.h>
     10#include <asm/sysreg.h>
     11
     12/*
     13 * User access enabling/disabling macros.
     14 */
     15#ifdef CONFIG_ARM64_SW_TTBR0_PAN
     16	.macro	__uaccess_ttbr0_disable, tmp1
     17	mrs	\tmp1, ttbr1_el1			// swapper_pg_dir
     18	bic	\tmp1, \tmp1, #TTBR_ASID_MASK
     19	sub	\tmp1, \tmp1, #RESERVED_SWAPPER_OFFSET	// reserved_pg_dir
     20	msr	ttbr0_el1, \tmp1			// set reserved TTBR0_EL1
     21	isb
     22	add	\tmp1, \tmp1, #RESERVED_SWAPPER_OFFSET
     23	msr	ttbr1_el1, \tmp1		// set reserved ASID
     24	isb
     25	.endm
     26
     27	.macro	__uaccess_ttbr0_enable, tmp1, tmp2
     28	get_current_task \tmp1
     29	ldr	\tmp1, [\tmp1, #TSK_TI_TTBR0]	// load saved TTBR0_EL1
     30	mrs	\tmp2, ttbr1_el1
     31	extr    \tmp2, \tmp2, \tmp1, #48
     32	ror     \tmp2, \tmp2, #16
     33	msr	ttbr1_el1, \tmp2		// set the active ASID
     34	isb
     35	msr	ttbr0_el1, \tmp1		// set the non-PAN TTBR0_EL1
     36	isb
     37	.endm
     38
     39	.macro	uaccess_ttbr0_disable, tmp1, tmp2
     40alternative_if_not ARM64_HAS_PAN
     41	save_and_disable_irq \tmp2		// avoid preemption
     42	__uaccess_ttbr0_disable \tmp1
     43	restore_irq \tmp2
     44alternative_else_nop_endif
     45	.endm
     46
     47	.macro	uaccess_ttbr0_enable, tmp1, tmp2, tmp3
     48alternative_if_not ARM64_HAS_PAN
     49	save_and_disable_irq \tmp3		// avoid preemption
     50	__uaccess_ttbr0_enable \tmp1, \tmp2
     51	restore_irq \tmp3
     52alternative_else_nop_endif
     53	.endm
     54#else
     55	.macro	uaccess_ttbr0_disable, tmp1, tmp2
     56	.endm
     57
     58	.macro	uaccess_ttbr0_enable, tmp1, tmp2, tmp3
     59	.endm
     60#endif
     61
     62#define USER(l, x...)				\
     639999:	x;					\
     64	_asm_extable	9999b, l
     65
     66/*
     67 * Generate the assembly for LDTR/STTR with exception table entries.
     68 * This is complicated as there is no post-increment or pair versions of the
     69 * unprivileged instructions, and USER() only works for single instructions.
     70 */
     71	.macro user_ldp l, reg1, reg2, addr, post_inc
     728888:		ldtr	\reg1, [\addr];
     738889:		ldtr	\reg2, [\addr, #8];
     74		add	\addr, \addr, \post_inc;
     75
     76		_asm_extable	8888b,\l;
     77		_asm_extable	8889b,\l;
     78	.endm
     79
     80	.macro user_stp l, reg1, reg2, addr, post_inc
     818888:		sttr	\reg1, [\addr];
     828889:		sttr	\reg2, [\addr, #8];
     83		add	\addr, \addr, \post_inc;
     84
     85		_asm_extable	8888b,\l;
     86		_asm_extable	8889b,\l;
     87	.endm
     88
     89	.macro user_ldst l, inst, reg, addr, post_inc
     908888:		\inst		\reg, [\addr];
     91		add		\addr, \addr, \post_inc;
     92
     93		_asm_extable	8888b,\l;
     94	.endm
     95#endif