cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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cache.h (3460B)

      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * Copyright (C) 2012 ARM Ltd.
      4 */
      5#ifndef __ASM_CACHE_H
      6#define __ASM_CACHE_H
      7
      8#include <asm/cputype.h>
      9#include <asm/mte-def.h>
     10
     11#define CTR_L1IP_SHIFT		14
     12#define CTR_L1IP_MASK		3
     13#define CTR_DMINLINE_SHIFT	16
     14#define CTR_IMINLINE_SHIFT	0
     15#define CTR_IMINLINE_MASK	0xf
     16#define CTR_ERG_SHIFT		20
     17#define CTR_CWG_SHIFT		24
     18#define CTR_CWG_MASK		15
     19#define CTR_IDC_SHIFT		28
     20#define CTR_DIC_SHIFT		29
     21
     22#define CTR_CACHE_MINLINE_MASK	\
     23	(0xf << CTR_DMINLINE_SHIFT | CTR_IMINLINE_MASK << CTR_IMINLINE_SHIFT)
     24
     25#define CTR_L1IP(ctr)		(((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
     26
     27#define ICACHE_POLICY_VPIPT	0
     28#define ICACHE_POLICY_RESERVED	1
     29#define ICACHE_POLICY_VIPT	2
     30#define ICACHE_POLICY_PIPT	3
     31
     32#define L1_CACHE_SHIFT		(6)
     33#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
     34
     35
     36#define CLIDR_LOUU_SHIFT	27
     37#define CLIDR_LOC_SHIFT		24
     38#define CLIDR_LOUIS_SHIFT	21
     39
     40#define CLIDR_LOUU(clidr)	(((clidr) >> CLIDR_LOUU_SHIFT) & 0x7)
     41#define CLIDR_LOC(clidr)	(((clidr) >> CLIDR_LOC_SHIFT) & 0x7)
     42#define CLIDR_LOUIS(clidr)	(((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7)
     43
     44/*
     45 * Memory returned by kmalloc() may be used for DMA, so we must make
     46 * sure that all such allocations are cache aligned. Otherwise,
     47 * unrelated code may cause parts of the buffer to be read into the
     48 * cache before the transfer is done, causing old data to be seen by
     49 * the CPU.
     50 */
     51#define ARCH_DMA_MINALIGN	(128)
     52
     53#ifndef __ASSEMBLY__
     54
     55#include <linux/bitops.h>
     56#include <linux/kasan-enabled.h>
     57
     58#ifdef CONFIG_KASAN_SW_TAGS
     59#define ARCH_SLAB_MINALIGN	(1ULL << KASAN_SHADOW_SCALE_SHIFT)
     60#elif defined(CONFIG_KASAN_HW_TAGS)
     61static inline unsigned int arch_slab_minalign(void)
     62{
     63	return kasan_hw_tags_enabled() ? MTE_GRANULE_SIZE :
     64					 __alignof__(unsigned long long);
     65}
     66#define arch_slab_minalign() arch_slab_minalign()
     67#endif
     68
     69#define ICACHEF_ALIASING	0
     70#define ICACHEF_VPIPT		1
     71extern unsigned long __icache_flags;
     72
     73/*
     74 * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
     75 * permitted in the I-cache.
     76 */
     77static inline int icache_is_aliasing(void)
     78{
     79	return test_bit(ICACHEF_ALIASING, &__icache_flags);
     80}
     81
     82static __always_inline int icache_is_vpipt(void)
     83{
     84	return test_bit(ICACHEF_VPIPT, &__icache_flags);
     85}
     86
     87static inline u32 cache_type_cwg(void)
     88{
     89	return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
     90}
     91
     92#define __read_mostly __section(".data..read_mostly")
     93
     94static inline int cache_line_size_of_cpu(void)
     95{
     96	u32 cwg = cache_type_cwg();
     97
     98	return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
     99}
    100
    101int cache_line_size(void);
    102
    103/*
    104 * Read the effective value of CTR_EL0.
    105 *
    106 * According to ARM ARM for ARMv8-A (ARM DDI 0487C.a),
    107 * section D10.2.33 "CTR_EL0, Cache Type Register" :
    108 *
    109 * CTR_EL0.IDC reports the data cache clean requirements for
    110 * instruction to data coherence.
    111 *
    112 *  0 - dcache clean to PoU is required unless :
    113 *     (CLIDR_EL1.LoC == 0) || (CLIDR_EL1.LoUIS == 0 && CLIDR_EL1.LoUU == 0)
    114 *  1 - dcache clean to PoU is not required for i-to-d coherence.
    115 *
    116 * This routine provides the CTR_EL0 with the IDC field updated to the
    117 * effective state.
    118 */
    119static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void)
    120{
    121	u32 ctr = read_cpuid_cachetype();
    122
    123	if (!(ctr & BIT(CTR_IDC_SHIFT))) {
    124		u64 clidr = read_sysreg(clidr_el1);
    125
    126		if (CLIDR_LOC(clidr) == 0 ||
    127		    (CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0))
    128			ctr |= BIT(CTR_IDC_SHIFT);
    129	}
    130
    131	return ctr;
    132}
    133
    134#endif	/* __ASSEMBLY__ */
    135
    136#endif