fpsimd.h (10522B)
1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (C) 2012 ARM Ltd. 4 */ 5#ifndef __ASM_FP_H 6#define __ASM_FP_H 7 8#include <asm/errno.h> 9#include <asm/ptrace.h> 10#include <asm/processor.h> 11#include <asm/sigcontext.h> 12#include <asm/sysreg.h> 13 14#ifndef __ASSEMBLY__ 15 16#include <linux/bitmap.h> 17#include <linux/build_bug.h> 18#include <linux/bug.h> 19#include <linux/cache.h> 20#include <linux/init.h> 21#include <linux/stddef.h> 22#include <linux/types.h> 23 24#ifdef CONFIG_COMPAT 25/* Masks for extracting the FPSR and FPCR from the FPSCR */ 26#define VFP_FPSCR_STAT_MASK 0xf800009f 27#define VFP_FPSCR_CTRL_MASK 0x07f79f00 28/* 29 * The VFP state has 32x64-bit registers and a single 32-bit 30 * control/status register. 31 */ 32#define VFP_STATE_SIZE ((32 * 8) + 4) 33#endif 34 35/* 36 * When we defined the maximum SVE vector length we defined the ABI so 37 * that the maximum vector length included all the reserved for future 38 * expansion bits in ZCR rather than those just currently defined by 39 * the architecture. While SME follows a similar pattern the fact that 40 * it includes a square matrix means that any allocations that attempt 41 * to cover the maximum potential vector length (such as happen with 42 * the regset used for ptrace) end up being extremely large. Define 43 * the much lower actual limit for use in such situations. 44 */ 45#define SME_VQ_MAX 16 46 47struct task_struct; 48 49extern void fpsimd_save_state(struct user_fpsimd_state *state); 50extern void fpsimd_load_state(struct user_fpsimd_state *state); 51 52extern void fpsimd_thread_switch(struct task_struct *next); 53extern void fpsimd_flush_thread(void); 54 55extern void fpsimd_signal_preserve_current_state(void); 56extern void fpsimd_preserve_current_state(void); 57extern void fpsimd_restore_current_state(void); 58extern void fpsimd_update_current_state(struct user_fpsimd_state const *state); 59 60extern void fpsimd_bind_state_to_cpu(struct user_fpsimd_state *state, 61 void *sve_state, unsigned int sve_vl, 62 void *za_state, unsigned int sme_vl, 63 u64 *svcr); 64 65extern void fpsimd_flush_task_state(struct task_struct *target); 66extern void fpsimd_save_and_flush_cpu_state(void); 67 68static inline bool thread_sm_enabled(struct thread_struct *thread) 69{ 70 return system_supports_sme() && (thread->svcr & SVCR_SM_MASK); 71} 72 73static inline bool thread_za_enabled(struct thread_struct *thread) 74{ 75 return system_supports_sme() && (thread->svcr & SVCR_ZA_MASK); 76} 77 78/* Maximum VL that SVE/SME VL-agnostic software can transparently support */ 79#define VL_ARCH_MAX 0x100 80 81/* Offset of FFR in the SVE register dump */ 82static inline size_t sve_ffr_offset(int vl) 83{ 84 return SVE_SIG_FFR_OFFSET(sve_vq_from_vl(vl)) - SVE_SIG_REGS_OFFSET; 85} 86 87static inline void *sve_pffr(struct thread_struct *thread) 88{ 89 unsigned int vl; 90 91 if (system_supports_sme() && thread_sm_enabled(thread)) 92 vl = thread_get_sme_vl(thread); 93 else 94 vl = thread_get_sve_vl(thread); 95 96 return (char *)thread->sve_state + sve_ffr_offset(vl); 97} 98 99extern void sve_save_state(void *state, u32 *pfpsr, int save_ffr); 100extern void sve_load_state(void const *state, u32 const *pfpsr, 101 int restore_ffr); 102extern void sve_flush_live(bool flush_ffr, unsigned long vq_minus_1); 103extern unsigned int sve_get_vl(void); 104extern void sve_set_vq(unsigned long vq_minus_1); 105extern void sme_set_vq(unsigned long vq_minus_1); 106extern void za_save_state(void *state); 107extern void za_load_state(void const *state); 108 109struct arm64_cpu_capabilities; 110extern void sve_kernel_enable(const struct arm64_cpu_capabilities *__unused); 111extern void sme_kernel_enable(const struct arm64_cpu_capabilities *__unused); 112extern void fa64_kernel_enable(const struct arm64_cpu_capabilities *__unused); 113 114extern u64 read_zcr_features(void); 115extern u64 read_smcr_features(void); 116 117/* 118 * Helpers to translate bit indices in sve_vq_map to VQ values (and 119 * vice versa). This allows find_next_bit() to be used to find the 120 * _maximum_ VQ not exceeding a certain value. 121 */ 122static inline unsigned int __vq_to_bit(unsigned int vq) 123{ 124 return SVE_VQ_MAX - vq; 125} 126 127static inline unsigned int __bit_to_vq(unsigned int bit) 128{ 129 return SVE_VQ_MAX - bit; 130} 131 132 133struct vl_info { 134 enum vec_type type; 135 const char *name; /* For display purposes */ 136 137 /* Minimum supported vector length across all CPUs */ 138 int min_vl; 139 140 /* Maximum supported vector length across all CPUs */ 141 int max_vl; 142 int max_virtualisable_vl; 143 144 /* 145 * Set of available vector lengths, 146 * where length vq encoded as bit __vq_to_bit(vq): 147 */ 148 DECLARE_BITMAP(vq_map, SVE_VQ_MAX); 149 150 /* Set of vector lengths present on at least one cpu: */ 151 DECLARE_BITMAP(vq_partial_map, SVE_VQ_MAX); 152}; 153 154#ifdef CONFIG_ARM64_SVE 155 156extern void sve_alloc(struct task_struct *task); 157extern void fpsimd_release_task(struct task_struct *task); 158extern void fpsimd_sync_to_sve(struct task_struct *task); 159extern void fpsimd_force_sync_to_sve(struct task_struct *task); 160extern void sve_sync_to_fpsimd(struct task_struct *task); 161extern void sve_sync_from_fpsimd_zeropad(struct task_struct *task); 162 163extern int vec_set_vector_length(struct task_struct *task, enum vec_type type, 164 unsigned long vl, unsigned long flags); 165 166extern int sve_set_current_vl(unsigned long arg); 167extern int sve_get_current_vl(void); 168 169static inline void sve_user_disable(void) 170{ 171 sysreg_clear_set(cpacr_el1, CPACR_EL1_ZEN_EL0EN, 0); 172} 173 174static inline void sve_user_enable(void) 175{ 176 sysreg_clear_set(cpacr_el1, 0, CPACR_EL1_ZEN_EL0EN); 177} 178 179#define sve_cond_update_zcr_vq(val, reg) \ 180 do { \ 181 u64 __zcr = read_sysreg_s((reg)); \ 182 u64 __new = __zcr & ~ZCR_ELx_LEN_MASK; \ 183 __new |= (val) & ZCR_ELx_LEN_MASK; \ 184 if (__zcr != __new) \ 185 write_sysreg_s(__new, (reg)); \ 186 } while (0) 187 188/* 189 * Probing and setup functions. 190 * Calls to these functions must be serialised with one another. 191 */ 192enum vec_type; 193 194extern void __init vec_init_vq_map(enum vec_type type); 195extern void vec_update_vq_map(enum vec_type type); 196extern int vec_verify_vq_map(enum vec_type type); 197extern void __init sve_setup(void); 198 199extern __ro_after_init struct vl_info vl_info[ARM64_VEC_MAX]; 200 201static inline void write_vl(enum vec_type type, u64 val) 202{ 203 u64 tmp; 204 205 switch (type) { 206#ifdef CONFIG_ARM64_SVE 207 case ARM64_VEC_SVE: 208 tmp = read_sysreg_s(SYS_ZCR_EL1) & ~ZCR_ELx_LEN_MASK; 209 write_sysreg_s(tmp | val, SYS_ZCR_EL1); 210 break; 211#endif 212#ifdef CONFIG_ARM64_SME 213 case ARM64_VEC_SME: 214 tmp = read_sysreg_s(SYS_SMCR_EL1) & ~SMCR_ELx_LEN_MASK; 215 write_sysreg_s(tmp | val, SYS_SMCR_EL1); 216 break; 217#endif 218 default: 219 WARN_ON_ONCE(1); 220 break; 221 } 222} 223 224static inline int vec_max_vl(enum vec_type type) 225{ 226 return vl_info[type].max_vl; 227} 228 229static inline int vec_max_virtualisable_vl(enum vec_type type) 230{ 231 return vl_info[type].max_virtualisable_vl; 232} 233 234static inline int sve_max_vl(void) 235{ 236 return vec_max_vl(ARM64_VEC_SVE); 237} 238 239static inline int sve_max_virtualisable_vl(void) 240{ 241 return vec_max_virtualisable_vl(ARM64_VEC_SVE); 242} 243 244/* Ensure vq >= SVE_VQ_MIN && vq <= SVE_VQ_MAX before calling this function */ 245static inline bool vq_available(enum vec_type type, unsigned int vq) 246{ 247 return test_bit(__vq_to_bit(vq), vl_info[type].vq_map); 248} 249 250static inline bool sve_vq_available(unsigned int vq) 251{ 252 return vq_available(ARM64_VEC_SVE, vq); 253} 254 255size_t sve_state_size(struct task_struct const *task); 256 257#else /* ! CONFIG_ARM64_SVE */ 258 259static inline void sve_alloc(struct task_struct *task) { } 260static inline void fpsimd_release_task(struct task_struct *task) { } 261static inline void sve_sync_to_fpsimd(struct task_struct *task) { } 262static inline void sve_sync_from_fpsimd_zeropad(struct task_struct *task) { } 263 264static inline int sve_max_virtualisable_vl(void) 265{ 266 return 0; 267} 268 269static inline int sve_set_current_vl(unsigned long arg) 270{ 271 return -EINVAL; 272} 273 274static inline int sve_get_current_vl(void) 275{ 276 return -EINVAL; 277} 278 279static inline int sve_max_vl(void) 280{ 281 return -EINVAL; 282} 283 284static inline bool sve_vq_available(unsigned int vq) { return false; } 285 286static inline void sve_user_disable(void) { BUILD_BUG(); } 287static inline void sve_user_enable(void) { BUILD_BUG(); } 288 289#define sve_cond_update_zcr_vq(val, reg) do { } while (0) 290 291static inline void vec_init_vq_map(enum vec_type t) { } 292static inline void vec_update_vq_map(enum vec_type t) { } 293static inline int vec_verify_vq_map(enum vec_type t) { return 0; } 294static inline void sve_setup(void) { } 295 296static inline size_t sve_state_size(struct task_struct const *task) 297{ 298 return 0; 299} 300 301#endif /* ! CONFIG_ARM64_SVE */ 302 303#ifdef CONFIG_ARM64_SME 304 305static inline void sme_user_disable(void) 306{ 307 sysreg_clear_set(cpacr_el1, CPACR_EL1_SMEN_EL0EN, 0); 308} 309 310static inline void sme_user_enable(void) 311{ 312 sysreg_clear_set(cpacr_el1, 0, CPACR_EL1_SMEN_EL0EN); 313} 314 315static inline void sme_smstart_sm(void) 316{ 317 asm volatile(__msr_s(SYS_SVCR_SMSTART_SM_EL0, "xzr")); 318} 319 320static inline void sme_smstop_sm(void) 321{ 322 asm volatile(__msr_s(SYS_SVCR_SMSTOP_SM_EL0, "xzr")); 323} 324 325static inline void sme_smstop(void) 326{ 327 asm volatile(__msr_s(SYS_SVCR_SMSTOP_SMZA_EL0, "xzr")); 328} 329 330extern void __init sme_setup(void); 331 332static inline int sme_max_vl(void) 333{ 334 return vec_max_vl(ARM64_VEC_SME); 335} 336 337static inline int sme_max_virtualisable_vl(void) 338{ 339 return vec_max_virtualisable_vl(ARM64_VEC_SME); 340} 341 342extern void sme_alloc(struct task_struct *task); 343extern unsigned int sme_get_vl(void); 344extern int sme_set_current_vl(unsigned long arg); 345extern int sme_get_current_vl(void); 346 347/* 348 * Return how many bytes of memory are required to store the full SME 349 * specific state (currently just ZA) for task, given task's currently 350 * configured vector length. 351 */ 352static inline size_t za_state_size(struct task_struct const *task) 353{ 354 unsigned int vl = task_get_sme_vl(task); 355 356 return ZA_SIG_REGS_SIZE(sve_vq_from_vl(vl)); 357} 358 359#else 360 361static inline void sme_user_disable(void) { BUILD_BUG(); } 362static inline void sme_user_enable(void) { BUILD_BUG(); } 363 364static inline void sme_smstart_sm(void) { } 365static inline void sme_smstop_sm(void) { } 366static inline void sme_smstop(void) { } 367 368static inline void sme_alloc(struct task_struct *task) { } 369static inline void sme_setup(void) { } 370static inline unsigned int sme_get_vl(void) { return 0; } 371static inline int sme_max_vl(void) { return 0; } 372static inline int sme_max_virtualisable_vl(void) { return 0; } 373static inline int sme_set_current_vl(unsigned long arg) { return -EINVAL; } 374static inline int sme_get_current_vl(void) { return -EINVAL; } 375 376static inline size_t za_state_size(struct task_struct const *task) 377{ 378 return 0; 379} 380 381#endif /* ! CONFIG_ARM64_SME */ 382 383/* For use by EFI runtime services calls only */ 384extern void __efi_fpsimd_begin(void); 385extern void __efi_fpsimd_end(void); 386 387#endif 388 389#endif