cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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kvm_mte.h (1378B)


      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * Copyright (C) 2020-2021 ARM Ltd.
      4 */
      5#ifndef __ASM_KVM_MTE_H
      6#define __ASM_KVM_MTE_H
      7
      8#ifdef __ASSEMBLY__
      9
     10#include <asm/sysreg.h>
     11
     12#ifdef CONFIG_ARM64_MTE
     13
     14.macro mte_switch_to_guest g_ctxt, h_ctxt, reg1
     15alternative_if_not ARM64_MTE
     16	b	.L__skip_switch\@
     17alternative_else_nop_endif
     18	mrs	\reg1, hcr_el2
     19	tbz	\reg1, #(HCR_ATA_SHIFT), .L__skip_switch\@
     20
     21	mrs_s	\reg1, SYS_RGSR_EL1
     22	str	\reg1, [\h_ctxt, #CPU_RGSR_EL1]
     23	mrs_s	\reg1, SYS_GCR_EL1
     24	str	\reg1, [\h_ctxt, #CPU_GCR_EL1]
     25
     26	ldr	\reg1, [\g_ctxt, #CPU_RGSR_EL1]
     27	msr_s	SYS_RGSR_EL1, \reg1
     28	ldr	\reg1, [\g_ctxt, #CPU_GCR_EL1]
     29	msr_s	SYS_GCR_EL1, \reg1
     30
     31.L__skip_switch\@:
     32.endm
     33
     34.macro mte_switch_to_hyp g_ctxt, h_ctxt, reg1
     35alternative_if_not ARM64_MTE
     36	b	.L__skip_switch\@
     37alternative_else_nop_endif
     38	mrs	\reg1, hcr_el2
     39	tbz	\reg1, #(HCR_ATA_SHIFT), .L__skip_switch\@
     40
     41	mrs_s	\reg1, SYS_RGSR_EL1
     42	str	\reg1, [\g_ctxt, #CPU_RGSR_EL1]
     43	mrs_s	\reg1, SYS_GCR_EL1
     44	str	\reg1, [\g_ctxt, #CPU_GCR_EL1]
     45
     46	ldr	\reg1, [\h_ctxt, #CPU_RGSR_EL1]
     47	msr_s	SYS_RGSR_EL1, \reg1
     48	ldr	\reg1, [\h_ctxt, #CPU_GCR_EL1]
     49	msr_s	SYS_GCR_EL1, \reg1
     50
     51	isb
     52
     53.L__skip_switch\@:
     54.endm
     55
     56#else /* !CONFIG_ARM64_MTE */
     57
     58.macro mte_switch_to_guest g_ctxt, h_ctxt, reg1
     59.endm
     60
     61.macro mte_switch_to_hyp g_ctxt, h_ctxt, reg1
     62.endm
     63
     64#endif /* CONFIG_ARM64_MTE */
     65#endif /* __ASSEMBLY__ */
     66#endif /* __ASM_KVM_MTE_H */