cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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cpu-reset.S (1358B)


      1/* SPDX-License-Identifier: GPL-2.0-only */
      2/*
      3 * CPU reset routines
      4 *
      5 * Copyright (C) 2001 Deep Blue Solutions Ltd.
      6 * Copyright (C) 2012 ARM Ltd.
      7 * Copyright (C) 2015 Huawei Futurewei Technologies.
      8 */
      9
     10#include <linux/linkage.h>
     11#include <asm/assembler.h>
     12#include <asm/sysreg.h>
     13#include <asm/virt.h>
     14
     15.text
     16.pushsection    .idmap.text, "awx"
     17
     18/*
     19 * cpu_soft_restart(el2_switch, entry, arg0, arg1, arg2)
     20 *
     21 * @el2_switch: Flag to indicate a switch to EL2 is needed.
     22 * @entry: Location to jump to for soft reset.
     23 * arg0: First argument passed to @entry. (relocation list)
     24 * arg1: Second argument passed to @entry.(physical kernel entry)
     25 * arg2: Third argument passed to @entry. (physical dtb address)
     26 *
     27 * Put the CPU into the same state as it would be if it had been reset, and
     28 * branch to what would be the reset vector. It must be executed with the
     29 * flat identity mapping.
     30 */
     31SYM_CODE_START(cpu_soft_restart)
     32	mov_q	x12, INIT_SCTLR_EL1_MMU_OFF
     33	pre_disable_mmu_workaround
     34	/*
     35	 * either disable EL1&0 translation regime or disable EL2&0 translation
     36	 * regime if HCR_EL2.E2H == 1
     37	 */
     38	msr	sctlr_el1, x12
     39	isb
     40
     41	cbz	x0, 1f				// el2_switch?
     42	mov	x0, #HVC_SOFT_RESTART
     43	hvc	#0				// no return
     44
     451:	mov	x8, x1				// entry
     46	mov	x0, x2				// arg0
     47	mov	x1, x3				// arg1
     48	mov	x2, x4				// arg2
     49	br	x8
     50SYM_CODE_END(cpu_soft_restart)
     51
     52.popsection