cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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sigreturn32.S (1330B)

      1/* SPDX-License-Identifier: GPL-2.0 */
      2/*
      3 * AArch32 sigreturn code.
      4 * Based on the kuser helpers in arch/arm/kernel/entry-armv.S.
      5 *
      6 * Copyright (C) 2005-2011 Nicolas Pitre <nico@fluxnic.net>
      7 * Copyright (C) 2012-2018 ARM Ltd.
      8 *
      9 * For ARM syscalls, the syscall number has to be loaded into r7.
     10 * We do not support an OABI userspace.
     11 *
     12 * For Thumb syscalls, we also pass the syscall number via r7. We therefore
     13 * need two 16-bit instructions.
     14 */
     15
     16#include <asm/unistd.h>
     17
     18	.globl __aarch32_sigret_code_start
     19__aarch32_sigret_code_start:
     20
     21	/*
     22	 * ARM Code
     23	 */
     24	.byte	__NR_compat_sigreturn, 0x70, 0xa0, 0xe3		// mov	r7, #__NR_compat_sigreturn
     25	.byte	__NR_compat_sigreturn, 0x00, 0x00, 0xef		// svc	#__NR_compat_sigreturn
     26
     27	/*
     28	 * Thumb code
     29	 */
     30	.byte	__NR_compat_sigreturn, 0x27			// svc	#__NR_compat_sigreturn
     31	.byte	__NR_compat_sigreturn, 0xdf			// mov	r7, #__NR_compat_sigreturn
     32
     33	/*
     34	 * ARM code
     35	 */
     36	.byte	__NR_compat_rt_sigreturn, 0x70, 0xa0, 0xe3	// mov	r7, #__NR_compat_rt_sigreturn
     37	.byte	__NR_compat_rt_sigreturn, 0x00, 0x00, 0xef	// svc	#__NR_compat_rt_sigreturn
     38
     39	/*
     40	 * Thumb code
     41	 */
     42	.byte	__NR_compat_rt_sigreturn, 0x27			// svc	#__NR_compat_rt_sigreturn
     43	.byte	__NR_compat_rt_sigreturn, 0xdf			// mov	r7, #__NR_compat_rt_sigreturn
     44
     45        .globl __aarch32_sigret_code_end
     46__aarch32_sigret_code_end: