cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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dma-mapping.c (1337B)


      1// SPDX-License-Identifier: GPL-2.0-only
      2/*
      3 * Copyright (C) 2012 ARM Ltd.
      4 * Author: Catalin Marinas <catalin.marinas@arm.com>
      5 */
      6
      7#include <linux/gfp.h>
      8#include <linux/cache.h>
      9#include <linux/dma-map-ops.h>
     10#include <linux/dma-iommu.h>
     11#include <xen/xen.h>
     12
     13#include <asm/cacheflush.h>
     14#include <asm/xen/xen-ops.h>
     15
     16void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
     17		enum dma_data_direction dir)
     18{
     19	__dma_map_area(phys_to_virt(paddr), size, dir);
     20}
     21
     22void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size,
     23		enum dma_data_direction dir)
     24{
     25	__dma_unmap_area(phys_to_virt(paddr), size, dir);
     26}
     27
     28void arch_dma_prep_coherent(struct page *page, size_t size)
     29{
     30	__dma_flush_area(page_address(page), size);
     31}
     32
     33#ifdef CONFIG_IOMMU_DMA
     34void arch_teardown_dma_ops(struct device *dev)
     35{
     36	dev->dma_ops = NULL;
     37}
     38#endif
     39
     40void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
     41			const struct iommu_ops *iommu, bool coherent)
     42{
     43	int cls = cache_line_size_of_cpu();
     44
     45	WARN_TAINT(!coherent && cls > ARCH_DMA_MINALIGN,
     46		   TAINT_CPU_OUT_OF_SPEC,
     47		   "%s %s: ARCH_DMA_MINALIGN smaller than CTR_EL0.CWG (%d < %d)",
     48		   dev_driver_string(dev), dev_name(dev),
     49		   ARCH_DMA_MINALIGN, cls);
     50
     51	dev->dma_coherent = coherent;
     52	if (iommu)
     53		iommu_setup_dma_ops(dev, dma_base, dma_base + size - 1);
     54
     55	xen_setup_dma_ops(dev);
     56}